JPH05251495A - Memory lsi - Google Patents
Memory lsiInfo
- Publication number
- JPH05251495A JPH05251495A JP4046695A JP4669592A JPH05251495A JP H05251495 A JPH05251495 A JP H05251495A JP 4046695 A JP4046695 A JP 4046695A JP 4669592 A JP4669592 A JP 4669592A JP H05251495 A JPH05251495 A JP H05251495A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- lsi
- chip
- package
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/4805—Shape
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】半導体装置のボンディングＰＡＤ
配置に関するものであり、特にＬｅａｄ Ｏｎ Ｃｈｉ
ｐパッケ−ジのボンディングＰＡＤ配置において有効で
ある。[Industrial application] Semiconductor device bonding PAD
Placement, especially Lead On Chi
This is effective in the bonding PAD arrangement of the p package.
【０００２】[0002]
【従来の技術】近年、パッケ−ジのダイアタッチ部のな
いパッケ−ジによるチップ占有面積の拡大がなされてい
る。このため、パッケ−ジの配線をチップの下面で行う
Ｃｈｉｐ Ｏｎ Ｌｅａｄ（以下ＣＯＬパッケ−ジと記
す）やチップの上面で行うＬｅａｄ Ｏｎ Ｃｈｉｐ
（以下ＬＯＣパッケ−ジと記す）等のパッケ−ジが使用
されるようになってきた。これらの構造は他のパッケ−
ジと比較して、大チップを搭載できること、高電流容量
をとれるための高速化に向く、チップのレイアウト設計
が自由になるなどのメリットをもつ。このため、メモリ
の大容量化に伴って、多ビット構成のメモリのニ−ズが
増大し、従来の１６Ｍ×１ビット、４Ｍ×４ビットから
２Ｍ×８ビット、２Ｍ×９ビットさらに１Ｍ×１６ビッ
ト、１Ｍ×１８ビットの半導体集積回路（以下ＬＳＩと
記す）が製品化されるようになってきており、また、入
出力ピン（以下Ｉ／Ｏピンと記す）の増加により、大型
のチップを限られたサイズのパッケ−ジに収納する必要
性があるため、高速化のために、最近、ＬＯＣパッケ−
ジを用いるようになってきた。2. Description of the Related Art In recent years, a chip occupying area has been expanded by a package without a die attach portion of the package. For this reason, Chip On Lead (hereinafter referred to as COL package) for wiring the package on the lower surface of the chip and Lead On Chip for wiring on the upper surface of the chip.
Packages such as (hereinafter referred to as LOC package) have come to be used. These structures are
Compared with the Ji, it has the advantages that a large chip can be mounted, it is suitable for high-speed operation to obtain high current capacity, and that the layout design of the chip is free. Therefore, as the capacity of the memory increases, the need for a multi-bit memory increases, and the conventional 16M × 1 bit, 4M × 4 bit to 2M × 8 bit, 2M × 9 bit, and 1M × 16 bit. A 1-bit × 1M × 18-bit semiconductor integrated circuit (hereinafter referred to as an LSI) is being commercialized, and due to an increase in input / output pins (hereinafter referred to as an I / O pin), a large chip is limited. Since it is necessary to store it in a package of the same size, LOC package has recently been used for speeding up.
I started to use Ji.
【０００３】ＬＯＣパッケ−ジとして、図２（ａ）にＳ
ｍａｌｌ Ｏｕｔｌｉｎｅ Ｊ−Ｌｅａｄｅｄ Ｐａｃ
ｋａｇｅ（以下ＳＯＪと記す）、図２（ｂ）にＳｍａｌ
ｌＯｕｔｌｉｎｅ Ｐａｃｋａｇｅ（以下ＳＯＰと記
す）、図２（ｃ）にＺｉｇｚａｇ ｉｎ−ｌｉｎｅ Ｐ
ａｃｋａｇｅ（以下ＺＩＰと記す）のぞれぞれの要部概
略図を示す。上記ＳＯＪは２方向リ−ドのＪ曲げパッケ
−ジで、リ−ドピッチが５０ｍｉｌのものであり、主と
してＤＲＡＭに使用されている。上記ＳＯＰは、パッケ
−ジ本体から２方向にリ−ドを引き出し、リ−ドをガル
ウィング形状に成形した表面実装形パッケ−ジであり、
リ−ドピッチは５０ｍｉｌが標準である。また、Ｔｈｉ
ｎ ＳＯＰ（以下ＴＳＯＰと記す）はパッケ−ジ本体の
短辺側からリ−ドを引き出して、パッケ−ジ高さが１．
２７ｍｍ以下のものをいい、上記ＳＯＰ，ＴＳＯＰ共に
主としてＳＲＡＭ，ＥＰＲＯＭに使用されている。ＺＩ
Ｐはリ−ドがパッケ−ジ本体から一方向に５０ｍｉｌピ
ッチで引き出され、リ−ドをパッケ−ジ面内で交互に折
り曲げ、ピンピッチを１００ｍｉｌとした構造のパッケ
−ジで主としてＤＲＡＭに使用されている。上記ＳＯ
Ｊ，ＳＯＰ，ＺＩＰ，ＴＳＯＰ等のボ−ドに両面実装す
るＬＯＣパッケ−ジ実装のＬＳＩにおいては、ボ−ド上
の配線を両面で共用するため、２種の左右のピン配置が
入れ替わったパタ−ンの異なるＬＳＩを製作し、ボ−ド
に両面実装している。As an LOC package, S is shown in FIG.
mall Outline J-Leaded Pac
Kage (hereinafter referred to as SOJ), Smal in FIG.
lOutline Package (hereinafter referred to as SOP), Zigzag in-line P in FIG.
FIG. 2 is a schematic view of the main parts of each ackage (hereinafter referred to as ZIP). The SOJ is a bi-directional lead J-bend package having a lead pitch of 50 mil and is mainly used for DRAM. The SOP is a surface mount type package in which leads are drawn out in two directions from the package body and the leads are formed into a gull wing shape.
The standard lead pitch is 50 mils. Also, Thi
n SOP (hereinafter referred to as TSOP) has a package height of 1. because the lead is pulled out from the short side of the package body.
It is a 27 mm or less, and both the SOP and TSOP are mainly used for SRAM and EPROM. ZI
P is a package in which the lead is pulled out from the package body in one direction at a pitch of 50 mils, and the leads are alternately bent in the package plane, and the pin pitch is 100 mils, which is mainly used for DRAM. ing. Above SO
In an LOC package mounting LSI that is mounted on both sides of a board such as J, SOP, ZIP, TSOP, etc., the wiring on the board is shared by both sides, so the pattern of two types of left and right pins is switched. LSIs with different cores are manufactured and mounted on both sides of the board.
【０００４】図３（ａ）にボ−ドに両面実装した場合の
４Ｍ×４ビット構成のＬＳＩのパッケ−ジとボ−ドの断
面の要部概略図を示す。パッケ−ジ１内のモ−ルド内に
はＬＳＩチップ２が設置され、上記ＬＳＩチップ２上の
ボンディングＰＡＤにはボンディングワイヤ３により、
リ−ドピン４と接続され、ボ−ド５上の外部のパタ−ン
と接続されている。図３（ｂ）に上記パッケ−ジとして
使用されるリ−ドピン配置、ボンディングワイヤ、ボン
ディングＰＡＤ配置の要部概略図を示す。Ｉ／Ｏピン、
ロウ・アドレス・ストロ−ブ信号ピン（以下ＲＡＳと記
す），カラムアドレスストロ−ブ信号ピン（以下ＣＡＳ
と記す），ライト・イネ−ブル信号ピン（以下ＷＥと記
す），アウトプット・イネ−ブル信号ピン（以下ＯＥと
記す），アドレスピン（Ａ０〜１１）、電源電圧ピン
（以下ＶCCと記す），接地電圧ピン（以下ＶSSと記
す），どの信号とも接続されてないピン（以下ＮＣと記
す）が設けられ、ボンディングワイヤ３によって、ボン
ディングＰＡＤ６に接続され、このことによって、内部
とボ−ド５上の外部パタ−ンとが接続されている。上記
パッケ−ジを両面実装するため、２つのパッケ−ジのう
ち、一方のリ−ドピンの曲げ方向を変えることによっ
て、左右対象のＬＳＩを製作し、両面実装を行ってい
る。FIG. 3 (a) shows a schematic view of a main portion of a cross section of a package and a board of an LSI having a 4M.times.4 bit structure when both sides are mounted on the board. The LSI chip 2 is installed in the mold in the package 1, and the bonding PAD on the LSI chip 2 is bonded by the bonding wire 3.
It is connected to the lead pin 4 and is connected to an external pattern on the board 5. FIG. 3 (b) shows a schematic view of the main parts of the lead pin arrangement, the bonding wire, and the bonding PAD arrangement used as the package. I / O pin,
Row address strobe signal pin (hereinafter referred to as RAS), column address strobe signal pin (hereinafter CAS)
, Write enable signal pin (hereinafter referred to as WE), output enable signal pin (hereinafter referred to as OE), address pin (A0 to 11), power supply voltage pin (hereinafter referred to as V CC ) ), A ground voltage pin (hereinafter referred to as V SS ), and a pin not connected to any signal (hereinafter referred to as NC), which are connected to the bonding PAD 6 by the bonding wire 3 and thereby the interior and the board. The external pattern on the terminal 5 is connected. In order to mount the above-mentioned package on both sides, left and right symmetrical LSIs are manufactured by changing the bending direction of one lead pin of the two packages, and are mounted on both sides.
【０００５】図４（ａ）に従来の左右対称なピン配置を
持つＬＯＣパッケ−ジの要部断面図を示す。パッケ−ジ
１のモ−ルド内にＬＳＩチップ２が配置され、ＶSS内部
のリ−ド７が配置され、外部と接続するため、ボンディ
ングＰＡＤ６はボンディングワイヤ３によってリ−ドピ
ン４と接続され、外部パタ−ンに接続されるようになっ
ている。図４（ｂ）に４Ｍ×４ビット、（ｃ）に１Ｍ×
１６ビットの上記ＬＯＣパッケ−ジに実装されたＬＳＩ
チップのリ−ドピン配置、ボンディングワイヤ、ボンデ
ィングＰＡＤ配置の要部概略図を示す。ＬＯＣパッケ−
ジを使用するＬＳＩにおいては、ボ−ド上の配線を両面
で共用するため、左右のピン配置が入れ替わった上記２
種のＬＳＩをボ−ドをはさみ、パッケ−ジを実装するこ
とによって、ボ−ド上で上下のピンの配置が一致するよ
うにしている。しかし、パッケ−ジの上下のモ−ルド厚
が大きく異なってくるため、パッケ−ジの曲げ方向を逆
にすると、応力が加わって、パッケ−ジクラックが発生
する等の問題があり、特にＴＳＯＰなど薄型のパッケ−
ジでは問題となっている。またＬＯＣパッケ−ジを用い
て、ボンディングの方向を左右切り換えることにより、
２種のＬＳＩを製作する際には、ボンディングＰＡＤを
複数列に配列すると、ボンディングワイヤを交差させて
ボンディングしなければならないため、上記ボンディン
グワイヤがショ−トする可能性があるためボンディング
ワイヤの交差は不可能である。このため、ボンディング
ＰＡＤをチップ中央に縦に一列に並べることが必要であ
り、このことによって、左右どちら側からもボンディン
グできるようにすることができるため、ボンディングの
方向を切り換えることによって、２種のＬＳＩを製作す
ることができる。しかし、この方法では、（ｃ）の１Ｍ
×１６ビットの要部概略図に示すように多ビット構成に
なることによって、Ｉ／Ｏピンが増加し、ボンディング
ＰＡＤ数も増大し、上記ボンディングＰＡＤを縦一列に
しか並べられないために、ボンディングＰＡＤが制約と
なってチップのサイズを小さくすることができないとい
う問題点がある。FIG. 4A shows a cross-sectional view of the main part of a conventional LOC package having a symmetrical pin arrangement. The LSI chip 2 is arranged in the mold of the package 1, the lead 7 inside V SS is arranged, and the bonding PAD 6 is connected to the lead pin 4 by the bonding wire 3 for connecting to the outside. It is designed to be connected to an external pattern. 4M × 4 bits in FIG. 4B and 1M × in FIG. 4C.
LSI mounted on the 16-bit LOC package
FIG. 3 is a schematic view of a main portion of a lead pin arrangement of chips, a bonding wire, and a bonding PAD arrangement. LOC package
In the LSI that uses a chip, the wiring on the board is shared on both sides, so the left and right pin arrangements are swapped.
The LSI is sandwiched between the boards and the package is mounted so that the upper and lower pins are aligned on the board. However, since the upper and lower mold thicknesses of the package are greatly different, there is a problem that stress is applied when the bending direction of the package is reversed and a package crack is generated. Especially, TSOP, etc. Thin package
It is a problem in Ji. Also, by using the LOC package to switch the bonding direction between left and right,
When the bonding PADs are arranged in a plurality of rows when manufacturing two kinds of LSIs, the bonding wires have to cross each other for bonding. Therefore, there is a possibility that the bonding wires may be short-circuited. Is impossible. Therefore, it is necessary to vertically arrange the bonding PADs in a line in the center of the chip, and this enables bonding from either the left or right side. LSI can be manufactured. However, in this method, 1M of (c)
As shown in the schematic diagram of the main part of × 16 bits, the multi-bit configuration increases the number of I / O pins and the number of bonding PADs. There is a problem that the size of the chip cannot be reduced due to PAD being a constraint.
【０００６】[0006]
【発明が解決しようとする課題】従来、ＬＯＣパッケ−
ジを用いて、リ−ド曲げによって、左右のピン配置が入
れ替わった２種のＬＳＩを製作する際、応力が加わり、
パッケ−ジクラックが発生するという問題がある。ま
た、左右どちら側からもボンディングできるようにする
ためにボンディングの方向を切り換えるという方法をと
ることによって、多ビット構成のＬＳＩのボンディング
ＰＡＤをチップ中央に縦に一列に並べ、ボンディングの
方向を切り換えなければならないため、チップのサイズ
を小さくすることができないという問題点がある。よっ
て、本発明は、上記問題点を解決するため、ボ−ド上に
両面実装するメモリＬＳＩをＬＯＣパッケ−ジを用い
て、リ−ドの曲げ方向と同じにすることによって、パッ
ケ−ジクラックを防止し高信頼度に、またボンディング
ＰＡＤを複数列にすることによって、小さなチップで実
装し、多ビットＬＳＩに対応できるようにすることを目
的とする。Conventionally, LOC packages have been used.
When manufacturing two kinds of LSIs in which the left and right pin arrangements are swapped by lead bending using a die, stress is applied,
There is a problem that package cracks occur. Also, by adopting a method of switching the bonding direction so that bonding can be performed from either the left or right side, the bonding PADs of the multi-bit LSI must be arranged vertically in a line in the center of the chip and the bonding direction must be switched. Therefore, there is a problem in that the size of the chip cannot be reduced. Therefore, according to the present invention, in order to solve the above problems, a memory LSI mounted on both sides of a board is formed in the same direction as the lead bending direction by using a LOC package, so that a package crack is prevented. It is an object of the present invention to prevent the problem with high reliability and to form a plurality of rows of bonding PADs so that they can be mounted on a small chip and can be applied to a multi-bit LSI.
【０００７】[0007]
【課題を解決するための手段】上記問題点を解決するた
めに、ＬＯＣパッケ−ジを用いるメモリＬＳＩに関し
て、各々のピンを入れ替えても機能の変わらないボンデ
ィングＰＡＤにおいては、上記ボンディングＰＡＤを２
列に配置することによって、左右対称なピン配置のＬＳ
Ｉのボンディング方向を変える。あるいは、ボンディン
グマスタ、配線マスク、ヒュ−ズ切り変え等マスタによ
って、２列に配置した２つのボンディングＰＡＤのＬＳ
Ｉ内部への結線をつなぎかえる。In order to solve the above problems, regarding a memory LSI using a LOC package, in the bonding PAD whose function does not change even if each pin is replaced, the bonding PAD is
By arranging in rows, the LS has a symmetrical pin arrangement.
Change the bonding direction of I. Alternatively, the LS of two bonding PADs arranged in two rows by a master such as a bonding master, a wiring mask, and fuse switching.
I Change the connection to the inside.
【０００８】[0008]
【作用】上記問題点を解決するために、ＬＯＣパッケ−
ジを用いるメモリＬＳＩに関して、各々のピンを入れ替
えても機能の変わらないボンディングＰＡＤにおいて
は、上記ボンディングＰＡＤを２列にすることによっ
て、小さなチップで実装することが可能となる。あるい
は、ボンディングＰＡＤによってＶSSとの電気的接続を
切り替えることにより、両面実装可能な同一ピン配置を
もつＬＳＩを製作することが可能となる。また、多ビッ
ト出力のメモリの２つのＩ／Ｏを相互に入れ替えること
によってメモリは動作上支障が発生しないので、メモリ
ＬＳＩのアドレスピンはリフレッシュアドレス及びそれ
以外のうちの２つのピンを入れ替えても動作させること
ができる。また、この入替え可能なピン同志をチップ上
に２列に、他のピンは１列に並べ、ボンディングの方向
を入れ替えることによって、同一チップでピン配置が対
称な２種のＬＳＩを作ることができる。In order to solve the above problems, the LOC package
Regarding a memory LSI using a memory chip, in a bonding PAD whose function does not change even if each pin is exchanged, by arranging the bonding PAD in two rows, it becomes possible to mount it in a small chip. Alternatively, by switching the electrical connection with V SS by the bonding PAD, it becomes possible to manufacture an LSI having the same pin arrangement that can be mounted on both sides. In addition, since the memory operation does not occur by exchanging the two I / Os of the multi-bit output memory with each other, even if the address pin of the memory LSI is replaced with the refresh address and two other pins. Can be operated. Further, by arranging the interchangeable pins in two rows on the chip and arranging the other pins in one row and exchanging the bonding directions, it is possible to make two kinds of LSIs having the same pin arrangement on the same chip. ..
【０００９】[0009]
【実施例】（実施例１）図１に同一チップでピン配置が
対称な２種の１Ｍ×１６ビット構成のＬＳＩのチップ上
でのピン配置を示す。この場合、ＶSS，ＶCC，ＲＡＳ，
ＣＡＳ，ＷＥ，ＯＥ等の外部入力信号ピンなど入れ替え
ることができないピンと接続したボンディングＰＡＤは
チップの中央に配置し、左右どちら側からでもボンディ
ングできるようにしている。また、１６ヶあるＩ／Ｏピ
ンは２列に並べられている。このとき、上記ＬＳＩのチ
ップ上のピン配置において、Ｙ軸に対して、鏡面対称な
ピン配置のＬＳＩとして考えた場合に、２列に並んだ上
記Ｉ／Ｏ同志が入れ替わることになるが、上記Ｉ／Ｏが
入れ替わると、書き込む際のチップ上のメモリセルの位
置も入れ替わることになるが、読みだしの際にも入れ替
わったメモリセルから読みだすことになるため、ＬＳＩ
の外部からみると正常に動作していることになる。ま
た、アドレスピンについても同様であり、アドレスの接
続が入れ替わると、やはり書き込むメモリセルの位置も
入れ替わることになるが、読みだす際のメモリセルも入
れ替わるため正常に動作する。しかし、ＤＲＡＭにおけ
るリフレッシュアドレスか否か、多ビット構成時にＹア
ドレスが他アドレスと同時にとりこまれるか否かなどア
ドレスは任意に入れられない場合がある。また、リフレ
ッシュアドレスはＲＡＳアドレスをとりこむことによ
り、ＲＡＳ ＯＮＬＹ リフレッシュモ−ドでリフレッ
シュするメモリセルを選択するアドレスであり、そうで
ないアドレスを入れ替えると、重複したアドレスのメモ
リセルをリフレッシュしたり、リフレッシュされないメ
モリセルが生じたりするため外部仕様として規定されて
おり、リフレッシュアドレスを入れ替えることはできな
い。本実施例では１Ｍ×１６ビット構成としているた
め、Ａ０〜Ａ１１の全てのアドレスをリフレッシュアド
レスとしているが、Ａ８〜Ａ１１をＸアドレスのみと
し、Ｙアドレスは使われていない。そして、Ｙアドレス
が上記アドレスのグル−プの内部及び他のアドレスのグ
ル−プ内であれば、アドレスの入替えはできない。(Embodiment 1) FIG. 1 shows pin arrangement on a chip of two types of 1M × 16-bit LSI having the same chip and symmetrical pin arrangement. In this case, V SS , V CC , RAS,
The bonding PAD connected to the non-replaceable pins such as external input signal pins such as CAS, WE, and OE is arranged in the center of the chip so that bonding can be performed from either the left or right side. The 16 I / O pins are arranged in two rows. At this time, in the pin arrangement on the chip of the above-mentioned LSI, if the LSI is considered to be a mirror-symmetrical pin arrangement with respect to the Y axis, the I / O comrades arranged in two rows will be exchanged. When the I / O is replaced, the position of the memory cell on the chip at the time of writing is also replaced, but at the time of reading, it is read from the replaced memory cell.
Seen from the outside, it is operating normally. The same applies to the address pins, and when the address connections are switched, the positions of the memory cells to be written are also switched, but the memory cells at the time of reading are also switched, so that they operate normally. However, there are cases where an address cannot be arbitrarily entered, such as whether or not it is a refresh address in a DRAM and whether or not a Y address is taken in at the same time as another address in a multi-bit configuration. Further, the refresh address is an address for selecting a memory cell to be refreshed in the RAS ONLY refresh mode by incorporating the RAS address, and if the other address is replaced, the memory cell of the duplicated address is not refreshed or refreshed. Since memory cells are generated, it is specified as an external specification, and refresh addresses cannot be exchanged. Since the present embodiment has a 1M × 16 bit configuration, all addresses A0 to A11 are used as refresh addresses, but only A8 to A11 are X addresses, and Y addresses are not used. If the Y address is inside the above group of addresses and within another group of addresses, the addresses cannot be exchanged.
【００１０】本実施例では、Ａ１〜Ａ７のみ２列に並べ
ているが、Ａ８〜Ａ１１のピンも２列に並べることは可
能であり、また、１Ｍ×１６ビット構成でなくても、多
ビット構成のＬＳＩにおいてもこのことは可能であ
る。。In this embodiment, only A1 to A7 are arranged in two rows, but pins A8 to A11 can also be arranged in two rows, and a multi-bit configuration is not required even if the configuration is 1M × 16 bits. This is also possible in the LSI. .
【００１１】また、各種テストモ−ドなどで、アドレス
ピンにアドレス入力以外の機能をもたせた場合には、本
実施例では、入れ替えができないのでボンディングＰＡ
Ｄを１列に並べる必要がある。In addition, when the address pins are provided with a function other than the address input in various test modes, the bonding PA cannot be replaced in this embodiment.
It is necessary to arrange D in one column.
【００１２】（実施例２）図５（ａ）に同一チップでピ
ン配置が対称なボンディングマスタを設けた２種のＬＳ
Ｉのチップ上でのピン配置の要部概略図を示す。ここで
ボンディングマスタとは、外部入力信号、アドレス信号
などの信号ピンをチップ上に２列に並べて、同一のピン
配置をもつ２種のＬＳＩを、１Ｍ×１ビット、１Ｍ×４
ビット等の動作モ−ドに切り替えるためのボンディング
ＰＡＤのことをいう。本実施例では、上記ボンディング
ＰＡＤに内部回路を切り換えるため、特に制限されない
が、ＶSSをボンディングするか何もボンディングしない
かによって２列に並んだ２つのボンディングＰＡＤ同志
の周辺回路への結線を入れ替えることによって２種のＬ
ＳＩを製作している。また、ＣＡＳ１は上記ＣＡＳ１周
辺に設けられたリ−ドピンの信号を制御するＣＡＳであ
り、ＣＡＳ２も同様に上記ＣＡＳ２周辺に設けられたリ
−ドピンの信号を制御するＣＡＳである。図５（ｂ）に
ボンディングマスタによる回路の入替え回路の要部概略
図を示す。ここでは、ＣＡＳ１，ＣＡＳ２からＡ３，Ａ
４、ＶSSまでのリ−ドピン配置を例にとっているが、ボ
ンディングマスタ８によって、スイッチ９の切り換えを
可能とし、２種のＬＳＩを製作することができる。実施
例２と実施例１とを比較すると実施例１においては、２
列に並べられるアドレスピンでの制約は回避できない。
一方、実施例２においては、上記外部入力信号、ボンデ
ィングＰＡＤも２列にならべることができ、アドレスピ
ンにおけるリフレッシュアドレスなどの制限は回避する
ことができる。また、外部入力信号、アドレスなど異な
る信号同志でも２列に並べることができる。特に制限さ
れないが、Ｉ／Ｏピンは出力回路を低インピ−ダンスに
するため、ボンディングマスタは用いずに、Ｉ／Ｏピン
同志を２列に並べている。また電源ピンについてもボン
ディングマスタによる切り替えが難しいため、左右どち
らからでもボンディングできるようにしている。本実施
例はボンディングマスタで説明したが、図５（ｃ）に示
すようにヒュ−ズ１０による切り替え、配線層のマスク
による切り替えなど他の切り替え手段でも可能である。(Embodiment 2) Two types of LS in which a bonding master having the same chip and symmetrical pin arrangement is provided in FIG.
1 shows a schematic view of a main part of a pin arrangement on an I chip. Here, the bonding master means that two types of LSIs having the same pin arrangement are formed by arranging signal pins such as external input signals and address signals in two rows on a chip, 1M × 1 bit, 1M × 4.
A bonding PAD for switching to an operation mode such as a bit. In this embodiment, since the internal circuit is switched to the bonding PAD, there is no particular limitation, but the connection of the two bonding PADs arranged in two rows to the peripheral circuit is switched depending on whether V SS is bonded or nothing is bonded. Two kinds of L
SI is produced. Further, CAS1 is a CAS for controlling a signal of a lead pin provided around the CAS1, and CAS2 is also a CAS for controlling a signal of a lead pin provided around the CAS2. FIG. 5B shows a schematic view of a main part of a circuit replacement circuit by the bonding master. Here, CAS1, CAS2 to A3, A
4, the lead pin arrangement up to V SS is taken as an example, but the bonding master 8 enables the switching of the switch 9, and two kinds of LSIs can be manufactured. Comparing Example 2 with Example 1, in Example 1, 2
The constraint on collocated address pins is unavoidable.
On the other hand, in the second embodiment, the external input signal and the bonding PAD can be arranged in two columns, and the limitation of the refresh address or the like on the address pin can be avoided. Also, different signals such as external input signals and addresses can be arranged in two columns. Although not particularly limited, the I / O pins are arranged in two rows without using a bonding master in order to make the output circuit have a low impedance. Also, since it is difficult to switch the power supply pin by the bonding master, it is possible to bond from either the left or right. Although the present embodiment has been described with respect to the bonding master, other switching means such as switching with the fuse 10 or switching with the mask of the wiring layer as shown in FIG. 5C is also possible.
【００１３】（実施例３）図６にチップ上の２列のボン
ディングＰＡＤの間にメモリアレイと上記メモリ周辺回
路をもち、ボンディングマスタによってＶSSとの結線を
切り換えることによって、両面実装可能な同一ピン配置
の２種のＬＳＩを製作することを可能とするＬＳＩのピ
ン配置の要部概略図を示す。２列のボンディングＰＡＤ
６の間にメモリアレイとメモリアレイの周辺回路１１が
チップ縦方向に２列に配置されており、実施例２と同様
にボンディングマスタ８が設けられ、ＶSSをボンディン
グするか否かによって２種のＬＳＩを製作することがで
きる。このように２列に並んだボンディングＰＡＤ６の
列の間にメモリアレイとメモリ周辺回路１１などが配置
されることによって、２つの列の間隔が離れていても実
施例１と同様にボンディングマスタを切り換えることが
でき、ピン配置、機能が同一な２種のＬＳＩを製作する
ことができる。(Embodiment 3) In FIG. 6, a memory array and the above memory peripheral circuit are provided between two rows of bonding pads on a chip, and by switching the connection with V SS by a bonding master, both sides can be mounted identically. FIG. 2 is a schematic view of a main part of an LSI pin arrangement that enables two types of LSIs having a pin arrangement to be manufactured. Two-row bonding PAD
6, the memory array and the peripheral circuits 11 of the memory array are arranged in two columns in the vertical direction of the chip, the bonding master 8 is provided as in the second embodiment, and there are two types depending on whether V SS is bonded or not. Can be manufactured. By arranging the memory array and the memory peripheral circuit 11 between the rows of the bonding PADs 6 arranged in two rows in this manner, the bonding master is switched as in the first embodiment even if the distance between the two rows is large. Therefore, it is possible to manufacture two types of LSIs having the same pin arrangement and the same function.
【００１４】（実施例４）図７に１つのピンで複数列の
ボンディングを可能とし、ボンディングマスタによっ
て、ＶSSとの結線を切り換えることによって、ピン配置
の同一な２種のＬＳＩを製作することが可能なＬＳＩの
チップ上でのピン配置の要部概略図を示す。ピンに複数
のボンディングを行なう場合には、ボンディングＰＡＤ
の列を２列以上にすることも可能である。本実施例で
は、２つのＬＳＩチップを横に２つ並べた構成である
が、アドレス、外部入力信号回路などを２組設けること
により、チップ内での信号伝達距離の低減を図り、高速
動作をねらったものである。また、Ｉ／Ｏピン以外を一
部含む信号ピンのリ−ドピンとＶSS内部リ−ド７が交差
するため、２層のパッケ−ジを用いている。(Embodiment 4) In FIG. 7, a plurality of rows of bonding can be performed with one pin, and two kinds of LSIs having the same pin arrangement are manufactured by switching the connection with V SS by the bonding master. FIG. 3 is a schematic view of a main part of a pin arrangement on a chip of an LSI capable of performing the above. Bonding PAD for multiple bonding to pins
It is also possible to have two or more columns. In this embodiment, two LSI chips are arranged side by side, but by providing two sets of addresses, external input signal circuits, etc., it is possible to reduce the signal transmission distance within the chip and achieve high-speed operation. It is what I was aiming for. Further, since the lead pins of the signal pins including a part other than the I / O pins and the V SS internal lead 7 intersect, a two-layer package is used.
【００１５】（実施例５）図８に２つ以上のチップを向
かいあわせの背中合せに１つのパッケ−ジに実装した断
面の要部概略図を示す。（ａ）は従来の例であり、
（ｂ）は本発明による例である。パッケ−ジ１のモ−ル
ド内にＬＳＩチップ２が実装され、ＬＳＩチップ２上に
はＶSS内部リ−ド７が配置され、外部と接続するために
ボンディングＰＡＤ６によって、ボンディングワイヤ３
とリ−ドピン４が接続され、２種の左右対称なピン配置
をもつを１つのパッケ−ジに実装している。上記ＬＳＩ
は信号制御によるＩ／Ｏピン同志、アドレスピン同志入
れ替え可能なＬＳＩであり、従来のものはチップを同一
方向に向けないとピンの配置を一致させることができな
いためパッケ−ジの接続がチップ端から外側にしかでき
ないが、本実施例では、チップを向かいあわせにするこ
とによって、チップ端内部で、パッケ−ジの接続を行な
うことができるため、パッケ−ジ外形を小さくできると
いう利点がある。(Embodiment 5) FIG. 8 shows a schematic view of a main part of a cross section in which two or more chips are mounted in one package facing each other and back to back. (A) is a conventional example,
(B) is an example according to the present invention. The LSI chip 2 is mounted in the mold of the package 1, the V SS internal lead 7 is arranged on the LSI chip 2, and the bonding wire 3 is formed by the bonding PAD 6 for connecting to the outside.
And the lead pin 4 are connected, and two types of bilaterally symmetrical pin arrangements are mounted in one package. Above LSI
Is an LSI that can switch between I / O pins and address pins by signal control. In the conventional LSI, the pin arrangement cannot be matched unless the chips are oriented in the same direction, so the package connection is at the chip end. However, in this embodiment, since the chips can be connected to each other inside the chip ends by facing the chips, there is an advantage that the outer shape of the package can be reduced.
【００１６】[0016]
【発明の効果】（１）同じチップのボンディング方向を
変えただけで対称な２種のＬＳＩを作るため、チップサ
イズの低減ができ、原価低減が可能となる。EFFECTS OF THE INVENTION (1) Since two kinds of symmetrical LSIs are produced only by changing the bonding direction of the same chip, the chip size can be reduced and the cost can be reduced.
【００１７】（２）ＬＯＣパッケ−ジのように、リ−ド
ピン、上下のモ−ルド厚の異なるＬＳＩのリ−ド曲げ方
向を同一にできパッケ−ジクラックを防止でき、ＬＳＩ
の信頼性が向上する。(2) Like the LOC package, the lead pins and the LSIs having different upper and lower mold thicknesses can have the same lead bending direction and can prevent package cracks.
Improves reliability.
【図１】同一チップでピン配置が対称な２種の１Ｍ×１
６ビット構成のＬＳＩのチップ上でのピン配置の要部概
略図。FIG. 1 Two types of 1M × 1 with the same chip and symmetrical pin arrangement
FIG. 6 is a schematic view of a main portion of a pin arrangement on an LSI chip having a 6-bit configuration.
【図２】両面実装可能なＬＯＣパッケ−ジの要部断面概
略図。FIG. 2 is a schematic cross-sectional view of a main part of a LOC package that can be mounted on both sides.
【図３】ボ−ドに両面実装した場合の１Ｍ×４ビット構
成のＬＳＩのパッケ−ジとボ−ドの断面の要部概略図と
上記ＬＳＩのリ−ドピン配置の要部概略図。FIG. 3 is a schematic view of a main part of a package and a cross-section of the board of an LSI having a 1M × 4 bit structure when mounted on both sides of a board, and a schematic view of a main part of a lead pin arrangement of the LSI.
【図４】同一チップでピン配置が対称なボンディングマ
スタを設けた２種のＬＳＩのチップ上ピン配置の要部概
略図とボンディングマスタによる回路の入替え回路の要
部概略図。FIG. 4 is a schematic view of a main part of a pin arrangement on a chip of two types of LSIs provided with a bonding master having a symmetrical pin arrangement on the same chip, and a schematic view of a main part of a circuit replacement circuit by the bonding master.
【図５】同一チップでピン配置が対称なボンディングマ
スタを設けた２種のＬＳＩのチップ上ピン配置の要部概
略図とボンディングマスタによる回路の入替え回路の要
部概略図。5A and 5B are a schematic view of a main part of an on-chip pin arrangement of two types of LSIs provided with bonding masters having symmetrical pin arrangements on the same chip and a schematic view of a main part of a circuit replacement circuit by the bonding master.
【図６】チップ上の２列のボンディングＰＡＤの間にメ
モリアレイと上記メモリ周辺回路をもち、ボンディング
マスタによって切り換えることによって、２種のＬＳＩ
のピン配置の要部概略図。FIG. 6 shows two kinds of LSIs having a memory array and the above memory peripheral circuits between two rows of bonding PADs on a chip and switching by a bonding master.
FIG.
【図７】１つのピンで複数列のボンディングを可能と
し、ボンディングマスタによって、２種のＬＳＩを製作
することが可能なＬＳＩのチップ上ピン配置の要部概略
図。FIG. 7 is a schematic view of a main part of an on-chip pin arrangement of an LSI capable of bonding a plurality of rows with one pin, and capable of manufacturing two types of LSIs by a bonding master.
【図８】信号制御によるＩ／Ｏピン同志、アドレスピン
同志入れ替え可能なＬＳＩをボ−ドに両面実装したとき
の断面の要部概略図。FIG. 8 is a schematic view of a main part of a cross section of an LSI in which I / O pins and address pins can be interchanged by signal control when both sides are mounted on a board.
１・・・・・パッケ−ジ、２・・・・・チップ、３・・・・・ボンディ
ングワイヤ、４・・・・・リ−ドピン、５・・・・・ボ−ド、６・・
・・ボンディングＰＡＤ、７・・・・ＶSS内部リ−ド、８・・・・
・ボンディングマスタ、９・・・・・スイッチ、１０・・・・・ヒ
ュ−ズ、１１・・・・・メモリアレイとメモリ周辺回路1 package, 2 chip, 3 bonding wire, 4 lead pin, 5 board, 6 ...
..Bonding PAD, 7 ... VSS internal lead, 8 ...
・ Bonding master, 9 ... Switch, 10 ... Fuse, 11 ... Memory array and memory peripheral circuit
フロントページの続き (72)発明者 角崎 学 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内Front page continuation (72) Inventor Manabu Kadosaki 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center
Claims (3)
おいて、チップ上に２列に並べることによって配置され
るアドレス用、入出力回路用のボンディングＰＡＤの全
てあるいはその一部と、チップ上に１列に並べることに
よって配置される電源用、制御信号用のボンディングＰ
ＡＤとを有することを特徴とするメモリＬＳＩ。1. In a memory LSI using a LOC package, all or a part of bonding PADs for addresses and input / output circuits arranged by arranging them in two rows on the chip, and one row on the chip. Bonding P for power supply and control signal arranged by arranging
A memory LSI having AD.
おいて、入出力回路信号のボンディングＰＡＤを全て、
あるいは一部をチップ上に２列に配置し、接地電圧ピン
のボンディングＰＡＤと上記接地電圧ピンのリ−ドとの
接続をボンディングワイヤによって切り換えることによ
って、上記ボンディングＰＡＤのそれぞれに接続されて
いる内部回路の出力論理を反転可能としたことを特徴と
するメモリＬＳＩ。2. In a memory LSI using a LOC package, all bonding pads of input / output circuit signals are
Alternatively, some of them are arranged in two rows on the chip, and the connection between the bonding PAD of the ground voltage pin and the lead of the ground voltage pin is switched by a bonding wire, so that the inside connected to each of the bonding PADs. A memory LSI characterized in that the output logic of the circuit can be inverted.
ク、ヒュ−ズ切断時等によるＲＯＭによって、内部回路
出力論理を反転可能としたことを特徴とする特許請求の
範囲第３項記載のメモリＬＳＩ。3. A memory LSI according to claim 3, wherein the output switching logic of the internal circuit can be inverted by a ROM for disconnecting the wiring mask, fuse, etc. ..
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4046695A JP2985479B2 (en) | 1992-03-04 | 1992-03-04 | Semiconductor memory and semiconductor memory module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4046695A JP2985479B2 (en) | 1992-03-04 | 1992-03-04 | Semiconductor memory and semiconductor memory module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05251495A true JPH05251495A (en) | 1993-09-28 |
| JP2985479B2 JP2985479B2 (en) | 1999-11-29 |
Family
ID=12754521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4046695A Expired - Lifetime JP2985479B2 (en) | 1992-03-04 | 1992-03-04 | Semiconductor memory and semiconductor memory module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2985479B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003059262A (en) * | 2001-08-20 | 2003-02-28 | Elpida Memory Inc | Semiconductor device |
| US6815525B2 (en) | 2000-12-07 | 2004-11-09 | Eastamn Chemical Company | Component introduction into manufacturing process through recirculation |
| JP2007059885A (en) * | 2005-07-22 | 2007-03-08 | Marvell World Trade Ltd | Packaging for high-speed integrated circuit |
| US7847377B2 (en) | 2005-09-29 | 2010-12-07 | Elpida Memory Inc | Semiconductor device including semiconductor chip with two pad rows |
| US7884451B2 (en) | 2005-07-22 | 2011-02-08 | Marvell World Trade Ltd. | Packaging for high speed integrated circuits |
| KR101340512B1 (en) * | 2006-12-01 | 2013-12-12 | 삼성디스플레이 주식회사 | Semiconductor chip package and printed circuit board assembly having the same |
-
1992
- 1992-03-04 JP JP4046695A patent/JP2985479B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6815525B2 (en) | 2000-12-07 | 2004-11-09 | Eastamn Chemical Company | Component introduction into manufacturing process through recirculation |
| JP2003059262A (en) * | 2001-08-20 | 2003-02-28 | Elpida Memory Inc | Semiconductor device |
| US7253457B2 (en) | 2001-08-20 | 2007-08-07 | Elpida Memory, Inc. | Semiconductor device with external terminals arranged symmetrically with respect to a normal external terminal arrangement |
| JP2007059885A (en) * | 2005-07-22 | 2007-03-08 | Marvell World Trade Ltd | Packaging for high-speed integrated circuit |
| US7884451B2 (en) | 2005-07-22 | 2011-02-08 | Marvell World Trade Ltd. | Packaging for high speed integrated circuits |
| US7847377B2 (en) | 2005-09-29 | 2010-12-07 | Elpida Memory Inc | Semiconductor device including semiconductor chip with two pad rows |
| KR101340512B1 (en) * | 2006-12-01 | 2013-12-12 | 삼성디스플레이 주식회사 | Semiconductor chip package and printed circuit board assembly having the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2985479B2 (en) | 1999-11-29 |
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