JPH04256032A - Pipeline system - Google Patents

Abstract

PURPOSE:To cancel the delay of write operation to a memory due to time taken for generating a check bit. CONSTITUTION:In the one-chip processor of a pipeline system in which stored data held in an accumulator 1 to store the result of arithmetic operation is transferred to a write register 4, and the write operation to the memory is executed in the next machine cycle, the stored data held in the accumulator 1 is inputted, and by a check bit generation circuit 5 for correcting an error and the register 3 to hold the check bit generated by the generation circuit 5 at the same timing as the timing at which the stored data is stored in the register 4, the check bit is outputted to an external memory 6 at the same timing as the data at the time when the data is written in the external memory 6 in conformity with a store a instruction.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a pipeline system, and more particularly to a pipeline system in which a check bit generation circuit for correcting a 1-bit error (soft error) that occurs during memory access is inserted into the pipeline. Regarding the method.

0002

[Prior Art] In the conventional technology, a check bit generation circuit for soft error correction was located between the processor and the memory, and generated check bits from data output from the processor and wrote them to the memory. .

0003

[Problems to be Solved by the Invention] In the conventional technology described above, in which check bits are generated from data output by a processor and written into memory, the time to generate the check bits is directly equal to the memory cycle time. In small-scale equipment that cannot make full use of techniques such as interleaving, this has become a major performance problem.

0004

[Means for Solving the Problems] The pipeline-in method of the present invention transfers store data held in an accumulator that stores operation results to a write data register, and performs a write operation to memory in the next machine cycle. In a pipelined one-chip processor, a first means for inputting store data held in the accumulator to generate a check bit for error correction; and a check generated by the first means. - The second means for holding the bit at the same timing as the storage data in the write data register allows the check bit to be held at the same timing of the data when writing memory data according to the store instruction. Constructed by outputting to memory.

[0005]

Embodiment FIG. 1 shows an embodiment of the present invention. 1 in the figure is an accumulator that stores the progress of the adder 10, 2 in the figure is an internal bus to which the contents of the accumulator 1 are always output, 4 in the figure is a write data register, and 6 in the figure is an external memory. 5 in the figure is an example of the first means, which is a check bit generation circuit for soft error correction, which is a feature of the present invention, and 3 in the figure is an example of the second means, which stores the check bit. It is a register. It is connected to the input internal bus 2 of the check bit generation circuit.

[0006] To execute a store instruction, first, write data is stored in accumulator 1 via an adder, transferred to write data register 4 via internal bus 2 in the next machine cycle, and transferred to the external write data register in the next machine cycle. memory 6
Perform a write operation on the .

In the present invention, check bits are generated along the flow of the write data. That is, during the period in which write data is transferred from the accumulator 1 to the write data register 4, a check bit is generated by the soft error correction check bit generation circuit 5, and the write data is stored in the write data register 4. Register 3 at the same time as
is stored in Also, during the period when a write operation is performed on the external memory 6, the check bit stored in the register 3 is also output at the same timing as the data stored in the write data register 4 is output to the memory. Output.

Details of the check bit generation circuit 5 for soft error correction are omitted here because the check bit generation circuit itself is already common and does not relate to the scope of the claims of the present invention.

As the most effective example of the present invention, FIG. 2 shows a timing chart when store instructions are processed successively. The pipeline method shown here is 1
Instruction processing is divided into each process as shown below, and the number of pipeline stages is seven. Each process is basically 1
It is assumed that memory access can be performed in one clock, and instruction fetch is performed when there is no operand read/write operation.

D: Instruction decode A: Address calculation T: Address conversion P: Operand read E: Operation S: Operation result storage Transfers the contents of the accumulator to the general register, etc. W: Memory write A stage that does not appear except for store instructions Here, the process of transferring write data from the accumulator 1 to the write data register 4 is performed in the S stage, and the write operation to the external memory 6 is performed in the W stage. Therefore, according to the present invention, the check bit of the write data is prepared together with the write data at the end of the S stage, and is supplied to the memory at the same timing as the write data in the next W stage. Therefore, since the time required to generate check bits is included in the S stage and not included in the W stage, high-speed memory writing is possible in the W stage, there is no disturbance in the pipeline, and subsequent instructions are processed without waiting. be done. In addition, the S stage processing normally only involves transferring write data from accumulator 1 to write data register 4, so even if you add the time required to generate the check bit, the S stage delay time is sufficient. can be kept within the machine cycle.

Since the pipeline system is used, the processing of each stage described above takes the same predetermined time (one clock in FIG. 2).
It is required to end within. However, this requirement is the strictest in the P stage and W stage, that is, in the memory
This is the stage for access. Especially when it is necessary to generate check bits for soft error correction when writing memory data in the W stage,
The time required for check bit generation is directly added to the processing time of the W stage, so that the processing cannot be completed within one machine cycle, and it is inevitable that the time required for the W stage will be doubled, for example.

[0012] Recently, with the advent of SRAMs in high schools, memory access can be performed in one clock, which has greatly improved performance. Here, if the processing time of the status is longer than that of other stages, the subsequent instructions of the write instruction will be forced to wait in the previous stage, as shown in FIG.

[0013]

[Effects of the Invention] As explained above, the present invention provides software
A check bit generation circuit for error correction is incorporated into the pipeline, generating check bits in parallel with transferring write data from the accumulator to the write data register, and transmitting the write data to the memory. By sending the data at the same timing, it eliminates delays in memory write operations due to the time it takes to generate check bits, greatly contributing to improved performance.

On the other hand, since a soft error correction function (ECC function) is indispensable for devices that require high reliability, it has recently been commonly employed even in small-scale devices using SRAM. As mentioned in the embodiment, when the ECC function is provided between the processor and the memory,
Performance will decrease due to increased memory cycle time. The present invention completely overcomes this reliability and performance gap.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the effectiveness of consecutive store instructions in the present invention.

FIG. 3 is a timing chart when store commands are executed consecutively when memory writing takes an extra clock.

[Explanation of symbols]

1 Accumulator 2 Internal bus 3 Register 4 that stores check bits
Register 5 for storing write data Check bit generation circuit 6 for soft error correction
External memory 10 Adder 11 1-chip processor

Claims (1)

[Claims] 1. A pipelined one-chip processor that transfers store data held in an accumulator that stores operation results to a write data register, and performs a write operation to memory in the next machine cycle. a first means for generating check bits for error correction by inputting store data held in the write data register; - The second means for holding data at the same timing as the data storage timing outputs a check bit to the memory at the same data timing when writing memory data according to a store instruction. Pipeline method.