JPH04245336A - Information processor - Google Patents

Abstract

PURPOSE:To outputs an optional interruption vector number from the output of a generated vector number holding means by setting a vector transforming table in a CPU, and to enable a compatible operation even when an application program is altered. CONSTITUTION:An internal vector number holding means 11 holds an alternable interruption vector number outputted from the CPU, a decoding means 12 decodes the specific bits of the interruption vector number from the internal vector number holding means, and a vector transforming means 13 selects the interruption vector signal held previously with the output of the decoding means. The generated vector number holding means 14 generates an interruption vector number newly from the selected interruption vector number from the vector transforming means 13 and a part of the interruption vector number of the internal vector holding means 11.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus that performs interrupt processing, and more particularly to an information processing apparatus that generates an arbitrary changeable interrupt vector number.

0002

[Prior Art] In an information processing device using a control device and an arithmetic device (hereinafter collectively referred to as a CPU), the CPU
U is designed to temporarily suspend normal processing and execute a pre-prepared interrupt processing program if an interrupt request is received from the outside or internally during normal processing. ing. When performing such interrupt processing, the CPU generates, for a specific interrupt factor, an interrupt vector number unique to the interrupt factor.

FIG. 3 is a block diagram showing an overview of interrupt processing in V30 of a CPU manufactured by NEC, and a method for receiving the address of this interrupt processing program will be briefly explained.

[0004] As an interrupt factor of V30, for example, NMI
(Non-maskable interrupt) When an external interrupt occurs due to the input 26, the CPU 21 first generates an interrupt vector "2" determined for the NMI input 26. CPU
21 is the address that is 4 times the interrupt vector “2”.
8” address of the external storage device 23 is output.
” The value 24 set in the corresponding address is read.

[0005] The address where the interrupt processing program 25 is located is set in advance at this address No. 8. The CPU 21 starts interrupt processing using the read value 24 as the interrupt processing start address.

[0006] The interrupt vector number generated by such a CPU has a value unique to the CPU for some specific interrupt factors. For example, in NEC's CPU V30, the NMI
For interrupts caused by input, the vector number is "2", and for interrupts caused by division by zero, vector number "0" is generated. Further, even among CPUs having the same instruction code, the interrupt vector numbers generated for a specific interrupt factor may differ.

[0007]

[Problem to be solved by the invention] Generally, when a CPU with expanded performance and functionality is created, if the newly created CPU cannot run the application program that was previously used, the newly created CPU will Application programs must be rewritten so that they can be executed by a CPU, which is a major drawback if the number of application programs is large. Therefore, even when new CPUs are created with enhanced performance and functionality, they are designed to have compatible instruction sets so that application programs that were previously used can be executed in the same way.

However, even in a CPU designed to execute instructions in the same way, due to requests for functional expansion, the interrupt vector number generated by the CPU during specific interrupt processing is changed to a different number than before. There are times when you have to. Because these interrupt vector numbers are different, some application programs may not perform the same operations.

[0009] Furthermore, in order to execute the same application program, several CPUs may employ the same instruction set and execute instructions in the same way; Even among CPUs that perform interrupt processing, the interrupt vector numbers generated by the CPUs may differ for a specific interrupt factor.

[0010] In conventional CPUs, the same application program may not be able to be executed between CPUs with the same instruction set because the interrupt vector numbers generated by the CPUs are different for a specific interrupt factor. It had drawbacks.

[0011] The purpose of the present invention is to solve such problems, and when a specific interrupt factor occurs inside the CPU,
The interrupt vector number generated by the CPU is stored in the vector conversion table, and when an interrupt factor occurs, the CPU
An object of the present invention is to provide an information processing device in which the interrupt vector number generated by a CPU can be freely changed since the interrupt vector number generated by the CPU is generated by converting it into the value of this vector conversion table.

0012

[Means for Solving the Problems] The configuration of the information processing device of the present invention includes an internal vector number holding means for holding a changeable interrupt vector number output from a CPU, and an interrupt vector number from the internal vector number holding means. a decoding means for decoding a predetermined bit of the number; a vector converting means for selecting an interrupt vector number previously held by the output of the decoding means; and an interrupt vector number selected from the vector converting means and holding the internal vector. The generated vector number holding means generates and holds a new interrupt vector number from a part of the interrupt vector number of the means, and an arbitrary interrupt vector number can be output by the output of the generated vector number holding means. characterized by things.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention. In this embodiment, internal vector number register 1
1 is held as a 16-bit wide value that was conventionally generated by the CPU as an interrupt vector number. If the value generated as this internal vector number (11) is a value from 0 to 255, the interrupt vector number (14) can be represented by the lower 8 bits of the internal vector number, and the upper 8 bits are always 0.
It is. Therefore, the vector conversion table 13 holds only the values of the lower 8 bits of the generated interrupt vector number. The decoder 12 decodes the lower 8 bits of the internal vector number 11 and sequentially selects the values set in the vector conversion table 13.

[0014] When an interrupt factor occurs, the CPU first
The generated internal vector number is held in the internal vector number register 11, and the decoder 12 stores the generated internal vector number in the internal vector number register 1.
Look at the lower 8 bits of 1 and select the lower 8 bits of the interrupt vector number from the vector conversion table 13. and 1
A 6-bit interrupt vector number is held in the interrupt vector number register 14, and the upper 8 bits of the internal vector number register 11 and the lower 8 bits of the interrupt vector number selected from the vector conversion table 13 are output as the interrupt vector number. Ru.

FIG. 2 is a block diagram showing another embodiment of the invention. In this embodiment, in addition to the first embodiment, vector conversion is performed for the internal vector number generated inside the CPU by a specific interrupt factor and held in the internal vector number register 11, and the output from this internal vector number register 11. In order to select which of the generated vector numbers converted using the table 13a and held in the generated vector number register 16 is to be output to the interrupt vector number register 14 as an interrupt vector number, select bit 15 is set in the interrupt vector conversion table 13a. I have it. If the selection bit 15 is "0", the internal vector number is output as the interrupt vector number and held in the register 11, and if the selection bit 15 is "1", the generated vector number is output and held in the register 16. This selection bit 15 is also set at the same time as setting the vector conversion table 13a.

The process from when an interrupt factor occurs in the CPU to generating the generated vector number (16) from the internal vector number (11) using the vector conversion table 13a is the first step.
This is similar to the embodiment.

In this embodiment, when the decoder 12 selects the vector number in the vector conversion table 13a, the address selection bit 15 is also selected at the same time. Then, as the interrupt vector number of the interrupt vector number register 14 output from the CPU, if the address selection bit 15 is "0", the selector 17 outputs an unconverted internal vector number, holds it in the register 11, and selects the selection bit 15.
If is "1", the generated vector number from the register 16 into which the internal vector number of the register 11 has been converted is selected as the interrupt vector number 14.

[0018]

[Effects of the Invention] As explained above, according to the present invention, compatibility problems in application programs can be solved by setting the vector conversion table inside the CPU before execution of the application program. The interrupt vector number generated by the CPU for a specific interrupt factor can be converted arbitrarily, and the application program may operate differently due to the different interrupt vector number while executing the same instruction. It has the great effect of being able to solve the problem.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing an overview of conventional interrupt processing.

[Explanation of symbols]

11 Internal vector number register 12 Decoder 13 Vector conversion table 14 Interrupt vector number register 15 Address selection bit 16 Generated vector number register 17 Selector 21 CPU 22 Address bus 23 Storage device 24 Interrupt processing address 25 Interrupt processing program 26 NMI interrupt signal

Claims (1)

[Claims] 1. Internal vector number holding means for holding a changeable interrupt vector number output from a CPU; decoding means for decoding predetermined bits of the interrupt vector number from the internal vector number holding means; vector converting means for selecting an interrupt vector number previously held by the output of the means; and a vector converting means for selecting an interrupt vector number previously held by the output of the means, and a new interrupt vector is generated from the selected interrupt vector number from the vector converting means and a part of the interrupt vector number of the internal vector holding means. 1. An information processing device comprising generated vector number holding means for generating and holding a number, and capable of outputting an arbitrary interrupt vector number by outputting the generated vector number holding means.