JPH036706A - Sequence controller - Google Patents

Abstract

PURPOSE:To shorten the processing time of a sequence program by outputting an interruption request signal to an interruption controller only when an execution signal is produced from a sequence arithmetic logic circuit. CONSTITUTION:A function instruction execution flag ACT is added to the data (sequence instruction) of a sequence program 4. Then a sequence arithmetic logic circuit 7 produces an execution signal if the flag ACT is equal to '1' when reading the sequence instruction. While no execution signal is produced if the flag ACT is equal to '0'. Then an AND gate 15 outputs an interruption request signal produced by an instruction decoder 6 to an interruption controller 10 only when the execution signal is produced. Thus it is possible to carry on a normal sequence process without starting an interruption routine with a function instruction which requires no execution. As a result, the processing time is shortened for the program 4.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a sequence controller, which uses a special general-purpose microprocessor (hereinafter referred to as MPU) to shorten the processing time of a sequence program and realize effective The present invention relates to a sequence controller that can improve processing speed.

[Prior Art] A sequence controller is a control device that sequentially advances operations according to predetermined conditions and sequences, but in particular, a controller that fully demonstrates the control function according to the control purpose of numerically controlled machine tools, etc. is required. Ru.

In particular, the sequence controller is configured such that an MPU performs a byte-based or word-based operation, and a sequence logic operation circuit performs a bit-based logical operation based on instructions from the MPU. For this reason, the sequence controller requires a capacity of multiple bytes or multiple words in the sequence program to perform bit-wise logical operations, resulting in a problem of poor memory efficiency and increased processing time for the sequence program. Ta.

By the way, sequence program data (sequence instructions) includes basic instructions (see Figure 8 (a)) and functional instructions (see Figure 8 (b)), and basic instructions are used when creating a sequence program. The most frequently used command is
Mnemonic rAND (data reading)” and “OR(
This is an instruction that performs a 1-bit logical operation such as OR) j.

In addition, the function commands are prepared exclusively for NC machine tools.
These instructions perform logical operations in byte or word units, such as OV (data transfer function) and rJMP (jump function), and can facilitate sequence programs that are difficult to perform using basic instructions alone.

If the sequence instruction is a functional instruction, interrupt processing is performed to temporarily interrupt the sequence processing, and the MPU
After executing that functional command, the process returns to sequence processing. That is, the sequence program 51 of the address specified by the MPU 50 (see FIG. 9)
The data is output to an instruction decoder 52, and the instruction decoder 52 decodes whether the read data is a basic instruction or a functional instruction. If the data is a basic instruction, sequence processing is performed by combining the data of the sequence program 51 and the sequence logic operation circuit 53, and if the data is a functional instruction, the instruction decoder 5
2 outputs an interrupt request signal to the interrupt controller 54 and sends it to the MPU 50 via the interrupt controller 54.
interrupt. Then, the MPU 50 immediately enters the interrupt processing routine, executes the interrupt processing routine such as saving the contents of the program counter and various registers,
After that, the data of the corresponding sequence program 51 is read again and the state of the execution flag of the data is checked. If the flag is "1", the function instruction is executed, and if the flag is "0", Prevents functional instructions from being executed. When the processing of the functional instruction is completed, the interrupt routine returns to the normal routine.

[Problems to be Solved by the Invention] However, in conventional sequence controllers, when a functional instruction exists in a sequence program, it first executes an interrupt routine (suspension of sequence processing) and then executes the interrupt routine when the corresponding functional instruction requires execution. If the function instruction does not require execution, the processing time of the sequence program increases by the amount of time required to execute the interrupt routine. Ta.

From the above, an object of the present invention is to provide a sequence controller that can continue normal sequence processing without entering an interrupt routine in the case of a functional instruction that does not require execution, and can shorten the processing time of a sequence program. That's true.

[Means to solve the problem]

In order to solve the above problem, the sequence controller of the present invention sets a functional command execution flag A to data of a sequence program 4 (see FIG. 1) that requires the execution of a functional command.
CTrl is provided, and a functional instruction execution flag ACTrO is provided for data that does not require the execution of a functional instruction, and when the functional instruction execution flag ACT is "1", an execution signal is generated, and the functional instruction execution flag ACT is Sequence logic operation circuit 7 having means for not generating an execution signal in the case of “0”
and an AND gate 15 that outputs an interrupt request signal generated by the instruction decode 6 to the interrupt controller 10 only when the execution signal is generated.

[Effect]

The data of the sequence program 4 is decoded by the instruction decode 6, and if the result of decoding is a functional command, the sequence logic operation circuit 7 sends out the signal of the functional command execution flag ACT of the corresponding data, and the logical product game) At step 15, the logical AND of the decoding result of the corresponding data and the signal of the functional instruction execution flag ACT is performed. If the result is true, an interrupt request signal is output to the interrupt controller 10. On the other hand, if the result of the above-mentioned logical product AND is false, no interrupt request signal is output.

[Example] Hereinafter, an example of the present invention will be described in detail based on the drawings.

The figure is a block diagram showing the main parts of the sequence controller of the present invention.

In Figure 1, 1 is a general-purpose microprocessor (hereinafter referred to as M
(referred to as PU), 2 is a main program that stores programs for processing contact commands, functional commands, and interrupts, and a program for processing instructions;
4 is a sequence program as a data area; 5 is a NOP code generation circuit that generates an instruction code (for example, a NOP instruction) that minimizes the execution time; 5 is a circuit that distributes the address output by the MPUI to the main program 2 or sequence program 4. an address decoder 6, an instruction decoder that decodes whether the sequence instruction output from the sequence program 4 is a basic instruction or a functional instruction;
7 is a sequence logic operation circuit that performs a 1-bit logic operation, 8 is a human power section, 9 is an output section, 10 is an interrupt controller for operations, etc., 11 is a buffer, 12 is a data transmitter, 13 is a 16-bit address bus, 14 is MPU
1 is a read signal to output, 15 is an AND gate for generating an interrupt request signal, 16 is an 8-bit data bus, 17 is a 16-bit data line for sequence program, and C8o is for selecting main program 2. C31 is a select signal for selecting sequence program 4, 18 is a 4-bit sequence instruction code line, and 19 is an input/output address line which also includes a bit data line. 5CLK is a sequence clock line, 20 is an interrupt signal line for arithmetic processing, etc., 21 is an interrupt request signal to the MPU, and 22 is an AND gate for generating the sequence clock 5CLK.

Note that sequence program 4 that requires the execution of functional commands
The data (sequence command) has a function command execution flag A.
CTrlJ is provided, and a functional instruction execution flag ACTrOJ is provided for sequence instructions that do not require execution of functional instructions. Further, when the sequence logic operation circuit 7 reads a sequence instruction, the function instruction execution flag ACT is set to “
1”, an execution signal is generated and the functional instruction execution flag A
It has means for not generating an execution signal when CT is "0".

Figure 2 shows the sequence program counter (hereinafter referred to as PC
12 is a flowchart illustrating a case in which contact commands and function commands are processed by a method called . Hereinafter, the present invention will be explained in detail along the flowchart of FIG. It is assumed that means is provided for allocating a predetermined area of the main program 2 of the MPUI as a reserved area for executing the sequence program 4 and sharing the PC of the MPUI as the PC of the sequence program 4. The NOP code generation circuit 3 also creates an area for executing a predetermined sequence program 4 in the main program 2 of the MPUI.
NOP occurs when fetching an opcode or reading operand data of a functional instruction that does not require execution.
Assume that an instruction is generated and sent to the data bus 16.

When the operation starts, the initial value of the sequence program 4 PC, for example rmmmmJ, is set in the MPUI PC (step 1.01).

When rmmmmJ is set in the MPUI PC, the address decoder 5 distributes the address "rmmmm" to the main program 2 and the sequence program 4, and the command part of the address distributed to the main program 2 is written as, for example, mmmm NOP. Since the NOP instruction is sent from the NOP code generation circuit 3 via the data bus 16, the MPU 1 reads the NOP instruction in the operation code fetch cycle. Note that executing a NOP instruction means not performing any processing, so
At the same time as executing the NOP instruction, the MPUI reads the sequence instruction at address 'mmmmJ of the sequence program 4, and performs logical operation processing based on the sequence instruction (step 102).

If the instruction indicated by address rmmmmJ is executed, M
PUI automatically increments (+l) the PC.

For example, after setting PC to rmmm(m+1)J (step 103) and incrementing PC, the MPUI repeats the processing from step 102 onwards.

When the MPU fetches the opcode as described above,
The time to execute the instruction NOP that can be executed in the minimum time is 1
It is possible to demonstrate high-speed execution of step sequence commands.

FIG. 3 is a flowchart illustrating interrupt processing according to the present invention. The interrupt processing will be explained below with reference to FIG.

The instruction decoder 6 decodes whether the instruction is a basic instruction or a functional instruction (determine whether it is a functional instruction, step 201).

As a result of the judgment, if the basic command (Fig. 8 [a)] is indicated, normal sequence processing is performed, while the functional command (Fig. 8 [a)]
(b)), then it is determined whether the functional instruction execution flag ACT is "1" (step 202).
).

As a result of the determination, if the functional instruction execution flag ACT is "0", normal sequence processing is performed; on the other hand, if the functional instruction execution flag ACT is "1", an interrupt request signal is output to the interrupt controller 10. Note that the data of the sequence program 4 is decoded by the instruction decode 6, and if the decoding result is a functional command, the sequence logic operation circuit 7 outputs the functional command execution flag ACT of the corresponding data.
The AND gate 15 performs an AND operation between the decoding result of the corresponding data and the signal of the functional instruction execution flag ACT.

Then, the interrupt controller 10 requests the MPUI to perform interrupt processing, and the MPUI starts the interrupt processing. That is, the MPUI performs interrupt processing such as saving according to the contents of the PC and the register, and also reads from the sequence program 4 whether the interrupt instruction (function instruction) is an instruction or not, and enters the processing (step 203).

Next, it is determined whether the interrupt instruction from the sequence program 4 is an END instruction indicating the end of the sequence program 4 (step 204), and if it is an END instruction, the P
PC4-mmmm to return C to the initial value rmmmmJ of the sequence program 4, step 205), and the process ends. On the other hand, if it is not an END instruction, the corresponding functional instruction is processed (step 206), and the interrupt processing returns to normal sequence processing.Step 20.7
), terminates interrupt processing.

By the way, in the determination at step 202, when the functional instruction execution flag ACT is "1" and the result of the above-mentioned AND is false, if the MPUI reads the operand data of the corresponding functional instruction, the MPUI No to
Since the NOP instruction is output from the P code generation circuit 3, the interrupt processing routine is passed through without entering (jumping in terms of processing).

Next, the operation when processing the ladder sequence program shown in the ladder sequence diagram of FIG. 4 will be explained in detail.

Note that the sequence program 4 (see Figure 1) includes the fourth
It is assumed that a ladder sequence program (ladder language) having the content shown in the ladder sequence diagram in the figure is stored in the memory in the form shown in FIG. Furthermore, this ladder language is actually stored in the form of executable contents as machine language (machine code) shown in FIG. That is, the upper 4 bits are a sequence instruction code, the next 3 bits are bit designation data, and the remaining 9 bits are human output address data. Note that the bit designation data is data for converting input/output data into 1-bit data for sequence processing when a general MPUI treats input/output data as parallel data.

By starting the sequence, the initial value of the PC of the sequence program 4 is set to the program counter PC of the MPU1.
mmJ is cent.

When rmmmmJ is set in the MPUI PC, address rmmmmJ is output to the main program 2 via the address bus 13. Then, the MPUI causes the NOP code generation circuit 3 to generate a NOP instruction via the read signal 14, and executes the NOP instruction. On the other hand, the address rmmmmJ is distributed by the address decoder 5,
Sequence program 4 via select signal CS+
is output to. That is, according to the timing chart of FIG. 7, the sequence command, that is, the memory address rmmmmJ of FIG. A sequence command with the content "a certain rRDool" will be output.

This sequence instruction is the monic rRD, which is the content of address 001 (see FIG. 5), and this sequence instruction is decoded through the instruction decoder 6 and basic instruction (8th
Since it is shown in Figure (a), it is output to the sequence logic operation circuit 7. Then, sequence processing is performed in the sequence logic operation circuit 7. This operation is performed between the fall and rise of the sequence clock 5CLK in FIG.

If you execute the sequence command with the contents at memory address r m, m m m J, MPUI will give +1 (
Increment) and set it as PC-PC+1. Then, PC becomes rmmm(m-t-1)J.

Similarly, the sequence processing is executed by repeating the processing operations of the PC. For example, the case of the sequence program 4 shown by (It) in the ladder sequence diagram of FIG. 4 will be described. It is assumed that this sequence program 4 is included in the sequence program 4 as a ladder language in the form shown in (II) in FIG. If the PC processing program shown in Fig. 2 continuously counts up the contents of the PC to rmmm (m ± 5), then the MPUI outputs the contents of this PC to the sequence program 4 and outputs the contents of the PC to rmmm (m + 5). The contents of address J are read into the sequence logic operation circuit 7.

Next, when MPUI increases PC by +1, rmmm(m+6
)", and when the MPUI outputs the contents of the PC to the sequence program 4, the contents of the address "rmmm(m+6)" indicate a function instruction (MOV), so the function of the sequence instruction read in the sequence logic operation circuit 7. It is determined whether the instruction execution flag ACT is "1" or "0", and if it is "1", an execution signal is output to the AND gate 15. On the other hand, since the sequence command is a functional command, the command decoder 6 outputs a predetermined signal.

If the execution signal is output from the sequence logic operation circuit 7, the AND gate 15 outputs an interrupt request signal to the interrupt controller 10.
enters interrupt processing. That is, MPU1 is rmmm
(m+6)" when the contents of the address are 005, rmmm
(m+7)” content of (A) at address rmmm(m+8)
” performs the job of forwarding to address (B).

2, the interrupt function of the MPUI can be used to process sequence operations and tasks by software having the functions shown in FIG. 2, and the flexibility of the program function can be demonstrated.

〔Effect of the invention〕

As explained above, according to the present invention, the functional instruction execution flag is set to "1" for sequence program data that requires the execution of a functional instruction, and the functional instruction execution flag is set to "0" for data that does not require the execution of a functional instruction. a sequence logic operation circuit having a means for generating an execution signal when the functional instruction execution flag is "1" and not generating an execution signal when the functional instruction execution flag is "0"; Since the above-mentioned instruction decoding has means for outputting an interrupt request signal generated by the instruction decoding to the interrupt controller only when a sequence processing can be continued, and the processing time of the sequence program can be shortened. As a result, it is possible to improve processing efficiency, processing capacity, etc. as a sequence controller for machine tools, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of the sequence controller of the present invention, FIG. 2 is a flowchart explaining the processing of the sequence program counter, FIG. 3 is a flowchart explaining the interrupt processing of the present invention, and FIG. 4 is a ladder sequence diagram of two embodiments of the present invention, FIG. 5 is a co-under diagram of the state in FIG. 4, FIG. 6 is an explanatory diagram of the machine code, and FIG.
FIG. 8 is a timing chart of various signals issued by PU commands, and is an explanatory diagram of sequence commands.
FIG. 8(a) is an explanatory diagram of basic instructions, FIG. 8(b) is an explanatory diagram of functional instructions, and FIG. 9 is a block diagram of a conventional sequence controller that performs interrupt processing. ■... Microprocessor (MPU), 2... Main program, 3... NOP code generation circuit, 4... Sequence program, 5... Address decoder, 6... Instruction decoder, 7... - Sequence logic operation circuit, 8... Human power section, 9... Output section, 10... Interrupt controller, 15... AND gate, ACT... Functional instruction execution flag. Fig. 4 Fig. 6 Alloy code bit data Human output address data Fig. 3 Fig. 7 Fig. 8 Procedural amendment (method) Display of incident Title of invention in patent application No. 1-142648 Sequence controller 3° correction Relationship with the patent case Patent applicant address: 1 Abiko, Abiko City, Chiba Name: Hitachi Seiki Co., Ltd. Representative: Teshima Gobe 4゜

Claims (1)

[Scope of Claims] A general-purpose microprocessor, an instruction decoder that decodes data of a sequence program at an address specified by the general-purpose microprocessor and generates an interrupt request signal if the decoded data is a functional instruction; A sequence controller comprising means for performing sequence processing by combining program data and a sequence logic operation circuit, and an interrupt controller that is connected to the general-purpose microprocessor and instructs interrupt processing using the interrupt request signal. A functional instruction execution flag "1" is provided for data of the sequence program that requires execution, a functional instruction execution flag "0" is provided for data that does not require execution of a functional instruction, and the functional instruction execution flag is set to "1". a sequence logic operation circuit having a means for generating an execution signal when the functional instruction execution flag is "0" and not generating an execution signal when the functional instruction execution flag is "0"; and the instruction decoder generating the execution signal only when the execution signal is generated. A sequence controller comprising means for outputting an interrupt request signal to an interrupt controller.