JPH0423491A - Manufacture of polyimide resin multilayer wiring board - Google Patents
Manufacture of polyimide resin multilayer wiring boardInfo
- Publication number
- JPH0423491A JPH0423491A JP12955790A JP12955790A JPH0423491A JP H0423491 A JPH0423491 A JP H0423491A JP 12955790 A JP12955790 A JP 12955790A JP 12955790 A JP12955790 A JP 12955790A JP H0423491 A JPH0423491 A JP H0423491A
- Authority
- JP
- Japan
- Prior art keywords
- polyimide resin
- thin film
- layer
- metal thin
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229920001721 polyimide Polymers 0.000 title claims abstract description 20
- 239000009719 polyimide resin Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000002184 metal Substances 0.000 claims abstract description 33
- 239000010409 thin film Substances 0.000 claims abstract description 19
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000007747 plating Methods 0.000 claims abstract description 6
- 238000000206 photolithography Methods 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 230000002950 deficient Effects 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- YECBIJXISLIIDS-UHFFFAOYSA-N mepyramine Chemical compound C1=CC(OC)=CC=C1CN(CCN(C)C)C1=CC=CC=N1 YECBIJXISLIIDS-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電子機器で用いられるポリイミド樹脂多層配
線基板の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a polyimide resin multilayer wiring board used in electronic equipment.
従来、ポリイミド樹脂多層配線基板はセラミック多層配
線基板上に導体配線層とポリイミド樹脂絶縁層を交互に
積層して製造し、多層配線層を含むアルミナ基板上に最
初に形成する層はアルミナ基板上の信号用ランド、接地
用電源用ランドの受はパッド的なメタル配線層を形成し
ていた。Conventionally, polyimide resin multilayer wiring boards are manufactured by alternately laminating conductor wiring layers and polyimide resin insulating layers on a ceramic multilayer wiring board, and the first layer formed on the alumina substrate containing the multilayer wiring layer is the layer on the alumina substrate. The signal land and grounding power supply land receivers formed pad-like metal wiring layers.
この従来のポリイミド樹脂多層配線基板の製造方法では
、まずアルミナセラミック上に金属薄膜を蒸着又はスパ
ッタリング等の方法で形成し、ホトレジストを用いてホ
トリソグラフィで第１層目の配線層をパターニングしそ
こにめっきにより第１層目の金属配線を形成した。第１
層目の金属配線が形成されたところでホトレジストをは
く離し、その後イオンビームエツチング装置を用いて金
属薄膜をエツチングしていた。In this conventional manufacturing method for polyimide resin multilayer wiring boards, a thin metal film is first formed on alumina ceramic by vapor deposition or sputtering, and then a first wiring layer is patterned by photolithography using photoresist. A first layer of metal wiring was formed by plating. 1st
The photoresist is peeled off after a layer of metal wiring is formed, and then the metal thin film is etched using an ion beam etching device.
第２図は従来の製造方法によるポリイミド樹脂多層配線
基板の断面図である。アルミナセラミッり多層配線基板
２１上に金属薄膜２２が形成され、金属薄膜２２にめっ
きを施して金属配線層２６を形成している。FIG. 2 is a sectional view of a polyimide resin multilayer wiring board manufactured by a conventional manufacturing method. A metal thin film 22 is formed on an alumina ceramic multilayer wiring board 21, and a metal wiring layer 26 is formed by plating the metal thin film 22.
上述した従来のポリイミド樹脂多層配線基板の製造方法
は、イオンビームエツチング装を用いて金属薄膜をエツ
チングしてもアルミナセラミックス上の微小な凹凸のた
め四部の金属薄膜は完全にはとりきれず（第２図に示す
完全にとれきれていない金属薄膜２７）、アルミナセラ
ミックス基板表面で十分な絶縁抵抗を得ることができな
いという問題がある。In the conventional manufacturing method of the polyimide resin multilayer wiring board described above, even if the metal thin film is etched using an ion beam etching system, the metal thin film on the four parts cannot be completely removed due to minute irregularities on the alumina ceramic. There is a problem that sufficient insulation resistance cannot be obtained on the surface of the alumina ceramic substrate due to the metal thin film 27) shown in FIG. 2, which is not completely removed.
本発明のポリイミド樹脂多層配線基板の製造方法は、ア
ルミナ基板上に最初にポリイミド樹脂絶縁層を形成し、
その上に金属薄膜を形成し、この金属薄膜上にホトレジ
ストを用いてホトリソグラフィで第１層目の配線層をパ
ターニングし前記ホトレジストのパターニングされた部
分のめっきにより第１層目の金属配線を形成し、この第
１層目の金属配線が形成されたところで前記ホトレジス
トをはく離し、その後イオンビームエツチング装置を用
いて金属薄膜の前記第１層目の金属配線の部分以外をエ
ツチングすることを特徴とする。The method for manufacturing a polyimide resin multilayer wiring board of the present invention includes first forming a polyimide resin insulating layer on an alumina substrate,
A metal thin film is formed thereon, a first layer wiring layer is patterned by photolithography using a photoresist on this metal thin film, and a first layer metal wiring layer is formed by plating the patterned portion of the photoresist. After the first layer of metal wiring is formed, the photoresist is removed, and then an ion beam etching device is used to etch the metal thin film other than the first layer of metal wiring. do.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１−図は本発明の一実施例を工程順に示ず断面図であ
る。FIG. 1 is a sectional view of an embodiment of the present invention without showing the process order.
第１図において、アルミナセラミック多層配線基板１に
ポリイミド樹脂のヴイアホール４を有する絶縁層５（非
感光性なら日立化成のＰＩＱ、デュポンのＰ Ｙ ＲＡ
Ｌ Ｙ Ｎ、東しのセミコファイン等、感光性なら日
立化成のＰ Ｌ−１，２００、デュポンのＰＩ−２７０
２Ｄ、東しの）オトニース、旭化成のＰＩＭＥＬ等）を
５ミクロンから１０ミクロンで形成する（第１図（ａ）
）。そしてこの上ニＣｒ ／ Ｐ ｄ金属薄膜２を５０
０Å／ ］−５００人で蒸着またはスパッタリングで形
成する（第１図（ｂ））。In FIG. 1, an alumina ceramic multilayer wiring board 1 has an insulating layer 5 having via holes 4 made of polyimide resin (for non-photosensitive materials, Hitachi Chemical's PIQ, DuPont's PYRA
L Y N, Toshi's Semico Fine, etc. For photosensitive products, Hitachi Chemical's PL-1,200, DuPont's PI-270
2D, Azuma Shino) Otonis, Asahi Kasei's PIMEL, etc.) is formed with a thickness of 5 to 10 microns (Figure 1 (a)
). Then, a 50% Cr/Pd metal thin film 2 was deposited on top of this.
0 Å/]-500 people by vapor deposition or sputtering (FIG. 1(b)).
そしてこの上にホトレジスト
ソグラフィーにより配線パターン７形成する（第１図（
Ｃ））。Then, a wiring pattern 7 is formed on this by photoresist lithography (Fig. 1 (
C)).
次に配線パターン７にめっき法で配線層６を形成する（
第１図（ｄ））。その後ホトレジスト３をはく離しイオ
ンビームエツチング装置によりＣｒ ／ Ｐ ｄ金属薄
膜２をエツチングする（第１図（ｅ））。Next, a wiring layer 6 is formed on the wiring pattern 7 by a plating method (
Figure 1(d)). Thereafter, the photoresist 3 is peeled off, and the Cr/Pd metal thin film 2 is etched using an ion beam etching device (FIG. 1(e)).
以上説明したように本発明によれば、多層配線基板を含
むアルミナ基板上にポリイミド樹脂の絶縁層と配線層が
交互に積層されたポリイミド樹脂多層配線基板で、多層
配線基板を含むアルミナ基板上に最初にポリイミド樹脂
絶縁層を形成することにより、次工程の信号用ランド、
接地用電源用ランドの受はパッド的なメタル配線層を形
成するとき、イオンビームエツチング装置を用いて金属
薄膜をエツチングしても、ポリイミド樹脂の表面はアル
ミナセラミックスに比べて十分滑らかなため、エツチン
グ残りによる絶縁抵抗不良の発生という問題を解決でき
る。As explained above, according to the present invention, there is provided a polyimide resin multilayer wiring board in which insulating layers and wiring layers of polyimide resin are alternately laminated on an alumina substrate including a multilayer wiring board. By first forming a polyimide resin insulating layer, the signal land in the next process,
When forming a pad-like metal wiring layer for the grounding power supply land support, even if a thin metal film is etched using an ion beam etching device, the surface of polyimide resin is smooth enough compared to alumina ceramics, so etching is difficult. This can solve the problem of poor insulation resistance caused by residual parts.
一one
第１図は本発明の一実施例を工程順に示す断面図、第２
図は従来の製造方法によるポリイミド樹脂多層配線基板
の断面図である。
１．２１・・・アルミナセラミック多層配線基板、２．
２２・・・金属薄膜、３・・・ホトレジスト、４・・・
ヴイアホール、５・・・絶縁層、６．２６・・・配線層
、７・・・配線パターン、２７・・・完全にとれきれて
いない金属薄膜。Figure 1 is a sectional view showing one embodiment of the present invention in the order of steps;
The figure is a cross-sectional view of a polyimide resin multilayer wiring board manufactured by a conventional manufacturing method. 1.21...Alumina ceramic multilayer wiring board, 2.
22... Metal thin film, 3... Photoresist, 4...
Via hole, 5... Insulating layer, 6.26... Wiring layer, 7... Wiring pattern, 27... Metal thin film not completely removed.
Claims (1)
、その上に金属薄膜を形成し、この金属薄膜上にホトレ
ジストを用いてホトリソグラフィで第１層目の配線層を
パターニングし前記ホトレジストのパターニングされた
部分のめっきにより第１層目の金属配線を形成し、この
第１層目の金属配線が形成されたところで前記ホトレジ
ストをはく離し、その後イオンビームエッチング装置を
用いて金属薄膜の前記第１層目の金属配線の部分以外を
エッチングすることを特徴とするポリイミド樹脂多層配
線基板の製造方法。First, a polyimide resin insulating layer is formed on an alumina substrate, a metal thin film is formed on it, and a first wiring layer is patterned on this metal thin film by photolithography using a photoresist. A first layer of metal wiring is formed by plating the first layer of metal wiring, and when the first layer of metal wiring is formed, the photoresist is peeled off, and then an ion beam etching device is used to remove the first layer of metal thin film. A method for manufacturing a polyimide resin multilayer wiring board, characterized by etching parts other than the metal wiring of the eyes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12955790A JPH0812952B2 (en) | 1990-05-18 | 1990-05-18 | Method for manufacturing polyimide resin multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12955790A JPH0812952B2 (en) | 1990-05-18 | 1990-05-18 | Method for manufacturing polyimide resin multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0423491A true JPH0423491A (en) | 1992-01-27 |
| JPH0812952B2 JPH0812952B2 (en) | 1996-02-07 |
Family
ID=15012444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12955790A Expired - Lifetime JPH0812952B2 (en) | 1990-05-18 | 1990-05-18 | Method for manufacturing polyimide resin multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0812952B2 (en) |
-
1990
- 1990-05-18 JP JP12955790A patent/JPH0812952B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0812952B2 (en) | 1996-02-07 |
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