JPH0677650A - Production of multilayer wiring board - Google Patents
Production of multilayer wiring boardInfo
- Publication number
- JPH0677650A JPH0677650A JP22983792A JP22983792A JPH0677650A JP H0677650 A JPH0677650 A JP H0677650A JP 22983792 A JP22983792 A JP 22983792A JP 22983792 A JP22983792 A JP 22983792A JP H0677650 A JPH0677650 A JP H0677650A
- Authority
- JP
- Japan
- Prior art keywords
- resist pattern
- metal film
- layer
- plating resist
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は多層配線板の製造方法に
係り、特に改良されたビルドアップ方式による多層配線
板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board, and more particularly to a method for manufacturing a multilayer wiring board by an improved build-up method.
【０００２】[0002]
【従来の技術】周知のように配線板（配線回路基板）
は、たとえばガラエポ樹脂基板などの絶縁性基板面上に
接着剤を介して貼着された銅箔について、フォトリソグ
ラフィや、フォトエッチング処理を施し、所要の配線パ
ターン化するという方法で一般的に製造されている。ま
た、この種の配線板において、配線の高密度化ないし配
線板のコンパクト化などを目的にした多層配線型の配線
板も知られている。そして、この多層配線型の配線板
は、たとえば金形面もしくは絶縁性基板面に、レジスト
を用い所要の導体パターンを設けレジスト層を剥離・除
去した後、この導体パターンを絶縁層を介して、たとえ
ばガラエポ樹脂基板面に順次転写することによって製造
されている。2. Description of the Related Art As is well known, wiring boards (wiring circuit boards)
Is generally manufactured by a method of subjecting a copper foil adhered on an insulating substrate surface such as a glass epoxy resin substrate via an adhesive to photolithography or photoetching to form a required wiring pattern. Has been done. Further, in this type of wiring board, a multilayer wiring type wiring board is also known for the purpose of increasing the density of wiring or downsizing the wiring board. Then, this multilayer wiring type wiring board is provided, for example, on a die surface or an insulative substrate surface, by forming a required conductor pattern using a resist, peeling and removing the resist layer, and then by passing this conductor pattern through an insulating layer, For example, it is manufactured by sequentially transferring to a glass epoxy resin substrate surface.
【０００３】前記転写法による多層配線板の製造は、た
とえば金形面など導電性の基板面に、絶縁性のフォトレ
ジスト層を配置し、選択的な露光・エッチングによりメ
ッキレジストパターンを形成する。次いで、前記導電性
の基板を陰極として電気銅メッキ処理を施し、前記メッ
キレジストパターンと逆パターンの導電パターンを形成
する。その後、上記導電パターン形成面上に絶縁層を一
体的に形成し、この絶縁層に上記の導電パターンに接続
する孔を設け、この孔内を導電体で埋め込む一方、絶縁
層面上にメッキレジストパターンを形成する。このよう
にメッキレジストパターンを設けてから、選択的な化学
メッキ処理、およびこの化学メッキ処理で形成した金属
層を利用しての電気銅メッキ処理により導電パターンを
形成する。以下、導電パターン形成面上への絶縁層形
成，孔明け・導電体で埋み，選択的なメッキ処理による
導電パターンの形成の工程を順次繰り返して所要の多層
配線層を形成する。こうして所要の多層配線層を形成し
た後、この多層配線層を導電性の基板面から、たとえば
プリプレグ面に剥離・転写することにより製造してい
る。 前記転写法による多層配線板の製造は、たとえば
絶縁性基板面に張合わせた銅箔の選択的なエッチングで
形成した導電パターンを、他の絶縁性基板面に積層的に
転写する方式に比べて、銅の節減などを図り得ることや
比較的微細な配線パターンとし得ることなどから、多く
の注目を集めている。In the manufacture of a multilayer wiring board by the transfer method, an insulating photoresist layer is arranged on a conductive substrate surface such as a die surface, and a plating resist pattern is formed by selective exposure / etching. Next, electrolytic copper plating is performed using the conductive substrate as a cathode to form a conductive pattern having a pattern opposite to the plating resist pattern. Then, an insulating layer is integrally formed on the conductive pattern forming surface, a hole connecting to the conductive pattern is provided in the insulating layer, and the inside of the hole is filled with a conductor, while a plating resist pattern is formed on the insulating layer surface. To form. After providing the plating resist pattern in this manner, a conductive pattern is formed by selective chemical plating and electrolytic copper plating using the metal layer formed by this chemical plating. Thereafter, the steps of forming an insulating layer on the surface on which a conductive pattern is formed, forming holes and filling with a conductor, and forming a conductive pattern by selective plating are sequentially repeated to form a required multilayer wiring layer. After the required multilayer wiring layer is formed in this manner, the multilayer wiring layer is manufactured by peeling and transferring the multilayer wiring layer from the conductive substrate surface to, for example, the prepreg surface. The production of a multilayer wiring board by the transfer method is, as compared with a method in which a conductive pattern formed by selective etching of a copper foil attached to an insulating substrate surface is transferred to another insulating substrate surface in a stacked manner, for example. However, it has attracted a lot of attention because it is possible to save copper and to form a relatively fine wiring pattern.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、前記転
写法に基づく多層配線板の製造方法の場合には、次のよ
うな不都合な点が認められる。すなわち、前記フォトレ
ジストパターンの形成、金属膜の形成、金属膜を電極と
しての電気銅メッキによる導体パターンの形成、および
層間絶縁層の形成、以下フォトレジストパターンの形成
などの繰り返しによって所要の多層配線層を構成した
後、その多層配線層を導電性基板から、たとえばプリプ
レグ層面に剥離・転写するとき、導電性基板面に対接し
ている絶縁層が、導電性基板面から剥離し難い傾向を呈
する。つまり、前記剥離・転写で導電性基板面から剥離
した絶縁層が破損などされ易く、表面平滑性が損なわれ
たり、あるいは絶縁性が損なわれたりして、歩留まりよ
くもしくは信頼性の高い多層配線板を常時得ることがで
きないという問題がある。However, in the case of the method for manufacturing a multilayer wiring board based on the transfer method, the following disadvantages are recognized. That is, the required multilayer wiring is formed by repeating the formation of the photoresist pattern, the formation of a metal film, the formation of a conductor pattern by electrolytic copper plating using the metal film as an electrode, the formation of an interlayer insulating layer, and the formation of a photoresist pattern hereinafter. After the layers are formed, when the multilayer wiring layer is peeled and transferred from the conductive substrate, for example, to the prepreg layer surface, the insulating layer that is in contact with the conductive substrate surface tends to be difficult to peel from the conductive substrate surface. . That is, the insulating layer peeled off from the conductive substrate surface by the peeling / transferring is easily damaged, and the surface smoothness is impaired or the insulating property is impaired, resulting in a high yield or high reliability of the multilayer wiring board. There is a problem that you cannot always get
【０００５】本発明は上記事情に対処してなされたもの
で、比較的簡略な工程によって、外観なども良好で、信
頼性の高い多層配線板を歩留まりよく製造し得る多層配
線板の製造方法の提供を目的とする。The present invention has been made in view of the above circumstances, and provides a method of manufacturing a multilayer wiring board which has a good appearance and is highly reliable and can be manufactured with a high yield by a relatively simple process. For the purpose of provision.
【０００６】[0006]
【課題を解決するための手段】本発明に係る多層配線板
の製造方法は、(A) 導電性を有する支持基体面上に剥離
性の第１の金属膜を一体的に被着形成する工程と、(B)
前記第１の金属被膜面上にフォトレジスト層を配置し選
択的な露光・エッチングにより第１のメッキレジストパ
ターンを形成する工程と、(C) 前記第１の金属膜を陰極
として電気銅メッキ処理を施し、第１のメッキレジスト
パターン上面と同一面を成すように露出する第１の金属
膜面を選択的に第１の銅メッキ層で肉盛りする工程と、
(D) 前記第１の銅メッキ層で肉盛りし平面化した面上に
フォトレジスト層を配置し選択的な露光・エッチングに
より肉盛り領域の一部を露出させて第２のメッキレジス
トパターンを形成する工程と、(E) 前記第２のメッキレ
ジストパターン形成面上に、第２のメッキレジストパタ
ーン面および露出面に区分された（隔別されて）第２の
金属膜を被着形成する工程と、(F) 前記第２のメッキレ
ジストパターンによる露出面に被着形成された第２の金
属膜を陰極として電気銅メッキ処理を施し、第２のメッ
キレジストパターン上面と同一面を成すように露出する
第２の金属膜面を選択的に第２の銅メッキ層で肉盛りす
る工程と、(G) 前記第２の銅メッキ層で肉盛りした後、
第２のメッキレジストパターン面上に被着形成された第
２の金属膜をソフトエッチングにより選択的に除去する
工程と、(H) 前記(D) 〜(G) の工程を繰り返し多層積層
体を形成した後、多層積層体を導電性を有する支持基体
面から転写・剥離して第１の金属膜をソフトエッチング
により除去する工程とを具備して成ることを特徴とする
多層配線板の製造方法。A method of manufacturing a multilayer wiring board according to the present invention comprises a step (A) of integrally forming a peelable first metal film on a surface of a conductive support substrate. And (B)
A step of forming a first plating resist pattern by selectively exposing and etching a photoresist layer on the surface of the first metal film, and (C) electrolytic copper plating using the first metal film as a cathode. And selectively depositing the first metal film surface exposed so as to be flush with the upper surface of the first plating resist pattern with the first copper plating layer,
(D) A photoresist layer is placed on the surface that has been flattened by the first copper plating layer and planarized, and a portion of the thickened area is exposed by selective exposure and etching to form a second plating resist pattern. Forming step, and (E) depositing a second metal film, which is divided (separated) into a second plating resist pattern surface and an exposed surface, on the second plating resist pattern forming surface. Step (F): An electrolytic copper plating process is performed using the second metal film deposited on the exposed surface of the second plating resist pattern as a cathode so as to be flush with the upper surface of the second plating resist pattern. Selectively depositing the second metal film surface exposed on the second copper plating layer with a second copper plating layer, and (G) after overlaying the second copper plating layer with the second copper plating layer,
A step of selectively removing the second metal film deposited on the surface of the second plating resist pattern by soft etching and (H) the steps of (D) to (G) are repeated to form a multilayer laminate. After the formation, the step of transferring / peeling the multi-layer laminate from the surface of the supporting substrate having conductivity and removing the first metal film by soft etching is included. .
【０００７】なお、上記工程において、第１の金属被膜
面上に第１の金属とは異種で、かつ導電性を有する第３
の金属層を被覆形成し、この第３の金属層面上にフォト
レジスト層を配置し選択的な露光・エッチングにより第
１のメッキレジストパターンを形成する工程へと、工程
の一部を変更することにより、金属膜のソフトエッチン
グの進行状況・程度を視覚的にも容易に把握・制御する
ことが可能である。In the above process, the third metal which is different from the first metal and has conductivity on the surface of the first metal coating film.
Part of the process is changed to a process of forming a first plating resist pattern by selectively forming a photoresist layer on the surface of the third metal layer and selectively exposing and etching the third metal layer. Thus, it is possible to easily visually grasp and control the progress and degree of soft etching of the metal film.
【０００８】[0008]
【作用】本発明に係る多層配線板の製造方法によれば、
たとえば導電性支持基体面に一体的に配置した金属層
が、電気銅メッキに当たって所要の電極機能を果たす一
方、導電性支持基体面に対して良好な剥離性を呈するた
め、所要の多層配線層形成後における剥離・転写工程
で、導電性支持基体面に対接する絶縁層が破損などする
恐れないし問題は全面的に解消される。つまり、本発明
に係る製造方法によれば、構造的に寸法精度や絶縁構成
など良好で、信頼性の高い多層配線板を容易に、かつ歩
留まりよく製造し得る。また、除去すべき金属膜のソフ
トエッチング工程においては、積層している金属膜が相
互に色違いなどしているため、目視的にソフトエッチン
グの進行程度を知り得ることになり、生産性などにも大
きく寄与する。According to the method for manufacturing a multilayer wiring board according to the present invention,
For example, the metal layer integrally arranged on the surface of the conductive supporting substrate fulfills the required electrode function upon electrolytic copper plating, while exhibiting a good peeling property from the surface of the conductive supporting substrate. In the later peeling / transferring process, there is no fear that the insulating layer that contacts the surface of the conductive supporting substrate is damaged, or the problem is completely solved. That is, according to the manufacturing method of the present invention, it is possible to easily manufacture a multilayer wiring board having good dimensional accuracy and insulation configuration structurally and high reliability, and at a high yield. Further, in the soft etching process of the metal film to be removed, since the laminated metal films have different colors from each other, it is possible to visually confirm the progress of the soft etching, which may affect productivity. Also greatly contributes.
【０００９】[0009]
【実施例】以下図１〜図10を参照して本発明の実施例を
説明する。Embodiments of the present invention will be described below with reference to FIGS.
【００１０】実施例１ 図１〜図10は本発明に係る配線板の製造方法の一実施態
様例を模式的に示したもので、次のように行われてい
る。先ず、導電性を有する支持基体として、たとえば厚
さ 0.3mmのステンレス薄板１を用意し、このステンレス
薄板１面に、たとえばメッキ法により剥離性の金属膜
２、たとえばニッケル(Ni)系の金属層を被着形成する
（図１）。次いで、前記被着形成した剥離性の金属膜２
面上に、フォトレジストフイルム３を貼合わせた後（図
２）、そのフォトレジストフイルム３に選択的な露光・
現像処理を施して、第１のメッキレジストパターン４化
する（図３）。 上記第１のメッキレジストパターン４
を形成した後、前記ステンレス薄板１を陰極として電気
銅メッキ処理を行い、露出している剥離性金属膜２面上
に銅を逆パターンに成長させ、第１のメッキレジストパ
ターン４と一平面を成す第１の銅メッキ層５を形成する
（図４）。その後、前記第１の銅メッキ層５を形成した
面上に、フォトレジストフイルムを貼合わせ、かつ選択
的な露光・現像処理を施して、第２のメッキレジストパ
ターン６を形成する（図５）。この第２のメッキレジス
トパターン６形成に当たっては、前記第１の銅メッキ層
５の少なくとも一部を露出させ、ステンレス薄板１との
電気的な接続を保持する構成に設定する。Embodiment 1 FIGS. 1 to 10 schematically show an embodiment of a method for manufacturing a wiring board according to the present invention, which is carried out as follows. First, a stainless thin plate 1 having a thickness of 0.3 mm, for example, is prepared as a conductive support substrate, and a metal film 2 that is removable by plating, for example, a nickel (Ni) -based metal layer, is formed on the surface of the stainless thin plate 1. Are deposited (FIG. 1). Next, the peelable metal film 2 formed by the deposition
After pasting the photoresist film 3 on the surface (Fig. 2), the photoresist film 3 is selectively exposed to light.
A development process is performed to form the first plating resist pattern 4 (FIG. 3). The first plating resist pattern 4
After the formation, copper electroplating is performed using the stainless steel thin plate 1 as a cathode, and copper is grown in a reverse pattern on the exposed surface of the peelable metal film 2 to form a plane with the first plating resist pattern 4. A first copper plating layer 5 is formed (FIG. 4). After that, a photoresist film is attached to the surface on which the first copper plating layer 5 is formed, and a selective exposure / development process is performed to form a second plating resist pattern 6 (FIG. 5). . In forming the second plating resist pattern 6, at least a part of the first copper plating layer 5 is exposed and the electrical connection with the stainless thin plate 1 is maintained.
【００１１】次いで、前記第２のメッキレジストパター
ン６をパターンニングした面上に、たとえばスパッタ法
により第２の金属膜7a，7b、たとえば CuOx 系の金属層
を被着形成する（図６）。ここで、 CuOx 系金属層を被
着して第２の金属膜7a，7bを形成するとき、第２の金属
膜7a，7bは互いに離隔し電気的にも不連続な形態を採っ
ている。こうして、第２の金属膜7a，7bを被着形成した
後、前記ステンレス薄板１を陰極として電気銅メッキ処
理を行い、露出している金属膜7a面上に銅を逆パターン
に成長させ、第２のメッキレジストパターン６と一平面
を成す第２の銅メッキ層８を形成する（図７）。その
後、前記第２のメッキレジストパターン６面上の金属膜
7bを、選択的にソフトエッチング処理で除去し（図
８）、要すれば、前記図５〜図８に図示した工程を適宜
繰り返して所要の多層配線層を形成してから、絶縁性支
持体９面上に配置したプリプレグ層10面に、最終的に形
成した銅メッキ層側を対接させた形で、ステンレス薄板
１から剥離・転写する（図９）。次いで、前記プリプレ
グ層10を加熱硬化などさせ、前記形成した配線層を絶縁
性支持体９面に一体化させた後、前記剥離・転写で露出
した第１の金属膜２をソフトエッチング処理により除去
することにより、型崩れ（たとえば表面の絶縁部など損
傷されていない）など回避された高精度で、機能的にも
信頼性の高い多層配線板が得られた（図10）。Then, second metal films 7a and 7b, for example, a CuO x type metal layer is deposited on the surface patterned with the second plating resist pattern 6 by, for example, a sputtering method (FIG. 6). . Here, when the second metal films 7a and 7b are formed by depositing a CuO x based metal layer, the second metal films 7a and 7b are separated from each other and are electrically discontinuous. . After depositing the second metal films 7a and 7b in this way, electrolytic copper plating is performed using the stainless steel thin plate 1 as a cathode to grow copper in a reverse pattern on the exposed surface of the metal film 7a. A second copper plating layer 8 is formed which is flush with the second plating resist pattern 6 (FIG. 7). Then, a metal film on the surface of the second plating resist pattern 6 is formed.
7b is selectively removed by a soft etching process (FIG. 8), and if necessary, the steps shown in FIGS. 5 to 8 are appropriately repeated to form a required multilayer wiring layer, and then the insulating support is formed. The prepreg layer 10 arranged on the 9th surface is peeled off and transferred from the stainless steel thin plate 1 with the finally formed copper plating layer side being in contact with it (FIG. 9). Then, the prepreg layer 10 is heated and cured to integrate the formed wiring layer on the surface of the insulating support 9, and then the first metal film 2 exposed by the peeling / transfer is removed by a soft etching process. By doing so, it was possible to obtain a highly accurate and functionally reliable multilayer wiring board in which the shape collapse (for example, the insulating portion of the surface was not damaged) was avoided (Fig. 10).
【００１２】実施例２ 本実施例の基本的な実施態様は、前記実施例１の場合
で、先ず、導電性を有する支持基体として、たとえば厚
さ 0.3mmのステンレス薄板１を用意し、このステンレス
薄板１面に、たとえばメッキ法により剥離性の第１の金
属膜２、たとえばCu系の金属層を被着形成し（図１）、
次いで、前記第１の金属膜２上に、フォトレジストフイ
ルム３を貼合わせた後（図２）、そのフォトレジストフ
イルム３に選択的な露光・現像処理を施して、第１のメ
ッキレジストパターン４化する（図３）。Example 2 The basic embodiment of this example is the case of Example 1 above. First, a stainless steel thin plate 1 having a thickness of 0.3 mm, for example, is prepared as a conductive support base, and this stainless steel is used. A peelable first metal film 2, for example, a Cu-based metal layer is formed on the surface of the thin plate 1 by plating (FIG. 1),
Then, after a photoresist film 3 is laminated on the first metal film 2 (FIG. 2), the photoresist film 3 is selectively exposed and developed to form a first plating resist pattern 4 (Fig. 3).
【００１３】上記第１のメッキレジストパターン４を形
成した後、前記ステンレス薄板１を陰極として、さらに
Cu系の金属とは色，エッチング速度などが異なる異種の
第３の金属層（図示せず）、たとえば半田系の金属をメ
ッキ処理して、露出している第３の金属膜面上に半田を
逆パターンに成長させ、第１のメッキレジストパターン
４と一平面を成す第１の半田メッキ層５を形成する（図
４）。その後、前記第１の銅メッキ層５を形成した面上
に、フォトレジストフイルムを貼合わせ、かつ選択的な
露光・現像処理を施して、第２のメッキレジストパター
ン６を形成する（図５）。この第２のメッキレジストパ
ターン６形成に当たっては、前記第１の半田メッキ層５
の少なくとも一部を露出させ、ステンレス薄板１との電
気的な接続を保持する構成に設定する。After forming the first plating resist pattern 4, the stainless thin plate 1 is used as a cathode, and
A third metal layer (not shown) different in color and etching rate from the Cu-based metal, for example, a solder-based metal is plated and soldered on the exposed third metal film surface. Are grown in a reverse pattern to form a first solder plating layer 5 that is flush with the first plating resist pattern 4 (FIG. 4). After that, a photoresist film is attached to the surface on which the first copper plating layer 5 is formed, and a selective exposure / development process is performed to form a second plating resist pattern 6 (FIG. 5). . In forming the second plating resist pattern 6, the first solder plating layer 5 is formed.
Is exposed and at least a part thereof is set so as to maintain electrical connection with the stainless thin plate 1.
【００１４】次いで、前記第２のメッキレジストパター
ン６をパターンニングした面上に、たとえばスパッタ法
により第２の金属膜7a，7b、たとえば CuOx 系の金属層
を被着形成する（図６）。ここで、 CuOx 系金属層を被
着して第２の金属膜7a，7bを形成するとき、第２の金属
膜7a，7bは互いに離隔し電気的にも不連続な形態を採っ
ている。こうして、第２の金属膜7a，7bを被着形成した
後、前記ステンレス薄板１を陰極として電気銅メッキ処
理を行い、露出している金属膜7a面上に銅を逆パターン
に成長させ、第２のメッキレジストパターン６と一平面
を成す第２の銅メッキ層８を形成する（図７）。その
後、前記第２のメッキレジストパターン６面上の金属膜
7bを、選択的にソフトエッチング処理で除去し（図
８）、要すれば、前記図５〜図８に図示した工程を適宜
繰り返して所要の多層配線層を形成してから、絶縁性支
持体９面上に配置したプリプレグ層10面に、最終的に形
成した銅メッキ層側を対接させた形で、ステンレス薄板
１から剥離・転写する（図９）。次いで、前記プリプレ
グ層10を加熱硬化（10′）などさせ、前記形成した配線
層を絶縁性支持体９面に一体化させた後、前記剥離・転
写で露出した第１の金属膜２および第３の金属膜を順次
ソフトエッチング処理により除去することにより、型崩
れ（たとえば表面の絶縁部など損傷されていない）など
回避された高精度で、機能的にも信頼性の高い多層配線
板が得られた（図10）。なお、この実施例における第１
の金属膜２および第３の金属膜のソフトエッチングで
は、第１の金属膜２と第３の金属膜とで、互いに色が異
なっているため、第１の金属膜２のエッチング除去状態
や、エッチングが第３の金属膜に移行して最終段階に入
っている状況など目視判定も可能で、生産性ないし製造
管理面での効率向上に大きく寄与することが確認され
た。Then, second metal films 7a and 7b, for example, a CuO x type metal layer is deposited on the surface patterned with the second plating resist pattern 6 by, for example, a sputtering method (FIG. 6). . Here, when the second metal films 7a and 7b are formed by depositing a CuO x based metal layer, the second metal films 7a and 7b are separated from each other and are electrically discontinuous. . After depositing the second metal films 7a and 7b in this way, electrolytic copper plating is performed using the stainless steel thin plate 1 as a cathode to grow copper in a reverse pattern on the exposed surface of the metal film 7a. A second copper plating layer 8 is formed which is flush with the second plating resist pattern 6 (FIG. 7). Then, a metal film on the surface of the second plating resist pattern 6 is formed.
7b is selectively removed by a soft etching process (FIG. 8), and if necessary, the steps shown in FIGS. 5 to 8 are appropriately repeated to form a required multilayer wiring layer, and then the insulating support is formed. The prepreg layer 10 arranged on the 9th surface is peeled off and transferred from the stainless steel thin plate 1 with the finally formed copper plating layer side being in contact with it (FIG. 9). Next, the prepreg layer 10 is heat-cured (10 ′) or the like to integrate the formed wiring layer on the surface of the insulating support 9, and then the first metal film 2 and the first metal film 2 exposed by the peeling / transferring By sequentially removing the metal film of No. 3 by soft etching treatment, a highly accurate and functionally reliable multilayer wiring board in which the shape collapse (for example, the insulating portion of the surface is not damaged) is avoided can be obtained. (Fig. 10). The first example in this embodiment
In the soft etching of the metal film 2 and the third metal film, since the colors of the first metal film 2 and the third metal film are different from each other, the etching removal state of the first metal film 2 and It was confirmed that it is possible to make a visual judgment such as the situation where the etching has moved to the third metal film and is in the final stage, and it greatly contributes to the improvement of efficiency in terms of productivity and manufacturing control.
【００１５】前記では、導電性支持基体としてステンレ
ス薄板を用いたが、その代わりに、たとえば銅７アルミ
の箔ないし薄板などを始め，要するに電気メッキの電極
として十分機能し得る導電性を有するものであれば特に
限定されない。In the above description, the thin stainless steel plate is used as the conductive support base, but instead of this, for example, a foil or thin plate of copper 7 aluminum, etc., that is, one having sufficient conductivity to function sufficiently as an electrode for electroplating. There is no particular limitation as long as it exists.
【００１６】[0016]
【発明の効果】上記説明から分かるように、本発明に係
る配線板の製造方法によれば、比較的簡単な操作で、高
精度でかつ機能的な信頼性も高い配線板を容易に、かつ
歩留まりよく製造し得る。すなわち、電気銅メッキの利
用によって、効率的に所要の配線パターンを形成し得る
ばかりでなく、剥離性の金属膜の介在によ導電性支持基
体面から、絶縁層を何等破損することなく剥離・転写さ
れる。また、前記配線パターン形成に当たって、配線パ
ターン層間の絶縁層としてメッキレジストパターン（フ
ォトレジストで形成されている）をそのまま利用するの
で工程を省略し得るし、前記フォトレジストの性質（乱
反射防止など）に基づく良好な解像性から、高精度の配
線パターン構成を採り得るし、また２次的な半田の供給
も要しない。As can be seen from the above description, according to the method for manufacturing a wiring board of the present invention, it is possible to easily and easily obtain a wiring board with high accuracy and high functional reliability by a relatively simple operation. It can be manufactured with high yield. That is, not only can the required wiring pattern be formed efficiently by using electrolytic copper plating, but also the insulating layer can be peeled off from the surface of the conductive support substrate by the interposition of the peelable metal film without any damage. Transcribed. Further, in forming the wiring pattern, since the plating resist pattern (formed of photoresist) is used as an insulating layer between the wiring pattern layers as it is, steps can be omitted, and the properties of the photoresist (preventing diffused reflection, etc.) can be eliminated. Based on the good resolution based on this, a highly accurate wiring pattern configuration can be adopted, and secondary solder supply is not required.
【図１】本発明に係る多層配線板の製造方法の実施態様
例において導電性支持基体面に第１の金属膜を被着形成
した状態を示す断面図。FIG. 1 is a cross-sectional view showing a state in which a first metal film is adhered and formed on a surface of a conductive supporting substrate in an embodiment example of a method for manufacturing a multilayer wiring board according to the present invention.
【図２】本発明に係る多層配線板の製造方法の実施態様
例において第１の金属膜面上にフォトレジスト層を被着
形成した状態を示す断面図。FIG. 2 is a cross-sectional view showing a state in which a photoresist layer is deposited on the first metal film surface in the embodiment example of the method for manufacturing a multilayer wiring board according to the present invention.
【図３】本発明に係る多層配線板の製造方法の実施態様
例においてフォトレジスト層を第１のメッキレジストパ
ターン化した状態を示す断面図。FIG. 3 is a cross-sectional view showing a state in which the photoresist layer is formed into a first plating resist pattern in the embodiment example of the method for manufacturing a multilayer wiring board according to the present invention.
【図４】本発明に係る多層配線板の製造方法の実施態様
例において第１のメッキレジストパターン面に第１の銅
メッキ層を成長させた状態を示す断面図。FIG. 4 is a cross-sectional view showing a state in which a first copper plating layer is grown on the first plating resist pattern surface in the embodiment example of the method for manufacturing a multilayer wiring board according to the present invention.
【図５】本発明に係る多層配線板の製造方法の実施態様
例において成長させた第１の銅メッキ層面に第２のメッ
キレジストパターンを形成した状態を示す断面図。FIG. 5 is a cross-sectional view showing a state in which a second plating resist pattern is formed on the surface of the first copper plating layer grown in the embodiment example of the method for manufacturing a multilayer wiring board according to the present invention.
【図６】本発明に係る多層配線板の製造方法の実施態様
例において第２のメッキレジストパターン形成面に第２
の金属膜を被着形成した状態を示す断面図。FIG. 6 is a view showing a second plating resist pattern forming surface on the second plating resist pattern forming surface in the embodiment example of the method for manufacturing a multilayer wiring board according to the present invention.
3 is a cross-sectional view showing a state in which the metal film of FIG.
【図７】本発明に係る多層配線板の製造方法の実施態様
例において第２の金属膜を被着形成面に第２の銅メッキ
層を成長させた状態を示す断面図。FIG. 7 is a cross-sectional view showing a state in which a second copper plating layer has been grown on the surface on which the second metal film is deposited in the embodiment example of the method for manufacturing a multilayer wiring board according to the present invention.
【図８】本発明に係る多層配線板の製造方法の実施態様
例において第２の銅メッキ層を成長させた後露出してい
る第２の金属膜をソフトエッチング除去した状態を示す
断面図。FIG. 8 is a cross-sectional view showing a state in which the exposed second metal film is removed by soft etching after growing the second copper plating layer in the embodiment example of the method for manufacturing a multilayer wiring board according to the present invention.
【図９】本発明に係る多層配線板の製造方法の実施態様
例において形成した配線層を導電性支持基体面から剥離
・転写する状態を示す断面図。FIG. 9 is a cross-sectional view showing a state in which the wiring layer formed in the embodiment example of the method for manufacturing a multilayer wiring board according to the present invention is peeled off and transferred from the surface of a conductive supporting substrate.
【図１０】本発明に係る多層配線板の製造方法で製造し
た配線板の構造例を示す断面図。FIG. 10 is a cross-sectional view showing a structural example of a wiring board manufactured by the method for manufacturing a multilayer wiring board according to the present invention.
１…導電性支持基体 ２…第１の金属膜 ３…フォ
トレジスト層 ４…第１のメッキレジストパターン
５…第１の銅メッキ層 ６…第２のメッキレジスト
パターン 7a，7b…第２の金属膜 ８…第２の銅メ
ッキ層 ９…絶縁性支持体 10…プリプレグ層 10′…プリ
プレグ硬化層DESCRIPTION OF SYMBOLS 1 ... Conductive support base 2 ... 1st metal film 3 ... Photoresist layer 4 ... 1st plating resist pattern
5 ... 1st copper plating layer 6 ... 2nd plating resist pattern 7a, 7b ... 2nd metal film 8 ... 2nd copper plating layer 9 ... Insulating support body 10 ... Prepreg layer 10 '... Prepreg hardening layer
Claims (2)
性の第１の金属膜を一体的に被着形成する工程と、 (B) 前記第１の金属被膜面上にフォトレジスト層を配置
し選択的な露光・現像により第１のメッキレジストパタ
ーンを形成する工程と、 (C) 前記第１の金属膜を陰極として電気銅メッキ処理を
施し、第１のメッキレジストパターン上面と同一面を成
すように露出する第１の金属膜面を選択的に第１の銅メ
ッキ層で肉盛りする工程と、 (D) 前記第１の銅メッキ層で肉盛りし平面化した面上に
フォトレジスト層を配置し選択的な露光・現像により肉
盛り領域の一部を露出させて第２のメッキレジストパタ
ーンを形成する工程と、 (E) 前記第２のメッキレジストパターン形成面上に、第
２のメッキレジストパターン面および露出面に区分され
た第２の金属膜を被着形成する工程と、 (F) 前記第２のメッキレジストパターンによる露出面に
被着形成された第２の金属膜を陰極として電気銅メッキ
処理を施し、第２のメッキレジストパターン上面と同一
面を成すように露出する第２の金属膜面を選択的に第２
の銅メッキ層で肉盛りする工程と、 (G) 前記第２の銅メッキ層で選択的に肉盛りした後、第
２のメッキレジストパターン面上に被着形成された第２
の金属膜をソフトエッチングにより選択的に除去する工
程と、 (H) 前記(D) 〜(G) の工程を繰り返した後、形成した多
層積層体を導電性を有する支持基体面から転写・剥離し
て第１の金属膜をソフトエッチングにより除去する工程
とを具備して成ることを特徴とする多層配線板の製造方
法。1. A step of integrally depositing and forming a peelable first metal film on a surface of a conductive support substrate, and (B) a photoresist on the surface of the first metal film. A step of arranging layers to form a first plating resist pattern by selective exposure / development, and (C) performing electrolytic copper plating using the first metal film as a cathode to form an upper surface of the first plating resist pattern. A step of selectively overlaying the exposed first metal film surface so as to form the same surface with a first copper plating layer, and (D) on a surface that is overlayed with the first copper plating layer and planarized And a step of forming a second plating resist pattern by exposing a part of the built-up area by selectively exposing and developing a photoresist layer on the second plating resist pattern forming surface. , A second divided into a second plating resist pattern surface and an exposed surface And (F) electrolytic copper plating is performed using the second metal film deposited on the exposed surface of the second plating resist pattern as a cathode to form a second plating resist. The second metal film surface exposed so as to be flush with the top surface of the pattern is selectively used as the second metal film surface.
(G) a step of depositing with the copper plating layer, and a second step of depositing and forming on the second plating resist pattern surface after selectively depositing with the second copper plating layer.
After the step of selectively removing the metal film by soft etching and (H) the steps of (D) to (G) are repeated, the formed multilayer laminate is transferred / peeled from the supporting substrate surface having conductivity. And a step of removing the first metal film by soft etching, the manufacturing method of the multilayer wiring board.
性の第１の金属膜を一体的に被着形成する工程と、 (B) 前記第３の金属層面上にフォトレジスト層を配置し
選択的な露光・現像により第１のメッキレジストパター
ンを形成する工程と、 (c) 前記第１の金属被膜面上に第１の金属とは異種でか
つ導電性を有する第３の金属層をメッキ処理により、第
１のメッキレジストパターン上面と同一面を成すように
露出する第１の金属膜面を選択的に第１の銅メッキ層で
肉盛りする工程と、 (D) 前記第３の金属膜を陰極として電気銅メッキ処理を
施し、第１のメッキレジストパターン上面と同一面を成
すように露出する第３の金属膜面を選択的に第１の銅メ
ッキ層で肉盛りする工程と、 (E) 前記第１の銅メッキ層で肉盛りし平面化した面上に
フォトレジスト層を配置し選択的な露光・エッチングに
より肉盛り領域の一部を露出させて第２のメッキレジス
トパターンを形成する工程と、 (F) 前記第２のメッキレジストパターン形成面上に、第
２のメッキレジストパターン面および露出面に区分され
た第２の金属膜を被着形成する工程と、 (G) 前記第２のメッキレジストパターンによる露出面に
被着形成された第２の金属膜を陰極として電気銅メッキ
処理を施し、第２のメッキレジストパターン上面と同一
面を成すように露出する第２の金属膜面を選択的に第２
の銅メッキ層で肉盛りする工程と、 (H) 前記第２の銅メッキ層で肉盛りした後、第２のメッ
キレジストパターン面上に被着形成された第２の金属膜
をソフトエッチングにより選択的に除去する工程と、 (I) 前記(E) 〜(H) の工程を繰り返し多層積層体を形成
した後、多層積層体を導電性を有する支持基体面から転
写・剥離して第１の金属膜をソフトエッチングにより除
去する工程とを具備して成ることを特徴とする多層配線
板の製造方法。2. A step of (A) integrally forming a peelable first metal film on the surface of a conductive support substrate, and (B) a photoresist layer on the surface of the third metal layer. And forming a first plating resist pattern by selective exposure / development, and (c) a third metal having a conductivity type different from that of the first metal on the first metal coating surface. A step of selectively depositing a first copper film layer on the exposed first metal film surface by plating the metal layer so as to be flush with the upper surface of the first plating resist pattern; and (D) An electrolytic copper plating process is performed using the third metal film as a cathode, and the exposed third metal film surface is flush with the first copper resist layer so as to be flush with the upper surface of the first plating resist pattern. And (E) a photoresist is formed on the flattened surface by overlaying with the first copper plating layer. Forming a second plating resist pattern by exposing a part of the built-up region by selective exposure and etching, and (F) forming a second plating resist pattern forming surface on the second plating resist pattern forming surface. Second step of depositing a second metal film divided into a plating resist pattern surface and an exposed surface, and (G) a second metal film deposited on the exposed surface by the second plating resist pattern. Is used as a cathode to perform electrolytic copper plating, and selectively exposes the exposed second metal film surface so as to be flush with the upper surface of the second plating resist pattern.
And (H) softening the second metal film deposited on the second plating resist pattern surface after overlaying with the second copper plating layer. The step of selectively removing and (I) the steps (E) to (H) are repeated to form a multi-layer laminate, and then the multi-layer laminate is transferred / peeled from the surface of the conductive support substrate to form a first layer. And a step of removing the metal film by soft etching, the method of manufacturing a multilayer wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22983792A JP3140859B2 (en) | 1992-08-28 | 1992-08-28 | Method for manufacturing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22983792A JP3140859B2 (en) | 1992-08-28 | 1992-08-28 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0677650A true JPH0677650A (en) | 1994-03-18 |
| JP3140859B2 JP3140859B2 (en) | 2001-03-05 |
Family
ID=16898459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22983792A Expired - Fee Related JP3140859B2 (en) | 1992-08-28 | 1992-08-28 | Method for manufacturing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3140859B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6591491B2 (en) * | 2000-03-22 | 2003-07-15 | Nitto Denko Corporation | Method for producing multilayer circuit board |
| JP2009123971A (en) * | 2007-11-15 | 2009-06-04 | Nippon Mektron Ltd | Manufacturing method for circuit wiring board with bump |
-
1992
- 1992-08-28 JP JP22983792A patent/JP3140859B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6591491B2 (en) * | 2000-03-22 | 2003-07-15 | Nitto Denko Corporation | Method for producing multilayer circuit board |
| JP2009123971A (en) * | 2007-11-15 | 2009-06-04 | Nippon Mektron Ltd | Manufacturing method for circuit wiring board with bump |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3140859B2 (en) | 2001-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5369881A (en) | Method of forming circuit wiring pattern | |
| US7098132B2 (en) | Method of manufacturing flexible wiring board | |
| US8277668B2 (en) | Methods of preparing printed circuit boards and packaging substrates of integrated circuit | |
| JPS62230091A (en) | Manufacture of wiring board | |
| US6350365B1 (en) | Method of producing multilayer circuit board | |
| US6977349B2 (en) | Method for manufacturing wiring circuit boards with bumps and method for forming bumps | |
| US7080448B2 (en) | PCB with inlaid outer-layer circuits and production methods thereof | |
| JP4052434B2 (en) | Multilayer substrate and manufacturing method thereof | |
| JP2001111201A (en) | Method of manufacturing wiring board and wiring board using the same | |
| KR20130031592A (en) | Method for manuracturing printed circuit board with via and fine pitch circuit and printed circuit board by the same method | |
| JPH04127492A (en) | Material for printed wiring, manufacture thereof and printed wiring board | |
| JPH0677650A (en) | Production of multilayer wiring board | |
| JP2006013030A5 (en) | ||
| JP2002290048A (en) | Via forming method in multilayer circuit board | |
| JP3948105B2 (en) | Method for manufacturing multilayer printed circuit board | |
| JP4449228B2 (en) | Manufacturing method of inspection jig | |
| JPH08264953A (en) | Wiring forming method of multilayer printed wiring board | |
| JPH06177277A (en) | Manufacture of semiconductor device | |
| JPH10335826A (en) | Multilayered wiring circuit board and manufacture thereof | |
| JPH02301187A (en) | Manufacture of both-sided wiring board | |
| JPH0964536A (en) | Thin film wiring board and production thereof | |
| JP2004072027A (en) | Method of manufacturing wiring board with bump electrode | |
| JPH1117059A (en) | Ball grid array board and continued body thereof | |
| JPH0438157B2 (en) | ||
| JPH0621651A (en) | Multilayer wiring circuit board and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20001205 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071215 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081215 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091215 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091215 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101215 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111215 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |