JPH04217121A - Parallel/serial conversion circuit - Google Patents

Abstract

PURPOSE:To attain efficient serial/parallel conversion by a small number of registers. CONSTITUTION:Registers R are arranged at the shape of the matrix of (n)X(n), and data selector S having two inputs (a/b) and one output are arranged on the input sides of the respective registers R. The registers R are horizontally connected through the (a) side inputs of these data selectors A, and the registers R are vertically connected through the inputs to the (b) sides. Input data are supplied to the vertical or horizontal direction of the matrix composed of the registers R, and output data are taken out in the horizontal or vertical direction of the matrix.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel/serial conversion circuit used, for example, in digital processing for image compression.

0002

[Prior Art] For example, when obtaining transform values of discrete cosine transform in image compression, matrix calculations in fast Fourier transform, and product-sum calculation circuits used in digital processing of images, audio, etc., for example, n pieces of data are processed. Parallel processing is performed to obtain n solutions at the same time. Such processing generally involves converting parallel data into serial data and processing the data bit by bit.

[0003] Therefore, as a parallel/serial conversion circuit used for such processing, the one shown in FIG. 6 has been known. That is, the example shown in the figure shows a case where 4-bit parallel data is converted from parallel to serial in units of four. In this figure, each R is a 1-bit register consisting of, for example, a D-flip-flop. For example, four registers R are provided in parallel, and these registers R are further connected in four stages to form a 4×
4 shift registers are formed. Further, 10 is a 4-bit parallel data input section. Each bit of data from the parallel data input section 10 is supplied to the leftmost register R forming the above-mentioned shift register. Furthermore, these registers R are connected in parallel to four registers R' via the b-side input of a data selector S having two inputs (a/b) and one output for each of the above-mentioned stages. These four registers R' for each stage are sequentially connected via the a-side input of the data selector S. The registers R' at the bottom of each stage are serial data processors 1 to 1.
Connected to 4.

Therefore, in this circuit, the data input section 1
Parallel data starting from 0 is supplied to each register R, and these data are sequentially shifted in the horizontal direction of the drawing. When four pieces of data have been input, the data selector S is switched to the register R side, and the data written in the register R is transferred to the register R'. Furthermore, the data selector S is switched to the side that sequentially connects the registers R', and the data written in the registers R' is shifted in the vertical direction. As a result, 4 bits of parallel data are parallel/serial converted four by four and supplied to the serial data processors 1-4. Further, while the data in register R' is being shifted in the vertical direction, subsequent parallel data is supplied from the data input section 10 to register R and sequentially shifted in the horizontal direction.

However, in the case of this circuit, for example, the above-mentioned 4
The number of registers R and R' required to convert (bits) x 4 (pieces) data from parallel to serial is 32, which is twice the total number of bits of the data to be converted, 4 x 4 = 16. It has become. On the other hand, the data written to register R is
It is not needed after the data is transferred to register R'. However, in the above-described circuit, the previous data remains in register R even after the data is transferred. This data remains until subsequent parallel data is supplied and sequentially shifted horizontally. This means that registers R and R' are not effectively used. Furthermore, if such unnecessary data remains, that amount of power will be wasted.

[0006]

The problem to be solved is that the registers R and R' are not used effectively and power is wasted.

[0007]

[Means for Solving the Problems] In the present invention, registers R each having one bit are arranged in an n×n (4×4) matrix, and a data selector S having two inputs and one output is connected to the input of each register R. is provided, and one of the two inputs of each data selector S connects the matrix in the vertical direction,
On the other hand, the matrix is connected horizontally, and input data (output of the data input section 10) is supplied vertically or horizontally to the matrix, and output data (input of the serial data processors 1 to 4) is supplied to the matrix. This is a parallel/serial conversion circuit that extracts the above matrix in the horizontal or vertical direction.

[0008]

[Operation] According to this, registers are arranged in a matrix, input data is supplied in the vertical or horizontal direction of the matrix, and output data is taken out in the horizontal or vertical direction of the matrix. Efficient parallel/serial conversion can be performed using registers.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The example shown in FIG. 1 shows a case where 4 bits of parallel data are converted from parallel to serial in groups of four. In this figure, each R is a 1-bit register consisting of, for example, a D-flip-flop. This register R
are arranged, for example, in a 4×4 matrix. Numbers in parentheses indicate positions on the matrix. Also, each S is 2
This is a data selector with one input (a/b) and one output. These data selectors S are provided on the input side of the register R, respectively. And through these data selectors S,
A resistor R is connected horizontally and vertically. That is, for example, the register R is set in the horizontal direction (11 to 14, 21 to 24, 31 to 34,
41 to 44). Also, b of data selector S
Through the side inputs, register R is connected vertically (11 to 41,
12-42, 13-43, 14-44).

Further, 10 is a 4-bit parallel data input section, for example. The data from the parallel data input section 10 is supplied to the a-side input of a data selector S provided on the input side of the register R (11, 21, 31, 41) at the left end of the matrix, respectively. Further, the data from the parallel data input section 10 is inputted to the registers R (11, 12, 13, 1) at the upper end of the matrix, respectively.
4) is supplied to the b-side input of the data selector S provided on the input side. Note that the data selector S provided on the input side of the register R (11) is supplied with the same data for both inputs on the a and b sides, so the data selector S in this part can be omitted.

Further, for example, a data selector S' is also provided on the output side of the register R (14, 24, 34, 44) at the right end of the matrix. and register R (14, 24
, 34, 44) is sent to a of data selector S'.
Serial data processors 1 to 4 are supplied through side inputs. For example, register R at the lower end of the matrix
The output data (41, 42, 43, 44) is supplied to the serial data processors 1-4 through the b-side input of the data selector S'. Note that the data selector S' provided on the output side of the register R (44) is supplied with the same data for both inputs on the a and b sides, so the data selector S' in this part can be omitted.

Therefore, in this circuit, for example, in a state where the data selectors S and S' select the input on the a side, the circuit configuration becomes as shown in FIG. 2. In this state, the data from the parallel data input section 10 is shifted through the matrix of the register R in the horizontal direction. The data written to the register R at time T4 when the four pieces of data are supplied becomes as shown in the figure.

At the next time T5, the data selectors S and S' select the b-side input. As a result, the circuit configuration is shown in Figure 3.
It becomes as shown in . In this state, parallel data input section 1
Data from 0 is shifted vertically through the matrix of register R. At this time, the data written to the register R up to time T4 is sequentially stored in the lower register R (41
, 42, 43, 44) and supplied to the serial data processors 1-4 through the b-side input of the data selector S'. As a result, data supplied from the data input section 10 in the form of parallel data is converted into serial data and supplied to the serial data processors 1 to 4.

Furthermore, the data written to register R at time T8 is as shown in FIG. And the next point T9
Then, the data selectors S and S' again select the input on the a side. As a result, the circuit configuration becomes as shown in FIG. 5. In this state, the data from the parallel data input section 10 is shifted through the matrix of the register R in the horizontal direction. At this time, the data written to register R up to time T8 is sequentially written to the rightmost register R (14, 24, 34, 44).
) and supplied to the serial data processors 1 to 4 through the a-side input of the data selector S'. As a result, data supplied from the data input section 10 in the form of parallel data is converted into serial data and supplied to the serial data processors 1 to 4.

Thus, according to this circuit, the registers R are arranged in a matrix, and input data (data input section 10
By supplying the output data (outputs of serial data processors 1 to 4) in the vertical or horizontal direction of the matrix and taking out the output data (inputs of serial data processors 1 to 4) in the horizontal or vertical direction of the matrix, efficiency can be achieved with a small number of registers R. This allows for good parallel/serial conversion.

That is, according to the above-mentioned circuit, the number of registers R required for parallel/serial conversion of the above-mentioned 4 (bits) x 4 (pieces) data is 16, for example. This is equal to the total number of bits of data to be converted, 4×4=16, which is halved compared to the circuit described in the prior art. Furthermore, as is clear from the above description, only data necessary for conversion is always written in register R. Therefore, the register R is effectively used, and power is not wasted due to unnecessary data remaining. This is especially advantageous when operating the circuit at high speed.

Note that the above-mentioned circuit is not limited to parallel/serial conversion of 4 (bits) x 4 (pieces) data as described above, but can also be used for parallel/serial conversion of arbitrary n (bits) x n (pieces) data. Applicable to serial conversion.

[0018]

According to the present invention, registers are arranged in a matrix, input data is supplied in the vertical or horizontal direction of the matrix, and output data is taken out in the horizontal or vertical direction of the matrix. This has made it possible to perform efficient parallel/serial conversion with a small number of registers.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a parallel/serial conversion circuit according to the present invention.

FIG. 2 is an explanatory diagram showing the state of the parallel/serial conversion circuit at time T4.

FIG. 3 is an explanatory diagram showing the state of the parallel/serial conversion circuit at time T5.

FIG. 4 is an explanatory diagram showing the state of the parallel/serial conversion circuit at time T8.

FIG. 5 is an explanatory diagram showing the state of the parallel/serial conversion circuit at time T9.

FIG. 6 is a configuration diagram of a conventional parallel/serial conversion circuit.

[Explanation of symbols]

1 to 4 Serial data processor 10 Data input section R Register S Data selector

Claims (1)

[Claims] [Claim 1] There are n×n registers of 1 bit each.
are arranged in a matrix, and two inputs are input to each of the above registers.
A data selector with one input and one output is provided, one of the two inputs of each data selector connects the matrix in the vertical direction, and the other connects the matrix in the horizontal direction, and the input data is connected to the matrix in the horizontal direction. A parallel/serial conversion circuit configured to supply data in the vertical or horizontal direction and to take out output data in the horizontal or vertical direction of the matrix.