JPS634969B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a circuit that converts serial input data into parallel output data or parallel input data into serial output data at high speed.

[Prior art]

FIG. 1 shows an example of the configuration of a conventional serial-to-parallel conversion circuit. Figure 1 shows a circuit that converts a 4-bit serial signal into a parallel signal, or a parallel signal into a serial signal. 4-7 are serial (parallel) signal input terminals, 8-1
1 is a parallel (serial) signal output terminal, 1-1 to 1-4
is a shift register composed of D-type flip-flops, 2-1 to 2-4 are registers also composed of D-type flip-flops, and 3-1 to 3-4 are shift registers composed of D-type flip-flops.
Input 1 output selector, 15 is the main clock,
16 and 17 indicate selector control signals.
FIG. 2 is a timing chart for explaining the operation of the serial-to-parallel conversion circuit.

Input terminal 4 is synchronized with main clock 15.
Signals in units of 4 bits are input in order: D ₀₀ , D ₁₀ , D ₂₀ , D ₃₀ , . . . Similarly, input terminal 5 has
D ₀₁ , D ₁₁ , D ₂₁ , D ₃₁ ,..., D ₀₂ at input terminal 6,
D ₁₂ , D ₂₂ , D ₃₂ , ..., input terminal 7 has D ₀₃ , D ₁₃ ,
D ₂₃ , D ₃₃ , . . . signals in units of 4 bits are input in order. Main clock 15 sends 4-bit signals to shift registers 1-1 to 1-4, respectively.
each 4-bit signal is transferred to
They are simultaneously stored in bit-configured registers 2-1 to 2-4. 4-input 1-output selector 3-1 to 3-
4 collects data from predetermined locations in registers 2-1 to 2-4, and outputs data to each register according to control signals 16 and 17 and in synchronization with main clock 15.
Bit by bit is output to output terminals 8-11. For example, when control signals 16 and 17 are both "0",
Among the four inputs, the signal from 2-1 is output, and when the control signal 16 is "1" and the control signal 17 is "0", the signal from 2-2 is output.

In this way, the series input D ₀₀ of input terminal 4,
After a time delay determined by the circuit, D ₁₀ , D ₂₀ , and D ₃₀ are converted into parallel data D ₀₀ , D ₁₀ , D ₂₀ , and D ₃₀ and output. Series input D ₀₁ of input terminals 5, 6, 7,
_D11 , _D21 , _D31 , _D02 , _D12 , _D22 , _D32 , _D03 ,
The same applies to D ₁₃ , D ₂₃ , and D ₃₃ . In addition, the data of input terminals 4 to 7 are input in parallel D ₀₀ , D ₀₁ ,
When considered as D ₀₂ and D ₀₃ , the series output D ₀₀ ,
D ₀₁ , D ₀₂ and D ₀₃ are obtained from the output terminal 8. Parallel input _D10 , _D11 , _D12 , _D13 , _D20 , _D21 , _D22 , _D23 ,
The same applies to D ₃₀ , D ₃₁ , D ₃₂ and D ₃₃ .

By the way, the conventional serial-to-parallel conversion circuit shown in FIG. 1 is composed of a shift register, a register that simultaneously stores information transferred to the shift register, and a selector that controls information distribution. Therefore, there are disadvantages in that the number of D-type flip-flops constituting the register is large, the signal lines to the selector are complex, and the circuit size and signal propagation delay are large. Although FIG. 1 shows an example of a 4-bit serial-to-parallel conversion circuit, a serial-to-parallel conversion circuit that handles 8 bits or more has similar drawbacks.

[Purpose/Summary of the invention]

In order to solve the above-mentioned conventional drawbacks, the present invention aims to solve n×n
One selector and one for each register unit circuit.
By providing multiple flip-flops and controlling the signal flow alternately in the horizontal direction (row direction) and vertical direction (column direction), serial input data can be converted into parallel output data, or parallel input data can be converted into serial input data. The objective is to provide a circuit that converts at high speed.

[Embodiments of the invention]

FIG. 3 is a configuration diagram of an embodiment of the present invention,
Similar to FIG. 1, this figure shows a 4-bit serial-to-parallel conversion circuit. In Figure 3, 4 to 7 are serial (parallel) signal input terminals, 8 to 11 are parallel (series)
A signal output terminal, 12 is a switch for switching between conduction and non-conduction, and 13 is a selector with 2 inputs and 1 output.
Also, 1 and 2 are D type flip-flops, 14 is a ternary output buffer, 15 is a main clock, and 18
is a signal that controls the flow of data. The unit circuit is composed of one selector 13 and one D type flip-flop 1.

The signals of input terminals 4 to 7 are passed through the switch 12,
The signal is input to the flip-flop 1 via the selector 13 from the left side or the bottom side. The data stored in the flip-flop is connected so that it can be transferred both to the right and upward. Therefore, the output signal is taken out from the right side or upper side via the ternary output buffer 14 to the output terminals 8 to 11.

FIG. 4 is a diagram illustrating the operating principle of the serial-to-parallel conversion circuit of FIG. 3. The 4.times.4 grid in FIG. 4 corresponds to the 4.times.4 register comprised of the D-type flip-flop 1 in the center of FIG. Fourth
Figure 1 starts with data D ₀₀ , D ₀₁ , D ₀₂ , D ₀₃ from the left side.
is input. After inputting 4 bits of data respectively, the data shown in FIG. 4 is held in the 4×4 register. Figure 4 3
indicates that when the next bit of data is input, it is controlled so that it is input from the bottom of the register. At this time, among the data stored in the 4×4 register, the upper 4 bits of data D ₀₀ ,
D ₁₀ , D ₂₀ , D ₃₀ are the latest input data E ₀₀ , E ₀₁ , E ₀₂ ,
Pushed out to E ₀₃ , output terminal 8 ~ as parallel output
Appears on the 11th. Figure 4 4 is each 4 from the bottom
It shows the contents of a 4×4 register when bits of data are input. Next, when new data is input, parallel output can be similarly obtained by switching the path and transferring the data horizontally from left to right as shown in FIG. 4.

In FIG. 3, the switches 12, 2-input, 1-output selectors 13, and 3 provided on the left and lower sides
The value output buffer 14 and control signal 18 function to control the direction of the signal transfer path from input to output. That is, when a signal is transferred in the horizontal direction, the control signal 18 turns on the four switches 12 on the left and turns the four switches 12 on the bottom.
OFF, the 2-input 1-output selector 13 selects the signal from the D-type flip-flop located on the left, and the four ternary output buffers 14 on the right
enable, the upper four ternary output buffers 14 are
It is set to be disabled and maintain a high impedance state. Furthermore, when a signal is transferred in the vertical direction, the above situation is reversed. In this way, the switch 12, the 2-input 1-output selector 13,
By alternately switching the three-value output buffer 14 using the control signal 18, the serial-to-parallel conversion function shown in FIG. 2 can be realized.

As mentioned above, the serial-to-parallel converter circuit in Figure 3 is
Selectors 3-1 to 3-4 in Figure 1 are distributed and serial/parallel conversion is performed during transfer.
By replacing the circuits corresponding to the registers 2-1 to 2-4 in FIG. 1 with eight D-type flip-flops, it is possible to reduce the circuit scale and eliminate the complexity of wiring.

Next, the features of the circuit of the present invention will be described in consideration of LSI implementation of the serial-to-parallel conversion circuit. Here, considering a CMOS transistor as a device used in a logic LSI, and comparing the total number of transistors with a conventional circuit, in the case of a 4-bit serial-to-parallel conversion circuit, the conventional circuit has 1160 transistors, whereas the circuit of the present invention has 1160 transistors. So 1056 pieces, 8
In the case of bits, the conventional circuit requires 3872 bits, whereas the circuit of the present invention requires 1728 bits. The difference between the two increases as the number of bits handled by the serial-to-parallel conversion circuit increases, and in the case of 16 bits, compared to 15296 in the conventional circuit,
It can be seen that the circuit of the present invention requires only 5504 circuits, and the circuit of the present invention can achieve the same function with a smaller circuit scale. In addition to having a small circuit scale, as can be seen by comparing Figures 1 and 3, the circuit of the present invention does not have the complicated wiring to the selector that exists in conventional circuits. It can be said that the configuration is easy to convert into LSI.

On the other hand, regarding the control signal, in the conventional circuit, if the control signal for the selector is 4 bits, two signals are required, but the circuit of the present invention can be said to be advantageous because it only requires one signal for direction switching. Also,
The control signal generation circuit is the same in both the conventional circuit and the circuit of the present invention.

The above has described the case of creating an LSI using CMOS, but the features of the circuit of the present invention are nE/
There is no difference even if you use other devices such as DMOS, or if you create a circuit at the board level using SSI or MSI.

〔Effect of the invention〕

As explained above, the serial-to-parallel conversion circuit of the present invention has a small circuit scale and is easy to wire, so it is suitable for creating LSIs with low power consumption and high yield. It can greatly contribute to performance and economy.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional serial-to-parallel conversion circuit;
1 is a timing diagram for explaining the operation of FIG. 1, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a diagram of the principle of operation of FIG. 3. 1, 2...D type flip-flop, 4-7
...Signal input terminal, 8-11...Signal output terminal,
12...Switch, 13...Selector, 14...
Three-value output buffer.

Claims (1)

[Claims] 1. Has n input terminals and n output terminals,
Either the signals input in series to the n input terminals are converted into parallel signals and output from the n output terminals, or the signals input in parallel to the n input terminals are converted into serial signals. In the serial-to-parallel conversion circuit that outputs data from the n output terminals respectively, n rows and n
A register group consisting of columns is provided, and one unit circuit of the register group has one selector with two inputs and one output that selects data in one of the row and column directions in the previous stage, and latches the data from the selector. It consists of one flip-flop that transfers the input signal to the row and column directions of the subsequent stage, and after transferring the input signal n times in the row direction through the register group, it outputs it n times in the column direction, and the input signal is transferred n times in the column direction. Serial-to-parallel conversion characterized by converting a serial input signal into a parallel output signal, or a parallel input signal into a serial output signal, by alternately repeating the operation of transferring in the direction and then outputting in the row direction n times. circuit.