JPS60221826A - Shifting circuit - Google Patents

Abstract

PURPOSE:To decrease the number of shifting circuits, and to shorten the shifting time by adding a register, masking circuit and a mask pattern generating circuit to the shifting circuit. CONSTITUTION:The first and the second data from a bus 16 are inputted to a shift register 1 of a shifting circuit, and a data from the register 1 is inputted to an AND circuit 7 of a masking circuit 31. Also, a mask pattern from the bus 16 is stored in a register 4 of a pattern generating circuit 30, a value of each bit is inverted by an inverting circuit 5, added to a selector 6 together with the output of the register 4, and an inverted output from the register 4 and the circuit 5 is selected by the selector 6. AND of an output of this selector 6 and an output of the register 1 is derived by the circuit 7, and outputted from the circuit 31. This output data is processed by a register 8 and an OR circuit 9, and OR of the circuits 7, 8 is derived by the circuit 9, this output is outputted to the bus 16 through a register 3, this operation is applied to all bits, and the number of the shifting circuits is decreased.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a graphical data processing device, etc.
The present invention relates to a device for efficiently shifting data with a long bit length.

[Prior art]

FIG. 1 is a block diagram showing a conventional shift circuit. In FIG. 10 is a bus that sends data to be stored in shift register 1, 11 is a bus that sends data to be stored in shift register 1, and 11 is a register that stores output data of shift register 1.
12 is a bus for inputting the output of the shift register 2 to the register 3, and 13 is a bus for outputting the data of the register 8.

Next, the operation will be explained.

In Fig. 2, the time indicating the timing of the operation is also = 1, t
=2. . . . and shows the data stored in each shift register and register at each timing.

First, at timing j=l, first input data Al and A2 are stored in the shift register 1, and the sheet register 2 is reset. Next, after repeating left shifts between shift registers 1 and 2, using shift-out data of 1 as shift-in data of 2, data A1 is transferred to shift register 2 and data A2 is transferred to shift register 2 at timing t==2. are respectively stored in shift register 1.

By storing the data in shift register 2 in register 3 at timing t==3, the data input to shift register 1 is shifted to the left by the required number of bits.
The output data of is obtained in register 8.

Next, data A1 and A2 are obtained in the shift register 2 at timing t=4 by performing a shift K in the same manner as when data was obtained at timing t=2.

The second input data Bl and B2 are input to the shift register HC at timing l=5, and then shifted in the same way as when data was obtained at timing i=2, and data A2 is input to shift register 2 at timing i=2. and get B1.

At timing l=7, the data in shift register 2 is stored in register 3 to obtain output data of %1M2.

By repeating these operations, output data in a format in which input data with a long bit width is shifted by the necessary number of bits as shown in Figure 3 is converted into the first output data -9.
The second output data can be obtained sequentially in the form of partial data such as...

Since the conventional shift circuit is configured as described above, 1
If the bit length of partial data is n, it requires four shifts to obtain one partial data, and there is a drawback that shifting requires a lot of busy time.

[Summary of the invention]

The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional circuit, and an object of the present invention is to provide a shift circuit that can obtain the above-mentioned output data with a small number of shifts.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 4, shift register 1. register 3, bus 1
0. ．． Reference numeral 13 indicates the same or similar part to that in FIG. 1; 4 is a register that stores a mask pattern; 5 is an inversion circuit that outputs data obtained by inverting the value of each bit of the data in register 4; and 6 is a selector that selects data from one of register 4 and inversion circuit 5, and 7 is a selector that outputs the AND of the data from shift register 1 and the data from selector 6.
ND circuit; 8 is a register that has the function of clearing data and stores the output data of AND circuit 7; 9 is an OR circuit that outputs the logical sum of the output data of AND circuit 7 and the data of register 8; 14 is a shift register A bus 15 inputs the shift-out data of the shift register 14 as shift-in data of the shift register 14.
16 is a bus that inputs data to register 4; 17 is a bus that inputs data from register 4 to inverting circuit 5 and selector 6; 18 is a bus that inputs the output of inverting circuit 5 to selector 6. , 19 indicates the output of selector 6 as A
20 is a bus that inputs the output of AND circuit 7 to register 8 and OR circuit 9, 21 is a bus that inputs the data of register 8 to OR circuit 9, 22 is O
A bus inputs the output of the R circuit to the register 3, 30 is a pattern generation circuit, and 31 is a mask circuit.

Next, the operation will be explained.

The time indicating the timing of the operation is t=1, t=2°...
..., and the data stored in shift register 1, register 3, 4.81C at each timing is
As shown in the figure. Of these, the data stored in the register 4 is unchanged, and 1s are stored from the right end by the number of bits to be shifted in advance, and 0s are stored in the remaining bits.

First, at timing j=l, the above data is stored in register 4.
Then, register 1 receives first input data AI.

Person 2 is stored and register 8 is cleared.

Next, the data in shift register 1 is rotated and shifted by the required number of bits, and data A1 comes to the right of data A2 at timing 1=2. At the same time, the selector 6 selects the data in the register 4, this data is input to the AND circuit 7 together with the data in the shift register 1, and the logical product of the two is output.

Here, since the part of the output data of the selector 6 corresponding to the data A2 of the shift register 1 is 0, the AND circuit 1
The output data is the data of shift register 1 and is data A2.
0 is stored in the part.

This data is input to the OR circuit, but register 8 is 0.
Therefore, at this time, the output of the OR circuit 9, which is the logical sum of the AND circuit 7 and the register 8, is equal to the output of the AND circuit 7.

At timing t==3, the output of the OR circuit 9 is stored in the register 3 to obtain first output data.

Next, selector 6 selects the output of inverting circuit 5 and transfers it to bus 1.
9 is input to the AND circuit 7, and the logical sum of this data and the data of the shift register 1 is output. Since the output of the inversion circuit 5 is the inversion of the values 0 and 1 in each bit of the register 4, the output of the AND circuit 7 is the result of storing 0 in the data A1 portion of the shift register 1. ing.

In this way, the AND circuit 70 output data is stored in the register 8 at timing t=4.

Next, at timing t==5, the second input data Bl, B, and 2 are input to shift register 1, and are rotated and shifted by the required number of bits, and at timing t=6, data B1 comes to the right of data B2. .

At the same time, selector 6 selects the data in register 4 and A
Input to ND circuit 7, register 4 and shift register 1
The logical product of is output. This results in 0 being stored in the data B2 portion of shift register 1.

The output data of the AND circuit 7 is input to the OR circuit 9 via the bus 20, and the OR circuit with the data of the register 8 is output. This data is the result of combining B1 to the right of A2.

At timing i=7, the output data of the OR circuit 9 is stored in the register 8 to obtain second output data.

Thereafter, by repeating the same operation, output data in a format in which the input data with a long bit width is shifted by the necessary number of bits as shown in Fig. 3 is converted into the first output data,
The second output data can be obtained sequentially in the form of partial data such as...

Note that in the above embodiment, the pattern generation circuit is provided with a register and the mask pattern is input from the outside, but this register is first reset as a shift register with a reset function, and 1 is input as shift-in data. The shift register may be configured to perform a similar shift operation at the time of the first shift operation of a shift register storing input data.

Further, when shifting the shift register, if the shift register is constructed so that it can be shifted in the direction with fewer shifts between left and right, the same function can be expected with fewer shifts.

〔Effect of the invention〕

As described above, according to the present invention, by adding a register, a mask circuit, and a mask pattern generation circuit, there is an effect that the number of shifts can be slightly reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional shift circuit, Fig. 2 is a timing chart for explaining its operation, Fig. 3 is an explanatory diagram of the data format, and Fig. 4 is a shift circuit according to an embodiment of the invention. FIG. 5 is a timing chart for explaining its operation. In the figures, 1...shift register, 8...register, 9...OR circuit, 30...no (turn generation circuit), 81...mask circuit. Note that the same reference numerals are used in each figure. shall indicate the same or equivalent parts. Patent Applicant Mitsubishi Electric Corporation 59.9.21 Showa 1999 (Monday/Monday) Commissioner of the Japan Patent Office 1. Indication of the case: Japanese Patent Application No. 59-76537 2. Invention name shift circuit 3. To Hitoshi Katayama, representative of the person making the amendment. 6. The statement of contents of the amendment shall be amended as follows.

Claims (1)

[Claims] In a shift circuit for converting a data string consisting of successive data groups having the same number of bits into a data string consisting of a new data group in which data is sequentially shifted by a predetermined bit between each data group, the above-mentioned data A shift register that stores groups sequentially and performs rotational shifts;
A pattern generation circuit that generates a mask pattern corresponding to the number of bits to be shifted in the data group, a mask circuit that receives the shift register data and the mask pattern as left inputs, and stores the output of this mask circuit. 1. A shift circuit comprising: a register, and configured to obtain a data string consisting of a data group having the above characteristics by ORing the output data of the register and the output data of the mask circuit.