JPS60140430A - Multiplier circuit - Google Patents

Abstract

PURPOSE:To speed up the operation while decreasing the gate number of a carry storing adder (CSA) tree by applying the loop back to the last CSA tree in a multiplier of the CSA tree system in a form of a G/P term. CONSTITUTION:The multiplier 1 of CSA trees 12, 13 connecting a CSA in a tree form inputs a sum (S) and a carry (C) of each bit being an intermediate output to a carry propagation adder (CPA)2, where the final output is obtained. In this case, the G/P unit generating a carry generating function (G) and a carry propagating function (P) from each bit of the inputs S, C is formed to an LSI at the multiplier 1, the output of registers 14, 15 is driven directly, the loop back to the CSA tree 13 is applied not with the S and C but with the G and P, then the gate number of the CSA tree is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a multiplication circuit using C3A L-Lee.
In particular, by looping back to the final stage C3A) in the form of a GZP term, the number of gates in the C5A) is reduced.

Prior art and problems Carry 5ave Adder
In a multiplier that uses C3A) Lee which connects CS
Product) as the sum of each pitch (SUM:
S) and carry (CARRY:C) are obtained. These S and C form a carry propagation adder.
e Adder: Input to CP A), where addition processing is performed and final output (FinalProduct)
, but also to the C8A tree which produced an intermediate output. : Loop back C.

An example is shown in FIG. In the figure, ■ is a multiplier (
Multtpeier), 2 is a carry propagation adder (C
PA). Although these are separate LSis, the multiplier 1 is often divided into multiple chips in bit units. Multiplier 1 is connected to a recorder (Re
coder ) 10 and the multiplicand CAND from its output
(Multiple game)
Gate) 11, the C8A tree 12 at the first stage and the C3A tree 13 at the final stage, registers 14 and 15 for latching the sum S and carry C for each focus obtained from the C8A tree 13, It is equipped with an output gate 16°17 corresponding to each bit,
Then, the above S and C are looped back (LOOP BACK) through output gates 1 to 16.17.

On the other hand, CPA2 generates a carry generation function (Generate: G) and a carry propagation function (P
ropagate: P) and a carry look-ahead logic (Carry Look-Ahead) that generates the final output from the generated G/P term.
Logic: CLA) 21, r\-Fusamurosic (H
alf-5umLogic: HS) 22, Full-3umLogic (FS)
23.

The G/P unit 20 is an AND gate 20 as shown in FIG.
1 and an or gate 202, Gi=Ai-Bi
・・・・・・(1) Pi=Ai+Bi ・・・・・・(
2) Generate outputs Gi and Pi corresponding to the bits (i is the bit number). The inputs Ai and Bi are 3 i and C1+t from the C8A tree 13.

By the way, in C3A) Lee, tree 12 narrows down the power of nine people to four outputs, and tree 13 narrows down the 4 bits and the loop-banked 2 pins, a total of 6 bits, to 2 bits S and C. Then, the final stage output of this C3A) Lee is subjected to addition processing by the CPA to obtain the final product. If loopback in this operation is performed in the form of S, C, C3A) Lee-1
3 becomes complicated. Further, if the driving ability of the registers 14 and 15 is insufficient to drive the G/P unit 20 of the other LSi2, there is a drawback that the output gates 16 and 17 are also required to correspond to bits.

Object of the Invention The present invention focuses on the fact that the above-mentioned G/P term includes S and C components, and attempts to solve the above-mentioned drawbacks by applying a C3A) Rieher loop bath to this.

Structure of the Invention The present invention uses a C8A tree to calculate a sum S and a carry C for each bit, and further uses a P/G unit to calculate a carry generation function G and carry propagation from the sum S and carry C. In a multiplication circuit that generates a function P and calculates the final product using these, the carry generation function G and the carry propagation function P are looped back to the final stage of C3A) Lee. However, this will be explained in detail below with reference to the illustrated embodiment.

Embodiment of the Invention FIG. 3 is a schematic diagram showing an embodiment of the invention, in which the same parts as in FIG. 1 are given the same reference numerals. This example differs from FIG. 1 in two ways. The first is C3A) Loopback to Lee 13 (LOOP BA(J) to S, not C,
This is the point that I made G and P. The second point is that the G/P unit 20 is formed in the LSi on the side of the multiplier 1 and is directly driven by the output of the registers 14 and 15. In this case, G/P
Unit 20 is CLA21 of another LSi2. It would be easy to directly drive the H822, and thus the output gates 16 and 17 in FIG. 1 could be omitted. This is not necessarily common, but by design register 1
This is useful when the driving capacity of the 4.15 cannot be increased.

Next, the gate saving effect due to the loopback of the G and P terms will be explained. Figure 4 shows a typical C3A single gate configuration.
There are three types of inputs: α, β, and T, and two types of outputs: C2S. The + and - symbols attached to each symbol indicate whether the same signal is used with its level inverted (-) or used as it is not inverted (+). The logic to be obtained is shown in the table below, and is associated with the gate numbers ■ to ■ in FIG.

Table 1 This 8-gate C3A is not shown in Figure 6. C3A tree 12
．． Used in most of the 13 cases. 8 with one white circle
Gate C3A30 is shown. In C3A tree 12, this 8
The gates C3A30 are combined in a tree shape, with three gates in the upper row and two gates in the lower row, to generate 2X2'=4 outputs from 3X3=9 human power from the multiplier gate MG. CC is an output indicating the next carry.

On the other hand, the 8-gate C3A 30 is also used in the C3A tree 13, but the 6-gate csA4o shown with diagonal lines is used for the C3A in which P and G are loop banked. Figure 5 is a gate development diagram of this 6-gate CS A4.0, where the inputs are α,
Three types: c, p (+, - as mentioned above), output is C1S
There are two types. Table 2 is the logic table for C3A40 (6 games), and gate table 2. As shown in Figure 2 and 2 (11, f21), not only G and P include C2S components, but also G is AND logic, Since P is OR logic, when G=1, the power of two people is both 1, so P=1.

Therefore, in Table 1, when β-G and r=P, the cases of gate number ■■ are combined into the case of gate number ■. This corresponds to the case of gate number ■ in Table 2, and is written as × to mean that the input P does not need to be handled.

This saves one gate of C3A, but the same thing applies to the case ■■ in Table 1, so
In Table 2, this is summarized in case ■, saving a total of two gates. Even if this is done, the types of combinations of output C1S in Table 2 remain the same as in Table 1. For reference, the correspondence with Table 2 is shown outside the margin of Table 1.

As is clear from FIG. 6, in the configuration of C3A) Lee-13, there are many 8-gate C3A30, and 6-gate CS A4
．． 0 is used only once per 1 bit. but,
When the total number is 56 to 80 bits, the gate saving effect due to the 6 gate C3A40 is multiplied by 56 to 80 times, resulting in a total saving of 112 to 160 gates. SUN in Figure 6 is the sum as the final output of C8A tree 13,
Also, CARRY is used to indicate a carry,
This corresponds to S and C in FIG.

If the multiplier iER in Figure 3 is 2 bytes, C3A tree 1
Loopback to 3 also takes 2 bytes.

The C3A l to Lee-12 in the upper row reduce the 9 manpower per bit to 4 outputs in the C3A group shown in Figure 6, and the C3A in the lower row
I-Lee-13 performs an operation to narrow down the six-man power, which is the four outputs plus the two-man power P and G of the loop bank, to two outputs S and C. The final output is obtained by calculating these two outputs S and C, but this is done after converting the two outputs S and C into a G/P term using a G/P Uniso I.20 in the high-speed adder. A concrete example uses the logic of CI and A21, and at the same time, F with HS 22 stopped.
Operate S23 to obtain the final output. During this time C3A
Loop banking to tree 13 is performed in parallel.

Effects of the Invention As described above, according to the present invention, the loopback to the final C3A) is performed using the csA three-way multiplier.
Since this is done in the form of terms, the number of gates of the csA1-Lee can be reduced. There is also a register that holds the output of the C3A I-Lee and a G/P that generates the 072 term.
If an LSi configuration is adopted in which no output gate is interposed between the unit and the unit, the gate saving effect will be increased accordingly, and furthermore, the delay of the output gate will be eliminated, thereby increasing the speed of operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional C3A) type multiplier, FIG. 2 is a detailed diagram of its G/P unit, FIG. 3 is a schematic block diagram showing an embodiment of the present invention, and FIG. The figure is a block diagram of a general 8-game 1-C3A, Figure 5 is a block diagram of a 6-game C3A according to the present invention, and Figure 6 is a block diagram of the C3A of Figure 3.
) is a detailed view of Lee. In the figure, 1 is a multiplier, 2 is a carry propagation adder, 12.13
20 is a G/P unit, 30 is an 8-gate C3A, and 40 is a 6-gate C3A. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi Figure 1 Figure 3

Claims (1)

[Claims] C3A Sum S and carry C for each bit using L-Lee
Furthermore, a P/G unit is used to generate a carry generation function G and a carry propagation function P from the sum S and carry C, and these are used to calculate the final product in a multiplication circuit. A multiplication circuit characterized in that a generation function G and a carry propagation function P are heave-backed at the final stage of C3AI-Lee.