JPS60110038A - Digital arithmetic device - Google Patents

Abstract

PURPOSE:To increase the number of data combinations to be supplied to an arithmetic circuit by using one of two pairs of unidirectional shift registers serving as data input parts as bidirectional shift registers. CONSTITUTION:A shift register 101 consists of two delay circuits 1, and the input of a delay circuit of the preceding stage is received from an input signal A. While the output of said delay circuit is supplied to a delay circuit of the next stage as well as to an arithmetic circuit 2 or the preceding stage. While the input of the circuit 1 is supplied only to the arithmetic circuit 2 of the next stage. A shift register 102 consists of two delay circuits 1 and two selection circuits 4. The input of the circuit 4 of the preceding stage is received from an input signal B and the output of the circuit 1 of the next stage and used as the input of the circuit 1 of the preceding stage. The output of the circuit 2 is supplied to an arithmetic circuit 3, and the output of the circuit 3 is turned into an output signal 21 and delivered to the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the configuration of a digital arithmetic circuit that performs digital arithmetic operations.

[Background of the invention]

The circuit configuration of the digital arithmetic device shown in FIG. 1 is used as a part of an image processing processor.

The digital arithmetic device shown in FIG. 1 consists of eight delay circuits 1, four two-manpower arithmetic circuits 2, and one concave input arithmetic circuit 3, and each delay circuit 1 receives one synchronizing signal. 13
are synchronized. Conventionally, the arithmetic circuit shown in Fig. 1 processes 2x2 pixel data sent by the rask scan image input method shown in Fig. 2, in which main scanning scans from left to right and sub-scanning scans from top to bottom. When trying to realize a nonlinear neighborhood operation, connect the two sets of ↓ calculation devices shown in Fig. 1, one delay circuit 5 for the image keytar row, and two delay circuits 1 as shown in Fig. 2. Each delay circuit is connected to one synchronous signal signal 1.
3, and the arithmetic circuit in the arithmetic device must also be set as shown. In order to perform nonlinear neighborhood calculations on image data sent by rask scanning in this manner, there is a drawback that two sets of calculation devices must be used.

In the figure, 11 and 12 are input signals, and 21 is an output signal.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an arithmetic device that can perform operations that have not been possible with conventional digital arithmetic devices.

[Summary of the invention]

The present invention is to increase the number of combinations of data input to the arithmetic circuit by making one of the two sets of unidirectional shift registers serving as the data input section a bidirectional shift register.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows a unidirectional input, two-stage shift register 101.
The configuration of a digital arithmetic device using one bidirectional, one two-stage shift register 102, two arithmetic circuits 2, and one another arithmetic circuit 3 is shown. Shift register 101
consists of two delay circuits 1, the input of the previous stage delay circuit 1 is received from the input signal A, and the output is input to the next stage delay circuit 1 and the previous stage arithmetic circuit 2. . In addition, the input of the delay circuit 1 in the subsequent stage is inputted only to the arithmetic circuit 2 in the subsequent stage.The 6 shift register +02 consists of two delay circuits 1 and two selection circuits 4, and The input of the selection circuit 4 is the input signal B and the subsequent delay circuit 1.
The output is received from the output of the delay circuit 1 in the previous stage. The output of the delay circuit 1 at the front stage is input to the arithmetic circuit 2 at the front stage and the selection circuit 4 at the rear stage. The selection circuit 4 at the rear stage receives input from the input signal B in addition to the serial circuit 1 at the front stage, and its output is input to the delay circuit at the rear stage. The output of the delay circuit 1' at the rear stage is input to the arithmetic circuit 2 at the rear stage, and also to the selection circuit 4 at the front stage. Each delay circuit 1 is synchronized by one synchronization signal 13.

Further, each selection circuit 4 is selected by one selection signal 14. Each output of the arithmetic circuit 2 is input to the arithmetic circuit 3, and the output of the arithmetic circuit 3 becomes an output signal 21 and is output to the outside. 4 and 5 show the flow of signals and the results of calculations when performing calculations by the calculation device shown in FIG. 3. Input signal A in Figure 3
, C data is input to the first clock, b data is input to the second clock, and C data is input to the input signal B to the first clock, and d data is input to the second clock.

In FIG. 4, the two sets of i-shift register columns into which data is input are always in the forward direction with respect to input signal A, and are also in the forward direction with respect to input signal B by selection signal 14. selected. When both shift register rows are in the forward direction, the signal flow is as shown by the diagonal lines in the circuit in Figure 4, and the combination of signals input to the arithmetic circuit 2 at this time is as shown in Figure 4(b). As shown in the figure, the signals are input with the same clock. On the other hand, in the calculation method shown in FIG.
The reverse direction of the register column is selected by the selection signal 11. In this case, the flow of the input signal is such that the data input to the input signal A is shifted from the front stage to the rear stage of the shift register, while the input signal The data input to B will be shifted from the latter stage of the shift 1 register to the previous stage. At this time, the combination of signals input to the arithmetic circuit 2 crosses the input signal directions, as shown in FIG. 5(b). In other words, by changing the selection signal 14 in the circuit shown in FIG. 3, two different signals as shown in the examples of FIGS. It becomes possible to perform calculations. In conventional arithmetic units, both of the shift register arrays in the input section were forward-oriented only, so as shown in Figure 5, operations in which the operations cross-multiply the inputs (such as nonlinear neighborhood operations) are not possible. For this, two computing devices had to be used as shown in FIG. However, by using the above-mentioned circuit system, it becomes possible to perform cross-over calculations in a combination of arithmetic units as shown in FIG.

Next, we incorporated this circuit system into a conventional arithmetic unit to realize 2×2 nonlinear neighborhood operations (crossover is an operation) for image input using a single arithmetic unit, as shown in Figure 2. An embodiment will be described with reference to the drawings. FIG. 6 shows one of the unidirectional shift registers of the conventional device of FIG. 1 changed to bidirectional. A selection circuit 4 is provided at the input part of the delay circuit of a conventional shift register, and is controlled by a 1 selection signal 1°4. The basic operation is the same as that of the circuit shown in FIG. 3; the delay circuit 1 of the shift register in FIG. 3 has two stages, whereas the delay circuit 1 in FIG. 6 has four stages. With this circuit system, the data input from the input signal B is transferred to the selection signal 14.
By switching, two types of shift registers are possible: one is to shift the shift register from the previous stage to the next stage, and the other is to shift the shift register from the latter stage to the previous stage. FIG. 7 shows an example of actually performing nonlinear, shape neighborhood calculations on 2×2 image data using the calculation device shown in FIG. The shift register of port A, which inputs image data, is selected in the forward direction, and the shift register of port B is selected in the reverse direction, and the arithmetic circuit 2 performs an operation that takes the absolute value of subtraction, and only the outputs of the two central arithmetic circuits 2 are operated. It is assumed that the signal is sent to circuit 3, and arithmetic circuit 3 performs an addition operation. Further, numeral 5 in the drawing is a delay circuit for the image data, - row, and all the delay circuits are synchronized by a synchronization signal 13. When performing calculations with these settings, the combination of image data input to the second and third stage delay circuits of the upper and lower shift registers, 7 in total, is as shown in Figure 5. Examples and,
The pattern will be exactly the same. In other words, with this circuit configuration, the cross-multiplication operation can be performed with a single arithmetic circuit, as shown in FIG. Then, as shown in FIG. 7, for the input signal at by Ct d, nonlinear neighborhood calculation 1 a-d 1+1 b-c 1
This can be realized with an arithmetic circuit.

FIG. 8 is an example in which the shift register section of the circuit configuration of FIG. 6 is logicalized using a clocked inverter.

In the drawing, 201 is a delay circuit block of a unidirectional shift register, and 202 is a bidirectional shift register block with a selection circuit.
This is a register delay circuit block. Each delay circuit is synchronized by two synchronizing signals 13, and the two synchronizing signals must be set so that they do not become high potentials at the same time. Further, the selection signal 14 selects the forward direction of the bidirectional shift register when the potential is high, and selects the reverse direction when the potential is low.

Figure 8 shows a 4-bit circuit configuration, 201, 202
The number of bits can be increased by adding blocks of .

〔Effect of the invention〕

According to the present invention, it becomes possible to perform calculations that could not be performed with a single set of calculation devices in the past.

[Brief Description of the Drawings] Fig. 1 is a block diagram of a conventional arithmetic unit used in an image processing processor, Fig. 2 is a block diagram of nonlinear neighborhood calculation using the arithmetic unit shown in Fig. 1, and Fig. 3 is a block diagram of a conventional arithmetic unit used in an image processing processor. is a block diagram of an arithmetic device having a bidirectional shift register in the input section according to an embodiment of the present invention, FIGS. 4 and 5 are flowcharts when the arithmetic device of FIG. A block diagram of the arithmetic device of the invention, FIG. 7 is a block diagram of nonlinear neighborhood calculation using the arithmetic device of FIG. 6, and FIG. 8 is a block diagram of the shift register section of the arithmetic device of FIG. 6 using a clocked inverter. It is a logical block diagram. DESCRIPTION OF SYMBOLS 1... Delay circuit, 2, 3... Arithmetic circuit, 4... Selection circuit, 5... Delay circuit for one line of image input, 101.
. . . Unidirectional shift 1 register, 102 . . . Bidirectional shift register. ■ 2 Example'￥J 3 Figure 4 Revised figure) Output signal (μ × 8 tread × % Beka % 5 Figure (Inoshi W calculation circuit 2. Continuation of input 1st page 0 Inventor Saka Tadashi Higashi Inside the 3-chome Saiwaimachi, Hitachi City0 Inventors Masaharu Takasawa Inside the 3-chome Saiwaimachi, Hitachi City

Claims (1)

[Claims] (2) A plurality of sets of shift registers each consisting of a plurality of series-connected delay circuits with a single data shift direction, and the output of the delay circuit of each of the shift registers as input;
In a digital arithmetic device comprising a plurality of arithmetic circuits that perform simultaneous parallel processing and another arithmetic circuit that integrates the outputs of these arithmetic circuits, at least one of the shift registers
A digital arithmetic device characterized in that data is shifted in both directions for sets.