JPH04208553A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a leak current by accumulating the first conductive film, which is thinner than the radius of the contact hole opened in an interlayer insulating film, and accumulating as second film all over the surface, and etching back it, and then accumulating the third conductive film all over the surface, and patterning the third conductive film and first conductive film at the same time. CONSTITUTION:A gate oxide film 2, a gate electrode 3, and an n-type diffusion layer 4 are made on a p-type substrate 1, and next an interlayer insulating film 5 is accumulated, and a contact hole 6 is opened. By accumulating nondoped polysilicon 8 all over the surface, after accumulating polysilicon doped with phosphorus all over the surface, and etching back it, the polysilicon 7 is exposed, whereby it gets in the condition that the polysilicon is filled up in the contact hole 6. Next, by thermal diffusion, the polysilicon 8 is doped with phosphorus, and aluminum 9 is accumulated all over the surface, and then the aluminum 9 and the polysilicon 7 are patterned to form wiring consisting of aluminum 9. Hereby, the diffusion layer 4 of the contact hole 16 is etched, where the element can be gotten at high yield rate without occurrence of leak currents.

Description

[Detailed description of the invention]

[00011

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a contact for wiring. [0002] In semiconductor integrated circuits and the like, aluminum wiring has been formed directly after contacts are opened in an interlayer insulating film. [0003] As integration becomes higher, the aspect ratio of contacts becomes larger due to smaller contact sizes and more complex cross-sectional structures. Breaking of the aluminum wiring on the side of the contact opening has become a problem. [0004] As a countermeasure to this problem, polysilicon is buried in the contact to flatten the area around the contact to prevent the wiring from breaking. [0005] An example thereof will be described with reference to FIGS. 12 to 14. [0006] First, as shown in FIG.
A gate oxide film 2 is formed by thermal oxidation, and a gate electrode 3 made of polysilicon is formed. [0007]Next, by performing ion implantation using the gate electrode 3 as a mask, an N-type diffusion layer 4 serving as a source-drain is formed, an interlayer insulating film 5 is deposited, and a contact having a diameter IILm is opened. [0008] Next, phosphorus-doped polysilicon 7 is deposited by CVD to a thickness of 1 μm, which is thicker than the radius of the contact. [0009] Next, as shown in FIG. 13, the phosphorus-doped polysilicon 7 is etched back by RIE using chlorine gas plasma to expose the surface of the interlayer insulating film 5 and leave the polysilicon 7 in the contact. The etching rate at this time is approximately 1008/min, but if phosphorus-doped polysilicon 7 remains on the surface of the interlayer insulating film, it will cause a wiring short, so taking into account variations in film thickness and etching rate, the etching rate should be reduced by 20%. Some degree of over-etching is required. [00101 Next, aluminum 9 is deposited on the entire surface. [00111 Next, as shown in FIG. 14, the element portion is completed by patterning the aluminum 9. [0012]

[Problems to be Solved by the Invention] In the prior art, the product yield was greatly affected by etchback control. [0013] In the process of etching back phosphorus-doped polysilicon, when a part of the interlayer insulating film begins to be exposed, a loading effect occurs in which the surface area of the phosphorus-doped polysilicon rapidly decreases and the etching rate accelerates several times. arise. [0014] The loading effect causes excessive etching of the phosphorus-doped polysilicon in the contact opening. [0015] In the worst case, as shown in FIG. 15, a part of the contact opening is exposed from where the phosphorus-doped polysilicon 7 becomes thin, forming an etching damage region 14. When etching reaches the substrate, leakage current increases due to surface damage caused by plasma irradiation, resulting in product defects. [0016] Due to the limitations of polysilicon residue due to insufficient etching and damage to the substrate surface due to excessive etching, there has been a problem in that the yield is influenced by delicate controllability of etchback. [0017]

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes the steps of forming an insulating film on a semiconductor substrate, opening a contact in a predetermined region of the insulating film, and opening the contact hole in the entire surface. a step of depositing a first conductive film thinner than a radius of , a step of depositing a second film over the entire surface, and an etching rate of the second film is higher than an etching rate of the first conductive film. etching back to leave at least a portion of the second film within the contact and leaving at least a portion of the first conductive film on the insulating film; and forming a third conductive film on the entire surface; and a step of patterning the third conductive film and the first conductive film at the same time. [0018]

[Example] Regarding the first example of the present invention, FIGS. 1 to 5
Explain with reference to. [0019] Finally, as shown in FIG. 1, a gate oxide film 2, a gate electrode 3, and an N-type diffusion layer 4 are formed on a P-type substrate 1. [00201 Next, an interlayer insulating film 5 is deposited with a diameter of 1 μm.
The contact hole 6 is opened. [00211] Next, as shown in FIG. 2, phosphorus-doped polysilicon 7 is deposited on the entire surface to a thickness of 2000 nm, and then undoped polysilicon 8 is deposited on the entire surface to a thickness of 6000 nm. [0022] Next, as shown in FIG. 3, by etching back using CBrF3 gas plasma, the phosphorus-doped polysilicon 7 on the upper surface of the interlayer insulating film 5 is exposed, and the contact hole 6 is filled with non-doped polysilicon 8. It will be in a depressed state. [0023] At this time, conditions can be selected in which the etching rate of non-doped polysilicon 8 is faster than the etching rate of phosphorus-doped polysilicon 7, depending on the type and pressure of the gas. Even if the upper layer non-doped polysilicon 8 is over-etched, the lower layer phosphorus-doped polysilicon 7 acts as a stopper and can prevent the substrate 1 from being etched. [0024] Furthermore, since the phosphorus-doped polysilicon 7 is present on the entire surface, there is no fear of excessive etching due to the loading effect. [0025] Next, as shown in FIG. 4, the non-doped polysilicon 8 is doped with phosphorus by thermal diffusion, and aluminum 9 is deposited on the entire surface. [0026] Next, as shown in FIG. 5, aluminum 9 and phosphorus-doped polysilicon 7 are patterned using a photoresist (not shown) as a mask to form wiring made of aluminum 9 and complete the element section. . [00271 In this embodiment, the lower layer phosphorus-doped polysilicon 7 acts as an etching stopper for the upper layer non-doped polysilicon 8, so even if the etching time is somewhat longer, leakage due to etching of the diffusion layer 4 of the contact hole 6 is prevented. It has become possible to manufacture devices with high yield without the generation of current. [0028] Next, a second embodiment of the present invention will be described with reference to FIGS. 6 to 11. [0029] First, as shown in FIG.
An N-well 10, a field oxide film 11, a gate oxide film 2, a gate electrode 3, an N-type diffusion layer 4, a P-type diffusion layer 12, an interlayer insulating film 5, and a contact hole 6 with a diameter of 1 μm are formed. [00301 Next, as shown in FIG.
silicide 15 is deposited, and then non-doped polysilicon 8 is deposited to a thickness of 6,000 yen. [00311] Next, as shown in FIG. 8, the non-doped polysilicon 8 is etched back to expose the silicide 15 on the surface of the interlayer insulating film 5, leaving the non-doped polysilicon 8 in the contact hole 6. [0032] Next, after masking the contact hole 6 on the N-type diffusion layer 4 with a resist 13, boron ions are selectively implanted into the non-doped polysilicon 8. [0033] Next, as shown in FIG. 9, the resist 13 is newly patterned after the resist is removed.
After masking the contact hole 6 on the P-type diffusion layer 12, phosphorus ions are selectively implanted into the non-doped polysilicon 8. [0034] Next, as shown in FIG.
After removing, aluminum 9 is deposited on the entire surface. [00351] Next, as shown in FIG. 11, the aluminum 9 and silicide 15 are buttoned to form wiring, thereby completing the element section of the CMO8-IC. [00361 In this example, by using silicide, which has a masking function against phosphorus diffusion, as the first conductive film,
Phosphorus-doped polysilicon can also be used as the second conductive film 8 for the CJiO5-IC. Without phosphorus diffusing from the phosphorus-doped polysilicon 8 to the P-type diffusion layer 12,
A good ohmic contact can be formed. [0037] The contact hole is in the source-drain diffusion layer 4
．． As a measure against leakage when it exceeds 12,
This can be dealt with by ion implantation after the conductive film 15 is deposited. The charge-up that occurs when ions are directly implanted into the contact hole 6 formed in the interlayer insulating film 5 is alleviated by the first conductive film 15, which has the effect of preventing discharge breakdown around the contact hole. [0038] Also, submicron size contact hole 6
If the aluminum 9 is deposited thickly, an overhang will occur and a cavity will be created inside the contact hole 6. In the manufacturing method of the present invention, the generation of cavities can be prevented by using an SOG film instead of the second conductive film 8 and performing reflow flattening. In this case, the source-drain diffusion layer 4
．． 12 to the aluminum wiring 9 through the first conductive film 15. [0039]

Effects of the Invention: A first conductive film thinner than the radius of the hole is deposited on the contact 1 opened in the interlayer insulating film, a second thick film is deposited on the entire surface, and the second conductive film is etched at a rate lower than the etching rate of the first conductive film. Etch back under conditions where the etching rate of the film is higher than that of the first conductive film, leaving at least a portion of the second film within the contact, leaving at least a portion of the first conductive film on the insulating film, and forming a third conductive film over the entire surface. The third conductive film and the first conductive film are simultaneously patterned. [00401 Therefore, even if the etchback time becomes longer than the optimum value, the first conductive film serves as an etching stopper. This has the effect of preventing the occurrence of leakage current due to etching damage to the substrate, and making it possible to manufacture devices at a high yield.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in order of steps.

FIG. 2 is a cross-sectional view showing the first embodiment of the present invention in order of steps.

FIG. 3 is a cross-sectional view showing the first embodiment of the present invention in order of steps.

Claims (1)

[Scope of Claims] [Claim 1] A step of forming an insulating film on a semiconductor substrate;
opening a contact in a predetermined region of the insulating film;
a step of depositing a first conductive film thinner than the radius of the contact hole over the entire surface; a step of depositing a second film over the entire surface; and an etching rate of the second film that is lower than the etching rate of the first conductive film. a third conductive film on the entire surface; A method of manufacturing a semiconductor device, comprising a step of depositing the third conductive film and a step of patterning the first conductive film at the same time. [
2. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductive film and the second film are made of polysilicon and have different phosphorus doping concentrations. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the second film is a conductive film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the second film is an insulating film.