KR100268943B1 - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to form gate electrodes for DRAM and logic regions separately to optimize the property of the gate electrode. CONSTITUTION: The method includes following steps. A semiconductor substrate is divided into the DRAM and logic regions. The first gate insulator layer, the first conductive polysilicon layer, a polycide and the first cap gate insulator layer are formed on the DRAM of the semiconductor substrate in series. The second gate insulator layer, an undoped polysilicon layer and the second gate insulator layer are formed on the logic region. n-type impurity is injected to form n-type doped polysilicon layer on the undoped polysilicon layer of the NMOS region. Then, p-type impurity is injected to form p-type doped polysilicon layer on the undoped polysilicon layer of the PMOS region. The first cap gate insulator layer, polycide, the first conductive polysilicon and the first gate insulator layer on the DRAM region and the second cap gate insulator layer, n and p-type doped polysilicon layer and the second gate insulator layer are patterned selectively to form gate electrodes spaced with a predetermined spacing. The first and the second cap gate insulators on the DRAM and the logic regions are removed. A sidewall spacer is formed and a silicide(36) is formed on the upper layer of the gate insulator and the semiconductor substrate.

Description

Manufacturing method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for optimizing the characteristics of each device when configuring a DRAM device and a logic device on one substrate.

In general, an embedded DRAM or a semiconductor device having different operating voltages needs to form oxide films having different thicknesses.

In other words, DRAMs and logic devices are rapidly developing according to the integration of semiconductor devices, and embedded DRAMs, in which DRAMs and logics are combined, are emerging, and this trend is expected to continue in the future. Oxide films of different thicknesses should be formed in areas with different operating voltages such as core and peripheral areas and areas other than I / O areas of logic devices, I / O buffers of logic and DRAM and electrostatic discharge (ESD) areas of logic. . In addition, the DRAM portion does not undergo a salicide (self aligned silicide) process, but the logic portion performs a salicide process.

Hereinafter, a method of manufacturing a conventional semiconductor device will be described with reference to the accompanying drawings.

1A to 1H are cross-sectional views illustrating a manufacturing process of a conventional semiconductor device.

First, as shown in FIG. 1A, first and second gate oxide films 2 and 3 having different thicknesses are formed on the semiconductor substrate 1 defined by the DRAM unit A and the logic unit B. FIG. At this time, the thickness of the first gate oxide film 2 of the DRAM unit A is increased.

As shown in Fig. 1B, an undoped polysilicon layer 4 is formed on the first and second gate oxide films 2 and 3, respectively.

As shown in FIG. 1C, n-type and p-type impurity ions are implanted into the undoped polysilicon layer 4 of the DRAM unit A and the logic unit B. As shown in FIG. In this case, the DRAM unit A is generally implanted with n-type impurity ions to reduce the process cost, and is formed as an n-type polysilicon layer 4a. In the logic unit B, in the NMOS region to maintain device performance, The n-type impurity ions are implanted to form the n-type polysilicon layer 4a, but the p-type impurity ions are implanted into the PMOS region to form the p-type polysilicon layer 4b.

As shown in Fig. 1D, a TiN layer 5, a polyside 6 and a nitride film 7 are sequentially formed on the n and p-type polysilicon layers 4a and 4b.

As shown in FIG. 1E, the photoresist film PR is coated on the nitride film 7, and then the photoresist film PR is patterned so as to remain only in the gate electrode region by defining a gate electrode region by an exposure and development process. Subsequently, the nitride film 7, the polyside 6, the TiN layer 5, the n and p-type polysilicon layers 4a and 4b and the first layer are etched using the patterned photoresist film PR as a mask. And the second gate oxide films 2 and 3 are selectively removed to form n and p-type gate electrodes 8 and 9 in the DRAM unit A and the logic unit B at predetermined intervals. In this case, n-type gate electrodes 8 are formed in the DRAM unit A, and n-type and p-type gate electrodes 8 and 9 are formed in the logic unit B.

As shown in FIG. 1F, the side surfaces of the polyside 6, the TiN layer 5, and the n and p-type gate electrodes 8 and 9 of the DRAM unit A and the logic unit B are oxidized. After forming the side oxide film 10, low concentration impurity ions are implanted to form the LDD region 11 in the semiconductor substrate 1 below the side surfaces of the gate electrodes 8 and 9.

As shown in FIG. 1G, an oxide film is formed on the entire surface of the substrate including the gate electrodes 8 and 9, and then etched back to form the nitride film 7, polyside 6, TiN 5, and gate electrode ( 8) 9 and sidewall spacers 12 are formed on the side surfaces of the first and second gate oxide films 2 and 3. Subsequently, a high concentration of impurity ions are implanted to form a source / drain region 13 in the semiconductor substrate 1 below the side surfaces of the gate electrodes 8 and 9 and the sidewall spacers 12.

As shown in FIG. 1H, an insulating film 14 is formed on the entire surface of the substrate including the gate electrode 8 and the sidewall spacer 12 of the DRAM unit A, and then the semiconductor substrate of the logic unit B is formed. Forming a high melting point metal on 1) and then heat treatment to form the silicide (15).

The conventional method of manufacturing a semiconductor device has the following problems.

First, in the DRAM part, the polysilicon layer for forming the gate electrode is generally formed of a doped polysilicon layer using an in-situ process, but in the case of a conventional semiconductor device, the polysilicon layer is an undoped polysilicon layer. In addition, the doping process should be performed separately, and in the gate electrode forming process, since the TiN layer, which is an unnecessary barrier metal, is formed instead of a polyside formed immediately above the gate electrode, there is a problem in that the characteristics of the DRAM device are deteriorated.

Second, in the logic section, the dual polysilicon / silicide structure is formed of the dual polysilicon / barrier metal / polyside structure, such that it is difficult to provide a highly reliable semiconductor device by degrading the characteristics of the logic section as a whole.

The present invention has been made to solve the problems of the conventional semiconductor device manufacturing method as described above to provide a gate electrode optimized in each part by proceeding each process separately when forming the gate electrode in the DRAM and logic section It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of improving reliability.

1A to 1H are cross-sectional views of a manufacturing process of a conventional semiconductor device.

2A to 2H are cross-sectional views of the manufacturing process of the semiconductor device of the present invention.

<Explanation of symbols for main parts of drawing>

21 semiconductor substrate 22 first gate insulating film

23a, 30a: first conductive gate electrode

24 polyside 25 first cap gate insulating film

26: second gate insulating film 27: undoped polysilicon layer

28: second cap gate insulating film 29a: second conductive gate electrode

31 side oxide film 32 LDD region

33 sidewall spacer 34 source / drain regions

35 insulating film 36 silicide

The method of manufacturing a semiconductor device according to the present invention includes preparing a semiconductor substrate, defining the semiconductor substrate as a DRAM portion and a logic portion, and then forming a first gate insulating film, a first conductive polysilicon layer, and a polyside on the semiconductor substrate of the DRAM portion. And forming a cap gate insulating layer in sequence, forming a second gate insulating layer, an undoped polysilicon layer, and a second cap gate insulating layer on the semiconductor substrate defined by the logic unit. N-type impurity ions are implanted into the undoped polysilicon layer in the NMOS region to form an n-type doped polysilicon layer, and p-type impurity ions are formed in the undoped polysilicon layer in the PMOS region. Implanting to form a p-type doped polysilicon layer, the cap gate insulating layer, the polyside, and the first conductive portion of the DRAM portion Selectively patterning a polysilicon layer and a first gate insulating layer and the second cap gate insulating layer, the n and p-doped polysilicon layer and the second gate insulating layer of the logic unit to form gate electrodes having a predetermined interval, and Removing the first and second cap gate insulating layers of the RAM unit and the logic unit; forming sidewall spacers on side surfaces of the gate electrodes; and forming silicide on an upper surface of the logic unit and the semiconductor substrate; Steps.

Such a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.

2A to 2H are cross-sectional views illustrating a process of manufacturing the semiconductor device of the present invention.

First, as shown in FIG. 2A, the first gate insulating layer 22, the first conductive type first polysilicon layer 23, and the semiconductor substrate 21 defined by the DRAM unit A and the logic unit B are formed. The polyside 24 and the first cap gate insulating layer 25 are sequentially formed. Subsequently, the first cap gate insulating layer 25, the polyside 24, the first conductive type first polysilicon layer 23, and the first gate insulating layer 22 may be selectively disposed to meet the DRAM unit A. Patterning (photolithography process + etching process). In this case, the first conductive first polysilicon layer 23 is formed of a polysilicon layer doped with n-type impurity ions.

As shown in FIG. 2B, a second gate insulating layer 26, an undoped polysilicon layer 27, and a second cap gate insulating layer 28 are sequentially formed on the entire surface of the substrate including the first cap gate insulating layer 25. do. In this case, the second gate insulating layer 26 is formed to be thinner than the first gate insulating layer 22.

As shown in FIG. 2C, the second cap gate insulating layer 28, the undoped polysilicon layer 27, and the second gate insulating layer 26 are selectively patterned so that only the logic portion B remains (photolithography process + Etching process).

As shown in FIG. 2D, the undoped polysilicon layer 27 of the logic portion B is defined as a PMOS and an NMOS region so that the undoped polysilicon layer 27 of the PMOS region is p-type. Impurity ions are implanted to form a second conductive polysilicon layer 29, and n-type impurity ions are implanted into the undoped polysilicon layer 27 in the NMOS region to form a first polysilicon layer ( 30).

As shown in FIG. 2E, the photoresist film PR is coated on the entire surface of the substrate including the first and second cap gate insulating layers 25 and 28, and then a gate electrode region is defined by an exposure and development process. The photoresist film PR is patterned to remain only.

Subsequently, the first cap gate insulating layer 25, the polyside 24, and the first conductive type first polysilicon layer 23 of the DRAM part A may be etched using the patterned photoresist PR as a mask. ) And the first gate insulating layer 22 are selectively etched to form a first conductive gate electrode 23a having a predetermined interval, and the second cap gate insulating layer 28 and the second of the logic unit B are formed. The conductive polysilicon layer 29 and the first conductive second polysilicon layer 30 are selectively removed to form the first conductive gate electrode 30a and the second conductive gate electrode 29a.

As shown in FIG. 2F, the side surfaces of the polyside 24 and the first and second conductive gate electrodes 23a, 30a, and 29a of the DRAM unit A and the logic unit B are oxidized. To form the side oxide film 31. Subsequently, low concentration impurity ions are implanted into the semiconductor substrate 21 under both sides of the gate electrodes 23a, 30a and 29a by using the gate electrodes 23a, 30a and 29a as masks. ).

As shown in FIG. 2G, an insulating film is formed on the entire surface of the substrate including the gate electrodes 23a, 30a, and 29a, and then the insulating film is etched back by an etch back process using reactive ion etching. Sidewall spacers 33 are formed on the side surfaces of 23a, 30a, and 29a. At this time, the first and second cap gate insulating layers 25 and 28 are removed. Next, using the sidewall spacer 33 as a mask, a high concentration of impurity ions are implanted into the semiconductor substrate 21 on both lower sides of the gate electrodes 23a, 30a, and 29a to form a source / drain region 34. do.

As shown in FIG. 2H, an insulating film 35 is formed on a substrate including the gate electrode 23a and the sidewall spacer 33 of the DRAM unit A, and then the semiconductor substrate of the logic unit B is formed. 21 and the silicide 36 is formed above the gate electrodes 30a and 29a.

In the method of manufacturing a semiconductor device according to the present invention, when the gate electrode is formed in the DRAM unit and the logic unit, the process is performed separately to provide a gate electrode optimized in each part, thereby providing a highly reliable semiconductor device manufacturing method. .

Claims (2)

Preparing a semiconductor substrate; Defining the semiconductor substrate as a DRAM unit and a logic unit, and then sequentially forming a first gate insulating layer, a first conductive polysilicon layer, a polyside, and a first cap gate insulating layer on the semiconductor substrate of the DRAM unit; Forming a second gate insulating film, an undoped polysilicon layer, and a second cap gate insulating film on the semiconductor substrate defined by the logic unit; The logic portion is defined as an NMOS and a PMOS region, an n-type impurity ion is implanted into the undoped polysilicon layer of the NMOS region to form an n-type doped polysilicon layer, and the undoped of the PMOS region Implanting p-type impurity ions into the polysilicon layer to form a p-type doped polysilicon layer; The first cap gate insulating layer, the polyside, the first conductive polysilicon layer and the first gate insulating layer and the second cap gate insulating layer, the n, p-type doped polysilicon layer, and the second gate insulating layer of the DRAM part Selectively patterning the gate electrodes to form gate electrodes having a predetermined interval; Removing the first and second cap gate insulating layers of the DRAM unit and the logic unit; Forming sidewall spacers on side surfaces of the gate electrodes; And forming a silicide on an upper surface of the gate electrode and the semiconductor substrate of the logic unit. The method of manufacturing a semiconductor device according to claim 1, wherein a reoxidation process is performed on the side surface of the gate electrode before the process of forming sidewall spacers on the side surface of the gate electrode.

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