JPH04206594A - Printed board surface treatment structure - Google Patents
Printed board surface treatment structureInfo
- Publication number
- JPH04206594A JPH04206594A JP32938990A JP32938990A JPH04206594A JP H04206594 A JPH04206594 A JP H04206594A JP 32938990 A JP32938990 A JP 32938990A JP 32938990 A JP32938990 A JP 32938990A JP H04206594 A JPH04206594 A JP H04206594A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- masking
- subjected
- carried out
- treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004381 surface treatment Methods 0.000 title claims description 7
- 229910000679 solder Inorganic materials 0.000 claims abstract description 63
- 238000000576 coating method Methods 0.000 claims abstract description 12
- 239000011248 coating agent Substances 0.000 claims abstract description 9
- 230000004907 flux Effects 0.000 claims abstract description 9
- 230000001681 protective effect Effects 0.000 claims abstract 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000011889 copper foil Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 24
- 238000005476 soldering Methods 0.000 abstract description 18
- 230000000873 masking effect Effects 0.000 abstract description 15
- 238000007639 printing Methods 0.000 abstract description 10
- 239000000463 material Substances 0.000 abstract description 5
- 238000003780 insertion Methods 0.000 abstract description 2
- 230000037431 insertion Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000007423 decrease Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000004043 dyeing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3489—Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、混載実装のプリント基板をはんだ付する場合
のはんだフローアップ率を高く維持するために有効な手
段であり、プリント基板全般に活用可能なプリント基板
表面処理構造に間する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is an effective means for maintaining a high solder flow-up rate when soldering mixed-mounted printed circuit boards, and can be applied to all printed circuit boards. Possible printed circuit board surface treatment structure.
第３図は、はんだコート基板を示したものであり、図中
１は基材、２．３．４は部品面に実装の表面実装部品フ
ットパターン、５．６ははんだ面に実装の表面実装部品
フットパターン、７は挿入部品用ランドでいずれも銅箔
である。Figure 3 shows a solder coated board, in which 1 is the base material, 2.3.4 is the foot pattern of surface mount components mounted on the component side, and 5.6 is the surface mount component mounted on the solder side. The component foot pattern 7 is a land for an inserted component, and all of them are made of copper foil.
第４図は、第３図の拡大断面図であり、８−１〜８−５
．８−１１〜８−１２は部品面のはんだコート、８−２
１〜８−２５．８−３１〜８−３２ははんだ面のはんだ
コート部を示す。この断面図で分かるようにはんだコー
ト部はフュージング（はんだを溶融させた後再凝固させ
ること）処理を行なうため円弧形状になる。FIG. 4 is an enlarged sectional view of FIG. 3, and 8-1 to 8-5.
．． 8-11 to 8-12 are solder coats on component surfaces, 8-2
1 to 8-25, and 8-31 to 8-32 indicate solder coated portions on the solder surface. As can be seen from this cross-sectional view, the solder coated portion has an arcuate shape due to fusing (melting and then resolidifying the solder) process.
混載実装の代表的なはんだ付工程としては、部品面をリ
フロー、はんだ面をフロ一方式、または部品面、はんだ
面共リフロ一方式があり、この選択は表面実装部品の比
率と実装面により決定される。Typical soldering processes for mixed mounting include reflow on the component side, flow on the solder side, or reflow on both the component and solder sides.The selection is determined by the ratio of surface mount components and the mounting surface. be done.
部品面リフロー、はんだ面フロ一方式のプロセスを第５
図、第６図で説明する。第５図は製造プロセス、第６図
（ａ）ははんだペースト印刷後の断面、第６１１！Ｉ
（ｂ）はりフロー後の断面、第６図（Ｃ）はＳＭＤ搭載
の断面を示す。こ二で９−１〜９−５ははんだペースト
、１０−１〜１Ｏ−５はりフロー後のはんだ接続部、１
１は部品面実装ＳＭＤ、１２ははんだ面実装ＳＭＤを示
す。はんだコート基板で問題となるのははんだペースト
印刷工程てあり、はんだコート作業は溶融中の半田を熱
風で吹き付は再凝固させるため、はんだコー）ｇ８−１
〜８−５．８−２１〜８−２５のはんだ量バラツキが大
きくなる。一方はんだペーストはスクリーンによる印刷
のため高さ方向が均一となり、はんだコートのばらつき
量がペースト印刷時のペースト量のばらつきとなる。第
６図（ｂ）のはんだ接続部１０−１〜１０−５の各々の
間で、はんだブリッヂやはんだ不足によるリード浮きか
発生する場合がある０次にはんだ面へのＳＭＤ搭載を第
６図（Ｃ）に示す。この工程でははんだコート形状が円
弧のため部品リードの位置決めが狭小リードになる程、
フットパターン５の中心からのずれ率が多くなり位置ず
れやはんだブリッヂ発生の原因となる。The fifth process is one-sided reflow on the component side and flow on the solder side.
This will be explained with reference to FIG. Fig. 5 shows the manufacturing process, Fig. 6(a) shows the cross section after printing the solder paste, and Fig. 611! I
(b) A cross section after beam flow, and FIG. 6(C) shows a cross section of the SMD mounted. 9-1 to 9-5 are solder pastes, 10-1 to 1O-5 are solder connections after beam flow, 1
1 indicates a component surface mount SMD, and 12 indicates a solder surface mount SMD. The problem with solder-coated boards is the solder paste printing process, and during the solder coating process, the molten solder is blown with hot air to re-solidify it, so solder coat) g8-1
~8-5. The variation in the amount of solder from 8-21 to 8-25 becomes large. On the other hand, since the solder paste is printed using a screen, it is uniform in the height direction, and the amount of variation in the solder coating becomes the variation in the amount of paste when printing the paste. Figure 6 shows the mounting of the SMD on the zero-order solder surface, which may cause solder bridges or floating leads due to insufficient solder between each of the solder connections 10-1 to 10-5 in Figure 6(b). Shown in (C). In this process, the shape of the solder coat is an arc, so the positioning of the component leads becomes narrower.
The rate of deviation of the foot pattern 5 from the center increases, causing positional deviation and the occurrence of solder bridges.
第７図は、プリフラックスコートの銅スルーホール基板
を示し・たものであり、図中１〜７Ｌｔ第３図と同一で
ある。第８図は第７図の拡大断面図、第９図はＳＭＤ搭
載状態を示す。第４図のはんだコート部の円弧形状に比
較すると、プリフラックス１３−１〜１３−５．１３−
１１〜１３−１２．１３−２１〜１３−２５．１３−３
１〜１３−３２は全面均一に塗布される。このため第６
図で問題となっているはんだペースト量のばらつきや、
はんだ部品の位置決め等は、はんだコート基板に比較す
ると改善される。しかし、混載実装の表面実装部品比率
が高くなると、はんだ付は方式も部品面リフロー、はん
だ面リフロー、その後局部フロートなり、はんだ付は工
程も多岐である。プリフラックスは上記工程では３回の
はんだ付けに対しての効果が要求されるが、はんだ付は
回数の増加に対し、はんだ揚り率は逆に低下する傾向に
あり、最終のフローはんだ付は工程でのはんだ揚り率低
下はばんだ接続信頼性に大きく影響する。FIG. 7 shows a pre-flux coated copper through-hole board, and is the same as FIG. FIG. 8 is an enlarged sectional view of FIG. 7, and FIG. 9 shows the SMD mounted state. Comparing the arc shape of the solder coat part in Fig. 4, preflux 13-1 to 13-5.13-
11-13-12.13-21-13-25.13-3
Nos. 1 to 13-32 are applied uniformly over the entire surface. For this reason, the sixth
The problem in the figure is the variation in the amount of solder paste,
Positioning of solder parts, etc. is improved compared to solder-coated boards. However, as the proportion of surface-mounted components in mixed mounting increases, the soldering process becomes more diverse, including component-side reflow, solder-side reflow, and then local float. Preflux is required to be effective for three times of soldering in the above process, but as the number of soldering increases, the soldering rate tends to decrease, and the final flow soldering Decrease in soldering rate during the process greatly affects solder connection reliability.
この様に、はんだコート基板では、はんだ揚り率は間Ｈ
にならないが、部品の位置決め精度、はんだペースト量
のバラツキが欠点となる。一方プリフラックスは部品の
位置決め精度、はんだペースト量のバラツキは問題にな
らないが、はんだ付は回数の増加に対しブラックスの効
果が低減し、はんだ揚り率が低下する欠点がある。In this way, with a solder-coated board, the solder coverage rate is between H
However, the drawbacks are the positioning accuracy of parts and the variation in the amount of solder paste. On the other hand, with preflux, there are no problems with component positioning accuracy or variations in the amount of solder paste, but the disadvantage is that the effectiveness of the brax decreases as the number of soldering increases, and the soldering rate decreases.
はんだコート基板では、はんだコート部が円弧形状にな
るため、特に表面実装の狭小リードピッチ部品の位置決
め精度低下とはんだペースト量のばら付きが多くなり問
題となる。In a solder-coated board, the solder-coated portion has an arc shape, which causes problems such as a decrease in positioning accuracy and a large variation in the amount of solder paste, especially for surface-mounted narrow lead pitch components.
一方のプリフラックスは両面混載実装になりプリント基
板のはんだ付は工程も増加し、はんだ揚り性が徐々に低
下する。特に挿入部品は最後のはんだ付は工程になるた
め、スルーホール部のはんだ揚り率低下は接続の信頼性
に大きく影響する０、本発明の目的は、はんだコートと
プリフラックス処理を同一基板で実施することにより、
混載実装基板のはんだ揚り性と位置決め精度向上を目的
とした構造である。On the other hand, preflux requires double-sided mounting, which increases the number of steps required for soldering printed circuit boards, and gradually reduces solderability. In particular, since the final soldering of inserted parts is a process, a decrease in the soldering rate at the through-hole section will greatly affect the reliability of the connection.The purpose of the present invention is to perform solder coating and preflux treatment on the same board. By implementing
This structure aims to improve the solderability and positioning accuracy of mixed mounting boards.
上記目的を達成するために、同一プリント基板のコーテ
ィング処理において、挿入部品部分はプリフラックス処
理を行なった構造である。In order to achieve the above object, the inserted parts are subjected to pre-flux treatment in the coating process of the same printed circuit board.
挿入部品ははんだコート、表面実装部品はプリフラック
ス処理を行なうことにより、はんだ付は性向上を実現す
る。Soldering properties are improved by applying a solder coat to insert parts and pre-flux treatment to surface mount parts.
３１１１０図に従来のプリント基板製造工程の１部を示
す、ソルダーレジス１４布、シルク文字印刷後表面処理
工程に移る。この段階ではんだコート、プリフラックス
処理のいずれかの工程を通り外形加工へと続く。Figure 31110 shows part of the conventional printed circuit board manufacturing process. After printing the solder resist 14 cloth and silk letters, the process moves to the surface treatment process. At this stage, the product goes through either solder coating or preflux treatment, followed by external processing.
これに対し本発明の工程は第１１図、第１２図のいずれ
でも可能である。第１１図は文字印刷後表面実装部品フ
ットパターン部のマスキング処理を行なった後、はんだ
コート、マスキング剥１１１作業を経て基板全体をプリ
フラックス処理し、外形加工へと続く。一方第１２図は
文字印字後基板全体をプリフラックス処理後、表面実装
部品フットパターン部をマスキングし、挿入部品用ラン
トのはんだコート、マスキング剥離、外形加工へと続く
。On the other hand, the process of the present invention can be performed in either FIG. 11 or FIG. 12. In FIG. 11, after character printing, the foot pattern portion of the surface mount component is masked, followed by solder coating and masking removal 111, followed by preflux treatment of the entire board, followed by external processing. On the other hand, in FIG. 12, after character printing, the entire board is prefluxed, the surface mount component foot pattern portion is masked, and the solder coating of the runt for the inserted component, masking peeling, and contour processing are continued.
両者工程のマスキング方法としては、はんだ耐熱性を有
するマスキング材を印刷するために予め表面実装部品の
フットパターン部をコートする形状のマスク設計を行な
い、印刷法によりマスキング作業を一括で行ない熱硬化
する。印刷方式のためマスキング形状は任意に形成出来
るため、剥離作業を容易にする形状とする。As for the masking method for both processes, in order to print a masking material that is resistant to soldering heat, a mask is designed in advance to coat the foot pattern part of the surface mount component, and the masking work is performed all at once using the printing method, and then heat cured. . Because it is a printing method, the masking shape can be formed arbitrarily, so the shape is designed to facilitate the peeling operation.
第１図と第２図に本発明の一実施例を示す。 An embodiment of the present invention is shown in FIGS. 1 and 2. FIG.
図中の番号で第３、第４、第７、第８図の一致する番号
は同一内容である。又、８−１１．８−１２．８−３１
．８−３２はプリフラックスを示す。The same numbers in the figures 3, 4, 7, and 8 have the same contents. Also, 8-11.8-12.8-31
．． 8-32 indicates preflux.
プリント基板の製造工程は第１１図、第１２図に示す如
くである。The manufacturing process of the printed circuit board is as shown in FIGS. 11 and 12.
第１図の製造工程としては、ソルダーレジスト塗布、シ
ルク文字印刷後部品面の表面実装部品フッＩ・パターン
２．３．４及びはんだ面実装の表面実装部品フットパタ
ーン部５．６にマスキング処理を行なう。次にはんだコ
ート処理を実施することにより、第２図のプリフラック
ス８−１１．８−３１．８−３２が形成される。そして
マスキング部分を剥離後プリフラックス処理を行ない、
１３−１〜１３−１５．１３−２１〜１３−２５．１３
−５１〜１３−５２．１３−６１．１３−６２を形成す
ることが可能である。The manufacturing process shown in Fig. 1 includes applying a solder resist, printing silk letters, and then masking the surface mount component foot pattern 2.3.4 on the component surface and the surface mount component foot pattern 5.6 for solder surface mounting. Let's do it. Next, by performing a solder coating process, preflux 8-11.8-31.8-32 shown in FIG. 2 is formed. Then, after peeling off the masking part, preflux treatment is performed.
13-1~13-15.13-21~13-25.13
-51 to 13-52.13-61.13-62.
部品実装工程は第５図と同一である。はんだ接続順番を
第２図の拡大断面図で説明すると、最初に部品面の表面
実装パターン１３−１〜１３−５．２番目にはんだ面の
表面実装パターン１３−２１〜１３−２５、特に狭小リ
ードピッチの場合光学式位置検出方式となり、プリフラ
ックスは平坦な面を形成出来、より有効である。最後に
８−１１．８−１２．８−３１．８−３２となる。この
順番ではんだ付は実施することによりフラックスの効果
低減防止や挿入部品８−１１．８−１２のはんだ揚り性
紙下を防止することが可能である。The component mounting process is the same as that shown in FIG. To explain the solder connection order using the enlarged cross-sectional view of Fig. 2, first the surface mounting patterns 13-1 to 13-5 on the component side are connected, and second, the surface mounting patterns 13-21 to 13-25 on the solder side, especially the narrow ones. In the case of lead pitch, an optical position detection method is used, and preflux can form a flat surface, which is more effective. Finally, it becomes 8-11.8-12.8-31.8-32. By performing soldering in this order, it is possible to prevent a reduction in the effect of flux and to prevent the solder from rising under the paper on the inserted parts 8-11, 8-12.
本発明により下記の効果がある。 The present invention has the following effects.
（１）混載実装プリント基板のはんだ付は性向上（２）
狭小ピッチリード部品の搭載精度向上（３）搭載機の検
出精度向上(1) Improved soldering performance of mixed mounting printed circuit boards (2)
Improving the mounting accuracy of narrow pitch lead components (3) Improving the detection accuracy of the mounting machine
【図面の簡単な説明】
第１図は本発明の一実施例を示すパターンの平面図、第
２図は第１図の拡大断面図、第３図ははんだコート基板
を示す平面図、第４図は第３図の拡大断面図、第５ｒＩ
！Ｊは製造プロセスを示すフロー図、第６図は製造プロ
セス内の解説を示す図、第７図はプリフラックスコート
基板を示す平面図、第８図は第７図の拡大断面図、第９
図はＳＭＤを搭載した拡大断面図、第１０図は従来のプ
リント基板製造工程の１部を示す工程図、第１１図、第
１２図は本発明の一実施例を示す製造工程図である。
ｌ・・・基材、２．３．４．５．６・・・表面実装部品
フットパターン、７・・・挿入部品用ラント、８・・・
はんだコー）（８−１・・・８−３２） 、９・・・は
んだベースト（９−１・・・９−５）、１０・・・リフ
ロー後のはんだ接続部、１１・・・部品面実装ＳＭＤ、
１２・・・はんだ面突１＊ｓＭＤ、１３・−・プリフラ
ックス〈１３−１・・・１３−３２）
：染１し ブ 【＝７１
＄ ３ 図
＄ ４ 図
第 ８ 図
第 ９ 図[Brief Description of the Drawings] Fig. 1 is a plan view of a pattern showing one embodiment of the present invention, Fig. 2 is an enlarged sectional view of Fig. 1, Fig. 3 is a plan view showing a solder coated board, and Fig. 4 is a plan view of a pattern showing an embodiment of the present invention. The figure is an enlarged sectional view of Figure 3, No. 5rI.
! J is a flow diagram showing the manufacturing process, FIG. 6 is a diagram showing an explanation of the manufacturing process, FIG. 7 is a plan view showing the pre-flux coated substrate, FIG. 8 is an enlarged sectional view of FIG. 7, and FIG.
The figure is an enlarged sectional view of an SMD mounted therein, FIG. 10 is a process diagram showing a part of a conventional printed circuit board manufacturing process, and FIGS. 11 and 12 are manufacturing process diagrams showing an embodiment of the present invention. l... Base material, 2.3.4.5.6... Surface mount component foot pattern, 7... Runt for insertion component, 8...
Solder base) (8-1...8-32), 9... Solder base (9-1...9-5), 10... Solder connection after reflow, 11... Component surface Implementation SMD,
12... Solder surface protrusion 1*sMD, 13... Preflux <13-1...13-32) : Dyeing 1 [=71 $ 3 Figure $ 4 Figure 8 Figure 9
Claims (3)
ックスによる保護構造部と、はんだコートによる保護構
造部を同一基板上に混在したプリント基板表面処理構造
。1. In copper foil surface treatment on a printed circuit board, a printed circuit board surface treatment structure in which a protective structure by pre-flux and a protective structure by solder coating are mixed on the same board.
ターンを保護する請求項１記載のプリント基板表面処理
構造。2. 2. The printed circuit board surface treatment structure according to claim 1, wherein the preflux protects a soldered foot pattern of a surface mount component.
る部品に該当するランドを保護する請求項１記載のプリ
ント基板表面処理構造。3. 2. The printed circuit board surface treatment structure according to claim 1, wherein the solder coating protects lands corresponding to parts into which leads are inserted into the printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32938990A JPH04206594A (en) | 1990-11-30 | 1990-11-30 | Printed board surface treatment structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32938990A JPH04206594A (en) | 1990-11-30 | 1990-11-30 | Printed board surface treatment structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04206594A true JPH04206594A (en) | 1992-07-28 |
Family
ID=18220890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32938990A Pending JPH04206594A (en) | 1990-11-30 | 1990-11-30 | Printed board surface treatment structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04206594A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003036908A (en) * | 2001-07-25 | 2003-02-07 | Nec Corp | Contact terminal for surface mounting, printed circuit board using this terminal, and portable information terminal |
-
1990
- 1990-11-30 JP JP32938990A patent/JPH04206594A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003036908A (en) * | 2001-07-25 | 2003-02-07 | Nec Corp | Contact terminal for surface mounting, printed circuit board using this terminal, and portable information terminal |
| JP4613457B2 (en) * | 2001-07-25 | 2011-01-19 | 日本電気株式会社 | Contact terminal for surface mounting, printed circuit board using the terminal, and portable information terminal device |
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