JP2768358B2 - Printed circuit board for mounting multi-terminal components - Google Patents
Printed circuit board for mounting multi-terminal componentsInfo
- Publication number
- JP2768358B2 JP2768358B2 JP9003564A JP356497A JP2768358B2 JP 2768358 B2 JP2768358 B2 JP 2768358B2 JP 9003564 A JP9003564 A JP 9003564A JP 356497 A JP356497 A JP 356497A JP 2768358 B2 JP2768358 B2 JP 2768358B2
- Authority
- JP
- Japan
- Prior art keywords
- lands
- land
- printed circuit
- circuit board
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【発明の詳細な説明】
【0001】
【産業用の利用分野】本発明は、フラットパッケージ型
LSIなどの多端子部品の各端子を該各端子に対向する
ようにプリント基板上に規則的に配置した複数個のラン
ドにそれぞれはんだ付けする多端子部品実装用プリント
基板に係り、特に、はんだ付けの際、各ランド間の短絡
あるいははんだ不足による接続不良などの欠点を生ずる
ことのない多端子部品実装用プリント基板に関する。
【0002】
【従来の技術】フラットパッケージ型LSIのプリント
基板への実装は、図3および図4に示すように、該LS
I6の各端子8を、該各端子8に対向するようにプリン
ト基板1上に規則的に配置した複数個のランド3にそれ
ぞれはんだ付けすることによって行われる。ここで、は
んだの供給は、予めプリント基板1の各ランド3上には
んだペーストをパターン印刷しておくことによって行
い、また、はんだ付け操作はレーザ、ベーパリフローあ
るいは熱風等による加熱によって行われれている。
【0003】近年ますます高密度化しているLSIにお
いて、各端子のピッチは0.65mmから0.5mmへ、端
子幅は0.3mmから0.25mmへ移行しつつあり、ま
た、プリント基板においても、ランド間隔が0.25mm
から0.15mmに移行しつつあるなど、微細化が急速に
進行している。このため、はんだペースト5の印刷は、
印刷作業性向上のため、一方向に配置されたランド3を
一括して帯状に被覆する(図4はんだペースト5)方法
を採る場合が多く、該帯状はんだパターンの幅は、通
常、0.35〜0.55mmとされている。ここで、ラン
ド3間を埋めたはんだは、プリント基板面に対する濡れ
性が小さいため、加熱はんだ付けの際、溶融状態で基板
面から遊離して、表面張力により各ランドに集まり、結
果的に各ランド間のはんだは吸引除去された状態となる
ものであるが、図5に示すように、印刷はんだ量が多す
ぎる場合にははんだがランド間に残存して短絡10を生
じ、また、印刷はんだ量が少なすぎる場合にははんだ不
足11を生ずることになる。これらの欠点の発生を防止
するためには、はんだペースト5供給量の適量を選び、
かつ、これを一定に被覆することが重要な要素となる。
【0004】ランド間の短絡を防止し、かつ、実装作業
時の位置合わせを容易にする方法として、先に、ランド
周辺に、ランドに密接して、ランドの厚さよりも厚い光
硬化性の絶縁樹脂層を形成する方法が提案されている
(特公昭第61-32840号)。この方法によれば、
ランド間が予め隔離されているため、実装作業に際し
て、短絡の問題を起すことは少なくなる。
【0005】
【発明が解決しようとする課題】しかしながら、ランド
周辺に該ランドの厚さよりも厚い光硬化性絶縁性樹脂層
を形成した場合、該ランド部が凹状となり、はんだを帯
状に印刷した時に、該凹状部分ではんだペーストがだれ
やすく、その断面形状が不均一となり、はんだペースト
量が各ランドに対して一定になりにくいという欠点があ
り、また、印刷時に、ステンレス製メタルマスクが光硬
化性絶縁樹脂層に圧着され、強く押圧されるため、該樹
脂層の端部に微細クラックが発生し、はんだ付け時の熱
負荷によってクラックが顕在化したり、密着性が低下す
るという欠点がある。
【0006】また、ランド周辺に光硬化性絶縁樹脂層が
存在しない場合にも、同様に、ランド間の凹状部分では
んだペーストがだれるため、ランド部へのはんだ供給量
が不均一になるという欠点がある。
【0007】本発明は、上記従来技術にみられる欠点を
解決し、端子ピッチの微細なLSIの端子をプリント基
板上の各ランドにはんだ付けをする際に、該ランドに適
量のはんだペーストを均一に供給できるプリント基板を
提供することを目的とする。
【0008】
【問題点を解決するための手段】上記目的は、LSIの
各端子に対向してプリント基板上に規則的に配置された
複数個のランドの周辺に、該各ランドに密接して、該ラ
ンドの厚さの約3分の1以上で該ランドの厚さを越えな
い範囲の厚さの光硬化性絶縁性樹脂層を設けることによ
って達成することができる。
【0009】
【作用】プリント基板上のランドの周辺に、該ランドに
密接して設けた光硬化性絶縁性樹脂層の厚さが該ランド
の厚さの3分の1以上で該ランドの厚さを超えない範囲
であるため、ランドとランド以外の部分の段差が小とな
り、より平坦化されていることによって、はんだペース
ト印刷時のペーストのだれが小となり、各ランド当りの
はんだ量が均一となる。
【0010】また、絶縁膜層の高さがランドの高さと同
じかそれよりも低いため、はんだペースト印刷時に、前
記従来技術にみられたようなメタルマスクの押圧による
絶縁樹脂層のクラック現象が発生することがない。
【0011】
【実施例】以下本発明の一実施例について図面によって
説明する。
【0012】図1は本発明による多端子部品実装用プリ
ント基板およびそれに実装すべきLSIを示す概略摸式
図で、多端子部品実装用プリント基板1は基材2上にL
SIの各端子に対向するように規則的に配置した複数個
のランド3、該各ランド3周辺に該各ランドに密接し
て、該各ランド3の厚さの3分の1以上でランドの厚さ
を越えない範囲の厚さで設けた光硬化性絶縁性樹脂層4
からなり、LSI6はLSI本体7および該LSI本体
7の周辺に一方向に突設して設けられた複数個の端子8
からなることを示す。ここで、ランド部周辺に該ランド
に密接して設ける光硬化性絶縁性樹脂層4の形成は、ま
ず、予めランド3を設けた基材2の全面に、該ランドの
厚さの3分の1以上の厚さで該ランドの厚さを越えない
範囲の厚さの該光硬化性絶縁性樹脂層を塗布し、次い
で、所定パターンのマスクを用いてランド3以外の部分
を露光し、硬化させ、さらに、現像処理を施すことによ
りランド3部の該樹脂層を溶解除去することにより行な
った。なお、該ランド部については、はんだ付け性を良
好ならしめるため、無電解銅めっきを施した。上記のよ
うにして得られた基板について、はんだペースト5の帯
状パターン印刷を行ったが、ランド3間の絶縁樹脂層4
上のおいてはんだペースト5のだれることのない均一な
はんだ層を得ることができた。この基板について、さら
に、LSI6の各端子8をそれぞれ対向するランド3上
に載置してはんだ付け操作を行ったが、図2にみられる
ように、各端子間の短絡不良やはんだ不足などの欠点の
ない良好なはんだ付け部9を得ることができた。
【0013】なお、図3は本発明による多端子部品プリ
ント基板を用いたLSI実装の完了した状態を示す概略
斜視図である。
【0014】
【発明の効果】以上述べてきたように、フラットパッケ
ージLSI等多端子部品実装用のプリント基板を、本発
明の構成によるプリント基板、すなわち、ランド周辺
に、該ランドに密接して、該ランドの厚さの約3分の1
以上で該ランドの厚さを越えない範囲の厚さの光硬化性
絶縁性樹脂を設けることによりランドとランド以外の部
分との段差を小さくしたプリント基板とすることによっ
て、はんだ供給を均一に行うことができ実装時における
ランド間の短絡不良あるいははんだ不足等の不良の発生
を防止することができた。また、その結果、短絡部の検
査あるいは欠陥部の修正作業等の簡潔化あるいは省略化
をはかることができ、作業の効率向上に寄与することが
できた。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for regularly arranging terminals of a multi-terminal component such as a flat package type LSI on a printed circuit board so as to face the terminals. The present invention relates to a printed circuit board for mounting a multi-terminal component, which is to be soldered to a plurality of lands, respectively. For printed circuit boards. 2. Description of the Related Art As shown in FIGS. 3 and 4, a flat package type LSI is mounted on a printed circuit board.
This is performed by soldering each terminal 8 of I6 to a plurality of lands 3 regularly arranged on the printed circuit board 1 so as to face each terminal 8. Here, the supply of the solder is performed by pattern-printing a solder paste on each land 3 of the printed circuit board 1 in advance, and the soldering operation is performed by heating with a laser, vapor flow, hot air, or the like. . [0003] In recent years, in LSIs which have become increasingly dense, the pitch of each terminal is shifting from 0.65 mm to 0.5 mm, and the terminal width is shifting from 0.3 mm to 0.25 mm. , Land spacing 0.25mm
From 0.15 mm to 0.15 mm. For this reason, printing of the solder paste 5
In order to improve the printing workability, a method of collectively covering the lands 3 arranged in one direction in a band shape (the solder paste 5 in FIG. 4) is often adopted, and the width of the band-shaped solder pattern is usually 0.35. 0.50.55 mm. Here, the solder filled between the lands 3 has low wettability with respect to the printed circuit board surface, so that the solder is released from the board surface in a molten state at the time of heat soldering, and is collected on each land by surface tension. The solder between the lands is in a state of being removed by suction. However, as shown in FIG. 5, when the amount of the printed solder is too large, the solder remains between the lands to cause a short circuit 10, and the printed solder is removed. If the amount is too small, a solder shortage 11 will occur. In order to prevent the occurrence of these defects, an appropriate amount of the solder paste 5 is selected.
In addition, it is an important element to coat the coating uniformly. As a method of preventing a short circuit between lands and facilitating alignment during a mounting operation, first, a photo-curable insulating material having a thickness larger than the thickness of the land is provided close to the land. A method of forming a resin layer has been proposed (Japanese Patent Publication No. 61-32840). According to this method,
Since the lands are isolated in advance, the occurrence of a short circuit problem during the mounting operation is reduced. [0005] However, when a photocurable insulating resin layer thicker than the land is formed around the land, the land becomes concave, and when the solder is printed in a strip shape, the land becomes concave. However, the solder paste tends to drip in the concave portion, the cross-sectional shape becomes non-uniform, and the amount of the solder paste is difficult to be constant with respect to each land. Since it is press-bonded to the insulating resin layer and strongly pressed, a minute crack is generated at an end of the resin layer, and there is a defect that the crack becomes apparent due to a heat load at the time of soldering or the adhesion decreases. Further, even when the photocurable insulating resin layer does not exist around the lands, the solder paste flows in the concave portions between the lands, so that the amount of the solder supplied to the lands becomes uneven. There are drawbacks. The present invention solves the above-mentioned disadvantages of the prior art, and when soldering terminals of an LSI having a fine terminal pitch to each land on a printed circuit board, an appropriate amount of solder paste is uniformly applied to the land. It is an object of the present invention to provide a printed circuit board that can be supplied to a computer. The object of the present invention is to provide a method in which a plurality of lands regularly arranged on a printed circuit board in opposition to terminals of an LSI are provided in close proximity to the lands. This can be achieved by providing a photocurable insulating resin layer having a thickness of not less than about one third of the thickness of the land and not exceeding the thickness of the land. The thickness of the photocurable insulating resin layer provided in close proximity to the land on the printed circuit board is at least one third of the thickness of the land, and Because of this, the step between the land and the land other than the land is small, and the surface is flattened, so that the dripping of the paste during solder paste printing is small and the amount of solder per land is uniform. Becomes In addition, since the height of the insulating film layer is equal to or lower than the height of the land, cracking of the insulating resin layer due to the pressing of the metal mask as seen in the above-described prior art during the printing of the solder paste is caused. Does not occur. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing a printed circuit board for mounting multi-terminal components according to the present invention and an LSI to be mounted on the printed circuit board.
A plurality of lands 3 regularly arranged so as to face the respective terminals of the SI; Photocurable insulating resin layer 4 provided with a thickness not exceeding the thickness
The LSI 6 comprises an LSI body 7 and a plurality of terminals 8 protrudingly provided in one direction around the LSI body 7.
It consists of. Here, the formation of the photocurable insulating resin layer 4 provided in close contact with the land around the land is performed by first forming a three-thirds of the thickness of the land on the entire surface of the base material 2 on which the land 3 is provided in advance. Apply the photocurable insulating resin layer having a thickness of not less than 1 and not exceeding the thickness of the land, and then exposing a portion other than the land 3 using a mask having a predetermined pattern, and curing. Then, the resin layer of three lands was dissolved and removed by performing a developing process. The lands were plated with electroless copper in order to improve the solderability. On the substrate obtained as described above, the band-shaped pattern printing of the solder paste 5 was performed.
A uniform solder layer without dripping of the solder paste 5 was obtained above. With respect to this substrate, the respective terminals 8 of the LSI 6 were further placed on the lands 3 facing each other and soldering was performed. As shown in FIG. A good soldered portion 9 without defects could be obtained. FIG. 3 is a schematic perspective view showing a state in which LSI mounting using the multi-terminal component printed board according to the present invention is completed. As described above, a printed circuit board for mounting a multi-terminal component such as a flat package LSI is placed on a printed circuit board according to the structure of the present invention, that is, close to the land. About 1/3 of the thickness of the land
By providing a photocurable insulating resin having a thickness not exceeding the thickness of the land as described above, a printed board having a small step between the land and the portion other than the land is provided, so that the solder is uniformly supplied. As a result, it was possible to prevent the occurrence of defects such as short-circuit failure between lands or insufficient solder during mounting. As a result, it was possible to simplify or omit the work of inspecting the short-circuited portion or correcting the defective portion, and contributed to the improvement of the work efficiency.
【図面の簡単な説明】
【図1】本発明による多端子部品実装用プリント基板お
よび該基板に実装するLSIを示す概略部分摸式図。
【図2】本発明による多端子部品実装用プリント基板を
用いてLSIの実装を行った状態を示す概略部分摸式
図。
【図3】本発明による多端子部品実装用プリント基板を
用いてLSIの実装が完了した状態を示す該略斜視図。
【図4】従来技術による多端子部品実装用プリント基板
および該基板に実装するLSIを示す概略部分摸式図。
【図5】従来技術による多端子部品実装用プリント基板
を用いてLSIの実装を行った状態を示す概略部分摸式
図である。
【符号の説明】
1…多端子部品実装用プリント基板、2…基材、3…ラ
ンド、4…光硬化性絶縁性樹脂層、5…はんだペース
ト、6…LSI、7…LSI本体、8…端子、9…はん
だ付け部、10…短絡、11…はんだ不足。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic partial schematic view showing a printed circuit board for mounting a multi-terminal component and an LSI mounted on the board according to the present invention. FIG. 2 is a schematic partial schematic view showing a state where an LSI is mounted using a printed circuit board for mounting multiple terminals according to the present invention. FIG. 3 is a schematic perspective view showing a state in which mounting of an LSI is completed using the printed circuit board for mounting multiple terminals according to the present invention. FIG. 4 is a schematic partial schematic diagram showing a printed circuit board for mounting a multi-terminal component according to a conventional technique and an LSI mounted on the board. FIG. 5 is a schematic partial schematic view showing a state where an LSI is mounted using a printed circuit board for mounting a multi-terminal component according to a conventional technique. [Description of Signs] 1 ... Printed circuit board for mounting multi-terminal components, 2 ... Base material, 3 ... Land, 4 ... Photocurable insulating resin layer, 5 ... Solder paste, 6 ... LSI, 7 ... LSI body, 8 ... Terminal, 9: Solder, 10: Short circuit, 11: Insufficient solder.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小関 護 神奈川県横浜市戸塚区戸塚町216番地 株式会社日立製作所戸塚工場内 (56)参考文献 特開 昭59−148388(JP,A) 特開 昭52−93271(JP,A) 特開 昭57−76897(JP,A) (58)調査した分野(Int.Cl.6,DB名) H05K 3/34 502 H05K 3/28──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Mamoru Koseki 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Totsuka Plant of Hitachi, Ltd. (56) References JP-A-59-148388 (JP, A) JP-A Sho 52-93271 (JP, A) JP-A-57-76897 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H05K 3/34 502 H05K 3/28
Claims (1)
プリント基板上に規則的に配置した複数個のランドに印
刷法によりはんだを供給し、前記各端子と前記複数個の
ランドとをそれぞれリフローはんだ付けする多端子部品
実装用プリント基板において、 前記ランド周辺に、該ランドに密接して、該ランドの厚
さの約3分の1以上で該ランドの厚さを越えない範囲の
厚さの光硬化性の絶縁性樹脂層を設けたことを特徴とす
る多端子部品実装用プリント基板。(57) [Claims] Each terminal of the multi-terminal component is marked on a plurality of lands regularly arranged on a printed circuit board so as to face the respective terminals.
The solder is supplied by a printing method, and each of the terminals and the plurality of
A multi-terminal component mounting printed board for reflow-soldering the lands with the lands, wherein the lands are in close proximity to the lands and not more than about one-third of the thickness of the lands. A printed board for mounting multi-terminal components, comprising a photocurable insulating resin layer having a thickness in a range.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9003564A JP2768358B2 (en) | 1997-01-13 | 1997-01-13 | Printed circuit board for mounting multi-terminal components |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9003564A JP2768358B2 (en) | 1997-01-13 | 1997-01-13 | Printed circuit board for mounting multi-terminal components |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62226265A Division JPH0666541B2 (en) | 1987-09-11 | 1987-09-11 | Printed circuit board for mounting multi-terminal components |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09186440A JPH09186440A (en) | 1997-07-15 |
JP2768358B2 true JP2768358B2 (en) | 1998-06-25 |
Family
ID=11560934
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9003564A Expired - Fee Related JP2768358B2 (en) | 1997-01-13 | 1997-01-13 | Printed circuit board for mounting multi-terminal components |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2768358B2 (en) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5293271A (en) * | 1976-02-02 | 1977-08-05 | Hitachi Ltd | Semiconductor device and its manufacture for that device |
JPS5776897A (en) * | 1980-10-31 | 1982-05-14 | Nippon Electric Co | Printed circuit board |
JPS59148388A (en) * | 1983-02-14 | 1984-08-25 | キヤノン株式会社 | Printed circuit board |
-
1997
- 1997-01-13 JP JP9003564A patent/JP2768358B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH09186440A (en) | 1997-07-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5453582A (en) | Circuit board to be precoated with solder layers and solder circuit board | |
EP0947125B1 (en) | Method of making a printed circuit board having a tin/lead coating | |
JPH0715122A (en) | Film composite for bonding and method of mounting electronic components | |
JP2768358B2 (en) | Printed circuit board for mounting multi-terminal components | |
JP2768357B2 (en) | Printed circuit board for mounting multi-terminal components | |
JP2842425B2 (en) | Multi-terminal component mounting method | |
JP2862003B2 (en) | Printed circuit board for mounting multi-terminal components | |
US5373113A (en) | Solder reflow mounting board | |
JPH0666541B2 (en) | Printed circuit board for mounting multi-terminal components | |
JPH0722749A (en) | Printed circuit board using solder layer as pre-coating and solder precoated printed circuit board | |
JP3905355B2 (en) | Mounting method of chip parts | |
JPH0443697A (en) | Soldering method | |
JPH04297091A (en) | Solder coating printed circuit board and manufacture thereof | |
JPH05283587A (en) | Soldering method of multiple-lead element | |
JP2001077522A (en) | Method of mounting electronic component | |
JPH10242629A (en) | Printed circuit board and its manufacture | |
JP3241525B2 (en) | Surface mounting method of printed wiring board | |
JPH10326956A (en) | Printed wiring board, manufacture of printed wiring board and method for mounting electronic component to printed wiring board | |
JPH0414892A (en) | Structure of solder resist opening of printed-wiring board | |
JPH02177390A (en) | Soldering method for surface mounting type electronic component | |
JPH04133492A (en) | Printed wiring board | |
JPH09191174A (en) | Printed wiring board, its production and structure for mounting electronic device on printed wiring board | |
JPH04313294A (en) | Soldering method for printed wiring board | |
JPH04181797A (en) | Coating method for cream solder on printed circuit board | |
JPH04206594A (en) | Printed board surface treatment structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |