JPH04196566A - Package for containing semiconductor element - Google Patents

Package for containing semiconductor element

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Publication number
JPH04196566A
JPH04196566A JP33282390A JP33282390A JPH04196566A JP H04196566 A JPH04196566 A JP H04196566A JP 33282390 A JP33282390 A JP 33282390A JP 33282390 A JP33282390 A JP 33282390A JP H04196566 A JPH04196566 A JP H04196566A
Authority
JP
Japan
Prior art keywords
semiconductor element
insulating base
metal layer
external lead
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33282390A
Other languages
Japanese (ja)
Other versions
JP2808044B2 (en
Inventor
Hiroshi Matsumoto
弘 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP33282390A priority Critical patent/JP2808044B2/en
Publication of JPH04196566A publication Critical patent/JPH04196566A/en
Application granted granted Critical
Publication of JP2808044B2 publication Critical patent/JP2808044B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To stably operate a semiconductor element to be contained without erroneous operation for a long period by providing on the upper surface of an insulating base a metallized metal layer, and securing an external lead terminal onto the layer through a special glass member. CONSTITUTION:An external lead terminal 5 is secured onto an insulating base 1 covered on its upper part with a metallized metal layer 4, a glass member 6 secures the terminal 5 onto the base 1 and is operated as a dielectric material of a capacity element A. The member 6 is formed of glass containing 5.0 to 50.0wt.% of perovskite type titanate as filler in 60.0 to 90.0wt.% of lead oxide, 5.0-15.0wt.% of boron oxide, and the permittivity of the glass is as high as 35.0 (1MHz at the ambient temperature). Since the member 6 has extremely high permittivity of 35.0, the electrostatic capacitance of a capacity element A to be formed between the layer 4 and the terminal 5 is extremely large, thereby effectively preventing adverse influence to a semiconductor element caused by the variation in power supply voltage by the element A.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体素子を収容するための半導体素子収納用
パッケージの改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a semiconductor element housing package for accommodating a semiconductor element.

(従来技術及びその課題) 従来、半導体素子を収容するためのパッケージ、特にガ
ラスの溶着によって封止するガラス封止型の半導体素子
収納用パッケージは、アルミナセラミックス等の電気絶
縁材料から成り、中央部に半導体素子を収容する空所を
形成するための凹部を有し、上面に封止用のガラス層か
被着された絶縁基体と、同じく電気絶縁材料から成り、
中央部に半導体素子を収容する空所を形成するための凹
部を有し、下面に封止用のガラス層か被着された蓋体と
、内部に収容する半導体素子を外部の電気回路に電気的
に接続するための外部リード端子とにより構成されてお
り、絶縁基体の上面に外部リード端子を載置させるとと
もに予め被着させておいた封止用のガラス層を溶融させ
ることによって外部リード端子を絶縁基体に仮止めし、
次に前記絶縁基体の凹部に半導体素子を取着するととも
に該半導体素子の各電極(信号電極、電源電極、接地電
極等)をボンディングワイヤを介して外部リード端子に
接続し、しかる後、絶縁基体と蓋体とをその相対向する
主面に被着させておいた封止用のガラス層を溶融一体化
させ、絶縁基体と蓋体とから成る容器を気密に封止する
ことによって最終製品としての半導体装置となる。
(Prior art and its problems) Conventionally, packages for accommodating semiconductor elements, especially glass-sealed packages for accommodating semiconductor elements that are sealed by glass welding, are made of electrically insulating materials such as alumina ceramics, and have a central part. It has a recess for forming a cavity for accommodating the semiconductor element, and is also made of an electrically insulating material, and has an insulating base on which a glass layer for sealing is applied on the upper surface,
It has a concave part in the center to form a cavity for accommodating the semiconductor element, a lid body with a sealing glass layer adhered to the bottom surface, and a lid body that connects the semiconductor element housed inside to an external electric circuit. The external lead terminal is made by placing the external lead terminal on the top surface of the insulating base and melting the glass layer for sealing that has been applied in advance. Temporarily fix it to the insulating base,
Next, a semiconductor element is attached to the recessed part of the insulating base, and each electrode (signal electrode, power supply electrode, ground electrode, etc.) of the semiconductor element is connected to an external lead terminal via a bonding wire. By melting and integrating the sealing glass layer that has been applied to the opposite main surfaces of the insulating base and the lid, the container consisting of the insulating base and the lid is hermetically sealed, resulting in a final product. semiconductor device.

尚、かかる従来の半導体素子収納用パッケージは内部に
収容する半導体素子か供給電源電圧の変動の影響を受け
ないようにするために通常、容量素子か付加されており
、該半導体素子収納用パッケージへの容量素子の付加は
一般に容器を構成する絶縁基体内部に多層電極を配し、
多層電極間(ゴ絶縁基体材料を誘電体として一定の静電
容量を形成したり、絶縁基体の半導体素子を収容する凹
部底面にチタン酸バリウム磁器からなる容量素子を取着
したりすることによって行われている。
In addition, in order to prevent the semiconductor elements housed inside from being affected by fluctuations in the supply voltage, such conventional semiconductor element storage packages usually have a capacitive element added to them. The addition of a capacitive element is generally done by arranging a multilayer electrode inside the insulating base that constitutes the container.
This is done by forming a constant capacitance between multilayer electrodes (by using an insulating base material as a dielectric material, or by attaching a capacitive element made of barium titanate porcelain to the bottom of a recess that accommodates a semiconductor element in an insulating base). It is being said.

しかしながら、この従来の半導体素子収納用パッケージ
においては容量素子の付加が容器を構成する絶縁基体の
内部に多層電極を配することによって行われている場合
、絶縁基体は一般にアルミナセラミックスから成り、該
アルミナセラミックスは誘電率が低い(誘電率9〜10
)ことから多層電極間に形成される静電容量も極めて小
さいものとなり、その結果、半導体素子の電源電圧変動
に起因する誤動作を完全に防止することかできないとい
う欠点を有していた。
However, in this conventional semiconductor device storage package, when the capacitive element is added by arranging a multilayer electrode inside the insulating base that constitutes the container, the insulating base is generally made of alumina ceramics, and the alumina Ceramics have a low dielectric constant (dielectric constant 9-10
) Therefore, the capacitance formed between the multilayer electrodes is also extremely small, and as a result, there is a drawback that malfunctions caused by fluctuations in the power supply voltage of semiconductor devices cannot be completely prevented.

尚、この欠点を解消するために多層電極の層数や電極対
向面積を増大させ、多層電極間に形成される静電容量を
大きくすることも考えられるか、電極の暦数や面積を増
大させるとパッケージ自体の形状か大きく成り、内部に
半導体素子を収容し、半導体装置とすると該半導体装置
か極めて大型のものとなる欠点を誘発する。
In addition, in order to eliminate this drawback, it may be possible to increase the number of layers of the multilayer electrode or the area where the electrodes face each other, increasing the capacitance formed between the multilayer electrodes, or increasing the number of electrodes or the area of the electrodes. This increases the size of the package itself, and when a semiconductor element is housed inside to form a semiconductor device, the semiconductor device becomes extremely large.

また絶縁基体の半導体素子を収容する凹部内にチタン酸
バリウム磁器から成る容量素子を取着することによって
半導体素子収納用パッケージに容量素子を付加した場合
、絶縁基体の半導体素子を収容する凹部かチタン酸バリ
ウム磁器から成る容量素子を取着するために大きくなり
、その結果、上述と同様、製品としての半導体装置か大
型化してしまうという欠点を有する。
Furthermore, when a capacitive element is added to a semiconductor element storage package by attaching a capacitive element made of barium titanate porcelain in the recess that accommodates the semiconductor element in the insulating base, the recess that accommodates the semiconductor element in the insulating base may be made of titanium porcelain. The size is increased due to the attachment of the capacitive element made of barium oxide porcelain, and as a result, as mentioned above, the semiconductor device as a product becomes large.

更に前記絶縁基体の外観形状をそのままとし、半導体素
子を収容する凹部のみの形状を容量素子か取着し得る程
度に大きくすることも考えられるが凹部の形状のみを大
きくすると絶縁基体と蓋体とを接合させ容器の内部を気
密封止する際、絶縁基体と蓋体との接合面積か狭くなっ
て容器の気密封止の信頼性か大きく低下するという欠点
を誘発してしまう。
Furthermore, it is conceivable to leave the external shape of the insulating base as is and make only the shape of the recess that accommodates the semiconductor element large enough to accommodate a capacitive element, but if only the shape of the recess is enlarged, the insulating base and the lid will be separated. When the inside of the container is hermetically sealed by joining them, the bonding area between the insulating base and the lid becomes narrow, resulting in a drawback that the reliability of hermetically sealing the container is greatly reduced.

(発明の目的) 本発明は上記欠点に鑑み案出されたちのて、その目的は
内部に収容する半導体素子を長期間にわたり誤動作する
ことなく安定に作動させることができる小型の半導体素
子収納用パッケージを提供することにある。
(Object of the Invention) The present invention was devised in view of the above-mentioned drawbacks, and its object is to provide a small package for storing semiconductor elements that can stably operate the semiconductor elements housed inside for a long period of time without malfunctioning. Our goal is to provide the following.

(課題を解決するための手段) 本発明は半導体素子を収容するための凹部を有する絶縁
基体と蓋体とから成る半導体素子収納用パッケージにお
いて、前記絶縁基体はその上面にメタライズ金属層を有
するとともに該メタライズ金属層上に外部リード端子か
酸化鉛60.0乃至90.0重量%、酸化ホウ素5.0
乃至15.0重量%に、フィラーとしてのペロブスカイ
ト型チタン酸塩を5.0乃至50.0重量%含有させて
成るガラス部材を介し固定されるとともに該外部リード
端子のうち半導体素子の電源電極もしくは接地電極と接
続される端子か前記メタライズ金属層に電気的に接続さ
れていることを特徴とするものである。
(Means for Solving the Problems) The present invention provides a semiconductor element storage package comprising an insulating base having a recess for accommodating a semiconductor element, and a lid, wherein the insulating base has a metallized metal layer on its upper surface. On the metallized metal layer, external lead terminals are coated with 60.0 to 90.0% by weight of lead oxide and 5.0% by weight of boron oxide.
15.0% by weight and 5.0% to 50.0% by weight of perovskite titanate as a filler. A terminal connected to a ground electrode is electrically connected to the metallized metal layer.

(実施例) 次に本発明を添付図面に示す実施例に基づき詳細に説明
する。
(Example) Next, the present invention will be described in detail based on an example shown in the accompanying drawings.

第1図は本発明の半導体素子収納用パッケージの一実施
例を示す断面図であり、1はアルミナセラミックス等の
電気絶縁材料より成る絶縁基体、2は同じ(電気絶縁材
料より成る蓋体である。この絶縁基体lと蓋体2とによ
り半導体素子3を収容するための容器か構成される。
FIG. 1 is a cross-sectional view showing one embodiment of the package for storing semiconductor elements of the present invention, in which 1 is an insulating base made of an electrically insulating material such as alumina ceramics, and 2 is the same (a lid made of an electrically insulating material). The insulating base 1 and the lid 2 constitute a container for accommodating the semiconductor element 3.

前記絶縁基体1及び蓋体2にはそれぞれの中央部に半導
体素子3を収容する空所を形成するための凹部が設けて
あり、絶縁基体1の凹部1a底面には半導体素子3が接
着材を介し取着固定される。
The insulating base 1 and the lid 2 are each provided with a recess in the center thereof to form a cavity for accommodating the semiconductor element 3, and the semiconductor element 3 is placed on the bottom surface of the recess 1a of the insulating base 1 with an adhesive. It is attached and fixed through.

前記絶縁基体l及び蓋体2は従来周知のプレス成形法を
採用することよって形成され、例えば絶縁基体1及び蓋
体2かアルミナセラミックスから成る場合には第1図に
示すような絶縁基体lまたは蓋体2に対応した形状を有
するプレス型内にアルミナセラミックスの粉末を充填さ
せるとともに一定圧力を印加して成形し、しかる後、成
形品を約1500 ’Cの温度で焼成することによって
製作される。
The insulating base 1 and the lid 2 are formed by employing a conventionally well-known press molding method. For example, when the insulating base 1 and the lid 2 are made of alumina ceramics, the insulating base 1 or the lid 2 as shown in FIG. It is manufactured by filling a press mold having a shape corresponding to the lid body 2 with alumina ceramic powder, molding it by applying a constant pressure, and then firing the molded product at a temperature of about 1500'C. .

また前記絶縁基体1はその上面にメタライズ金属層4が
被着されており、更にメタライズ金属層4の上部には外
部リード端子5がガラス部材6を介して固定され、メタ
ライズ金属層4と外部リード端子5との間にガラス部材
6を誘電体材料とした容量素子Aが形成されている。こ
の容量素子Aは半導体素子3の電源電極と接地電極の間
に接続され、半導体素子3に供給電源電圧の変動に起因
した悪影響か及ぼさないように作用する。
Further, the insulating substrate 1 has a metallized metal layer 4 deposited on its upper surface, and an external lead terminal 5 is fixed to the upper part of the metallized metal layer 4 via a glass member 6. A capacitive element A using a glass member 6 as a dielectric material is formed between the terminal 5 and the terminal 5 . This capacitive element A is connected between the power supply electrode and the ground electrode of the semiconductor element 3, and acts to prevent the semiconductor element 3 from being adversely affected by fluctuations in the supply voltage.

前記絶縁基体lの上面に被着されるメタライズ金属層4
は金(Au)、銀−白金(Ag−Pt) 、銀−パラジ
ウム(Ag−Pd)等の金属材料から成り、金粉末等に
適当な存機溶剤、溶媒を添加混合して得た金属ペースト
を絶縁基体1の上面に従来周知のスクリーン印刷法を採
用することによって印刷塗布し、しかる後、これを約4
50°Cの温度で焼成し、金粉末等を絶縁基体lの上面
に焼き付けることによって被着される。
Metallized metal layer 4 deposited on the upper surface of the insulating substrate l
is made of metal materials such as gold (Au), silver-platinum (Ag-Pt), silver-palladium (Ag-Pd), etc., and is a metal paste obtained by adding and mixing a suitable organic solvent and solvent to gold powder etc. is applied by printing on the upper surface of the insulating substrate 1 by employing a conventionally well-known screen printing method, and then approximately 4
It is deposited by firing at a temperature of 50° C. and baking gold powder or the like onto the upper surface of the insulating substrate l.

前記メタライズ金属層4は半導体素子3に供給される電
源電圧の変動を平滑化して半導体素子3の誤動作を有効
に防止する容量素子Aの一方の電極として作用し、該メ
タライズ金属層4には半導体素子3の電源電極、或いは
接地電極か電気的に接続される。
The metallized metal layer 4 acts as one electrode of the capacitive element A that smoothes fluctuations in the power supply voltage supplied to the semiconductor element 3 and effectively prevents malfunctions of the semiconductor element 3. The power supply electrode or the ground electrode of the element 3 is electrically connected.

前記メタライズ金属層4が被着された絶縁基体lの上部
にはまた外部リード端子5かガラス部材6を介して固定
されており、該ガラス部材6は絶縁基体1上に外部リー
ド端子5を固定するとともに容量素子Aの誘電体材料と
して作用する。
An external lead terminal 5 is also fixed to the upper part of the insulating base l on which the metallized metal layer 4 is adhered via a glass member 6, and the glass member 6 fixes the external lead terminal 5 on the insulating base 1. At the same time, it acts as a dielectric material of the capacitive element A.

前記ガラス部材6は酸化鉛60.0乃至90.0重量%
、酸化ホウ素5.0乃至15.0重量%に、フィラーと
してのペロブスカイト型チタン酸塩を5.0乃至50.
0重量%含有するガラスから成り、該ガラスの誘電率は
35.0(室温IMHz)と高い。
The glass member 6 contains 60.0 to 90.0% by weight of lead oxide.
, 5.0 to 15.0% by weight of boron oxide, and 5.0 to 50% of perovskite titanate as a filler.
It is made of glass containing 0% by weight, and the dielectric constant of the glass is as high as 35.0 (room temperature IMHz).

前記ガラス部材6はその誘電率か35.0と極めて高い
ことからメタライズ金属層4と外部リード端子6との間
に形成される容量素子Aの静電容量値か極めて大きな値
となり、その結果、容量素子Aによって供給電源電圧の
変動に起因する半導体素子への悪影響を有効に防止する
ことかでき、内部に収容する半導体素子を誤動作させる
ことなく安定に作動させることができる。
Since the glass member 6 has an extremely high dielectric constant of 35.0, the capacitance value of the capacitive element A formed between the metallized metal layer 4 and the external lead terminal 6 is extremely large, and as a result, The capacitive element A can effectively prevent adverse effects on the semiconductor element due to fluctuations in the supply voltage, and the semiconductor element housed inside can operate stably without malfunctioning.

尚、前記ガラス部材6は酸化鉛の含有量か60.0重量
%未満であるとガラス部材6の加熱溶融温度が高くなり
、絶縁基体1にガラス部材6を被着、また絶縁基体1に
外部リード端子5をガラス部材6を介し固定する作業性
か悪いものとなり、また90.0重量%を越えるとガラ
ス部材6の熱膨張係数か絶縁基体lと合わなくなりガラ
ス部材6を絶縁基体1に強固に被着させることか困難と
なってしまう。従って、酸化鉛の含有量は60.0乃至
90.0重量%の範囲に特定される。
Note that if the content of lead oxide in the glass member 6 is less than 60.0% by weight, the heating and melting temperature of the glass member 6 will be high, and the glass member 6 will be attached to the insulating base 1, and the insulating base 1 will not be exposed to the outside. The workability of fixing the lead terminal 5 through the glass member 6 will be poor, and if it exceeds 90.0% by weight, the coefficient of thermal expansion of the glass member 6 will not match the insulating base l, and the glass member 6 will be firmly attached to the insulating base 1. It becomes difficult to coat the surface. Therefore, the content of lead oxide is specified in the range of 60.0 to 90.0% by weight.

また酸化ホウ素の含有量は5.0重量%未満であるとガ
ラス部材6のガラス化か困難となり、外部リード端子5
を絶縁基体l上に強固に固定することか不可となり、ま
た15.0重量%を越えるとガラス部材6の加熱溶融温
度か高くなり、絶縁基体1にガラス部材6を被着、また
絶縁基体lに外部リード端子5をガラス部材6を介し固
定する作業性か悪いものとなってしまう。従って、酸化
ホウ素の含有量は5.0乃至15.0重量%の範囲に特
定される。
Further, if the content of boron oxide is less than 5.0% by weight, it becomes difficult to vitrify the glass member 6, and the external lead terminal 5
If it exceeds 15.0% by weight, the heating and melting temperature of the glass member 6 will become high, and the glass member 6 will not adhere to the insulating base 1, and the insulating base l However, the workability of fixing the external lead terminal 5 through the glass member 6 becomes poor. Therefore, the content of boron oxide is specified in the range of 5.0 to 15.0% by weight.

更にフィラーとして含育されるペロブスカイト型のチタ
ン酸塩は例えば、ジルコンやチタン酸鉛か使用され、そ
の含有量が5.0重量%未満であるとガラス部材6の誘
電率か低くなり、外部リード端子5とメタライズ金属層
4との間に大きな静電容量値の容量素子Aを形成するこ
とができなくなり、また50.0重量%を越えるとガラ
ス部材6の熱膨張係数が絶縁基体1と合わなくなりガラ
ス部材6を絶縁基体lに強固に被着させることか困難と
なってしまう。従って、ペロブスカイト型のチタン酸塩
の含育量は5.0乃至50,0重量%の範囲に特定され
る。
Furthermore, the perovskite type titanate contained as a filler, for example, zircon or lead titanate, is used, and if the content is less than 5.0% by weight, the dielectric constant of the glass member 6 will be low, and the external lead It becomes impossible to form a capacitive element A with a large capacitance value between the terminal 5 and the metallized metal layer 4, and if it exceeds 50.0% by weight, the thermal expansion coefficient of the glass member 6 will match that of the insulating base 1. This makes it difficult to firmly adhere the glass member 6 to the insulating substrate l. Therefore, the content of perovskite titanate is specified to be in the range of 5.0 to 50.0% by weight.

前記ガラス部材6は酸化鉛、酸化ホウ素、酸化チタン、
酸化ジルコニウムの粉末に適当な有機溶剤、溶媒を添加
混合して得たガラスペーストを絶縁基体lの上面に従来
周知のスクリーン印刷法により印刷塗布し、しかる後、
これを約500°Cの温度で焼き付けることによって絶
縁基体lの上面に被着される。
The glass member 6 is made of lead oxide, boron oxide, titanium oxide,
A glass paste obtained by adding and mixing a suitable organic solvent and a solvent to zirconium oxide powder is printed and coated on the upper surface of the insulating substrate l by a conventionally well-known screen printing method, and then,
By baking this at a temperature of about 500°C, it is applied to the upper surface of the insulating substrate l.

前記ガラス部材6はその厚みが0.05mm未満である
と絶縁基体1に外部リード端子5を強固に固定できなく
なる危険性があり、また0、5mmを越えると外部リー
ド端子5とメタライズ金属層4との間に形成される容量
素子Aの静電容量値か小さな値となって半導体素子3へ
の電源電圧変動の影響を有効に防止できなくなる危険性
がある。従って、前記ガラス部材6はその厚みを0.0
5乃至0.5mmの範囲としておくことか好ましい。
If the thickness of the glass member 6 is less than 0.05 mm, there is a risk that the external lead terminal 5 cannot be firmly fixed to the insulating base 1, and if the thickness exceeds 0.5 mm, the external lead terminal 5 and the metallized metal layer 4 may be damaged. There is a risk that the electrostatic capacitance value of the capacitive element A formed between the capacitive element A and the capacitive element A becomes small, and the influence of power supply voltage fluctuations on the semiconductor element 3 cannot be effectively prevented. Therefore, the thickness of the glass member 6 is 0.0
It is preferable to keep the thickness in the range of 5 to 0.5 mm.

また前記ガラス部材6を介して絶縁基体1の上部に固定
される外部リード端子5は例えば、コバール金属(Fe
−Ni−Co合金)や42Alloy(Fe−Ni合金
)等の金属から成り、該コバール金属等のインゴット(
塊)を従来周知の圧延加工法及び打ち抜き加工法を採用
することによって所定の板状に形成される。
Further, the external lead terminal 5 fixed to the upper part of the insulating base 1 via the glass member 6 is made of, for example, Kovar metal (Fe).
-Ni-Co alloy) and 42Alloy (Fe-Ni alloy), etc., and the Kovar metal ingot (
The block is formed into a predetermined plate shape by employing conventionally known rolling and punching methods.

前記外部リード端子5は内部に収容する半導体素子3の
信号電極、電源電極及び接地電極を外部電気回路に接続
する作用を為し、その一端には半導体素子3の各電極か
ボンディングワイヤ7を介して接続され、外部リード端
子5を外部電気回路に接続することによって半導体素子
3は外部電気回路と接続されることとなる。
The external lead terminal 5 functions to connect the signal electrode, power supply electrode, and ground electrode of the semiconductor element 3 housed inside to an external electric circuit, and has one end connected to each electrode of the semiconductor element 3 via a bonding wire 7. By connecting the external lead terminals 5 to the external electrical circuit, the semiconductor element 3 is connected to the external electrical circuit.

尚、前記外部リード端子5はその外表面にニッケル、金
等から成る良導電性で、且つ耐蝕性に優れた金属をメツ
キにより2.0乃至20.0μmの厚みに層着させてお
くと外部リード端子5の酸化腐食を有効に防止するとと
もに外部リード端子5と外部電気回路との電気的接続を
良好となすことかできる。そのため外部リード端子5は
その外表面にニッケル、金等をメツキにより2.0乃至
20,0μmの厚みに層着させておくことか好ましい。
Note that the external lead terminal 5 may be coated with a layer of a highly conductive and corrosion-resistant metal such as nickel or gold to a thickness of 2.0 to 20.0 μm on its outer surface. Oxidation corrosion of the lead terminals 5 can be effectively prevented, and electrical connection between the external lead terminals 5 and an external electric circuit can be made good. Therefore, it is preferable that the outer surface of the external lead terminal 5 is coated with nickel, gold, etc. to a thickness of 2.0 to 20.0 μm.

また前記外部リード端子5は半導体素子3に供給される
電源電圧の変動を平滑化して半導体素子3の誤動作を有
効に防止する容量素子Aの一方の電極としても作用し、
該外部リード端子5のうち半導体素子3の電源電極ある
いは接地電極か接続される端子5aはボンディングワイ
ヤ7aを介して絶縁基体1の上面に被着させたメタライ
ズ金属層4に電気的に接続され、これによって外部リー
ド端子5とメタライズ金属層4との間に形成される容量
素子Aは半導体素子3の電源電極と接地電極の間に電気
的に接続されることとなる。
The external lead terminal 5 also acts as one electrode of a capacitive element A that smoothes fluctuations in the power supply voltage supplied to the semiconductor element 3 and effectively prevents malfunction of the semiconductor element 3.
Among the external lead terminals 5, a terminal 5a connected to the power supply electrode or the ground electrode of the semiconductor element 3 is electrically connected to the metallized metal layer 4 deposited on the upper surface of the insulating substrate 1 via a bonding wire 7a, Thereby, the capacitive element A formed between the external lead terminal 5 and the metallized metal layer 4 is electrically connected between the power supply electrode and the ground electrode of the semiconductor element 3.

前記半導体素子3の電源電極と接地電極との間に接続さ
れる容量素子Aは、メタライズ金属層4を被着させた絶
縁基体lの上部に外部リード端子5を高誘電率のガラス
部材6を介し固定することによって形成されることから
絶縁基体1の半導体素子3を取着する凹部1aの大きさ
を容量素子Aを取着するために特別大きくする必要は一
切ない。
The capacitive element A connected between the power supply electrode and the ground electrode of the semiconductor element 3 includes an external lead terminal 5 and a glass member 6 having a high dielectric constant on the top of an insulating base l on which a metallized metal layer 4 is deposited. Since the recess 1a of the insulating substrate 1 to which the semiconductor element 3 is attached does not have to be particularly large in size to accommodate the capacitive element A, since it is formed by fixing the semiconductor element 3 through the insulating substrate 1.

そのため後述する絶縁基体1と蓋体2とを接合させ容器
を気密封止することによって半導体装置となす際、絶縁
基体1と蓋体2とはその外観形状を大きくすることなく
両者の接合面積を広くなすことかでき、その結果、容器
の気密封止の信頼性を高いものとして、且つ半導体装置
の形状も小型となすことかできる。
Therefore, when forming a semiconductor device by bonding the insulating base 1 and the lid 2 and hermetically sealing the container, which will be described later, the insulating base 1 and the lid 2 can reduce the bonding area between them without increasing their external shape. As a result, the hermetic sealing of the container can be made highly reliable, and the shape of the semiconductor device can also be made smaller.

また前記半導体素子3の電源電極と接地電極との間に接
続される容量素子Aはその静電容量値か大きいため供給
電源電圧の変動に起因する半導体素子3への影響を有効
に防止することもてき、これによって半導体素子3は供
給電源電圧の変動に左右されることなく安定に作動する
二とか可能となる。
Further, since the capacitive element A connected between the power supply electrode and the ground electrode of the semiconductor element 3 has a large capacitance value, it is possible to effectively prevent the influence on the semiconductor element 3 caused by fluctuations in the supply voltage. This allows the semiconductor element 3 to operate stably without being affected by fluctuations in the supply voltage.

前記外部リード端子5か固定された絶縁基体1はまたそ
の上面に蓋体2がガラス材6aを介して接合され、これ
ににって絶縁基体1と蓋体2とから成る容器内部に半導
体素子3か気密に封止される。
The insulating base 1 to which the external lead terminals 5 are fixed also has a lid 2 bonded to its upper surface via a glass material 6a, thereby allowing a semiconductor element to be placed inside the container consisting of the insulating base 1 and the lid 2. 3.Hermetically sealed.

前記蓋体2を絶縁基体1に接合させるガラス材6aは低
融点のガラス材料から成り、該ガラス材6aは予め蓋体
2の下面に被着されている。
The glass material 6a for joining the lid 2 to the insulating base 1 is made of a glass material with a low melting point, and the glass material 6a is previously attached to the lower surface of the lid 2.

尚、前記ガラス材6aは酸化鉛50.0乃至80.0重
量%、酸化ホウ素5.0乃至15.0重量%、酸化亜鉛
15.0重量%以下、酸化ケイ素1O00重量%以下、
酸化アルミニウム10.0重量%以下を含むガラスから
成り、該各ガラス原料粉末に適当な有機溶剤、溶媒を添
加混合して得たガラスペーストを蓋体2の下面に従来周
知のスクリーン印刷法により印刷塗布するとともにこれ
を約400°Cの温度で焼成することによって蓋体2下
面に被着される。
The glass material 6a contains 50.0 to 80.0% by weight of lead oxide, 5.0 to 15.0% by weight of boron oxide, 15.0% by weight or less of zinc oxide, 100% by weight or less of silicon oxide,
A glass paste made of glass containing 10.0% by weight or less of aluminum oxide and obtained by adding and mixing an appropriate organic solvent or solvent to each of the glass raw material powders is printed on the lower surface of the lid body 2 by a conventionally well-known screen printing method. It is coated on the lower surface of the lid body 2 by coating and baking it at a temperature of about 400°C.

かくしてこの半導体素子収納用パッケージによれば絶縁
本体1の凹部1a底面に半導体素子3を取着するととも
に該半導体素子3の各電極をボンディングワイヤ7によ
り外部リード端子4に接続させるとともに半導体素子3
の電源電極、或いは接地電極が接続される外部リード端
子5aをボンディングワイヤ7aを介して絶縁基体1の
上面に被着させたメタライズ金属層4に接続させ、しか
る後、絶縁基体lと蓋体2とを蓋体2の下面に予め被着
させておいたガラス材6aを加熱溶融させ、接合させる
ことによって内部に半導体素子3を気密封止し、これに
よって最終製品としての半導体装置か完成する。
Thus, according to this semiconductor element storage package, the semiconductor element 3 is attached to the bottom surface of the recess 1a of the insulating body 1, and each electrode of the semiconductor element 3 is connected to the external lead terminal 4 by the bonding wire 7.
The external lead terminal 5a to which the power supply electrode or the ground electrode is connected is connected to the metallized metal layer 4 deposited on the upper surface of the insulating base 1 via the bonding wire 7a, and then the insulating base 1 and the lid 2 are connected to each other. By heating and melting the glass material 6a previously attached to the lower surface of the lid body 2 and joining them, the semiconductor element 3 is hermetically sealed inside, thereby completing the semiconductor device as a final product.

(発明の効果) 以上の通り、本発明の半導体素子収納用パッケージによ
れば、絶縁基体の上面にメタライズ金属層を被着し、更
にその上部に外部リード端子を誘電率か35.0である
酸化鉛60.0乃至90.0重量%、酸化ホウ素5.0
乃至15.0重量%に、フィラーとしてのペロブスカイ
ト型チタン酸塩を5.0乃至50.0重量%含有させて
成るガラス部材を介して固定するとともに該外部リード
端子のうち半導体素子の電源電極もしくは接地電極が接
続される端子を前記メタライズ金属層に電気的に接続し
たことからメタライズ金属層と外部リード端子との間に
大きな静電容量を有した容量素子を形成することがてき
、その結果、前記容量素子によって供給電源電圧の変動
に起因する半導体素子への悪影響を存効に防止し、半導
体素子を長期間にわたり正常、且つ安定に作動させこと
か可能となる。
(Effects of the Invention) As described above, according to the semiconductor element storage package of the present invention, a metallized metal layer is deposited on the upper surface of an insulating base, and an external lead terminal is further provided on the upper surface with a dielectric constant of 35.0. Lead oxide 60.0 to 90.0% by weight, boron oxide 5.0
to 15.0% by weight and a glass member containing 5.0 to 50.0% by weight of perovskite titanate as a filler. Since the terminal to which the ground electrode is connected is electrically connected to the metallized metal layer, a capacitive element having a large capacitance can be formed between the metallized metal layer and the external lead terminal, and as a result, The capacitive element effectively prevents adverse effects on the semiconductor element due to fluctuations in the supply voltage, and allows the semiconductor element to operate normally and stably for a long period of time.

また前記容量素子はメタライズ金属層を被着させた絶縁
基体の上部に外部リード端子を誘電率か35.0のガラ
ス部材を介し固定することによって形成されることから
絶縁基体の半導体素子を取着する凹部の大きさを容量素
子を取着するために特別大きくする必要は一切ない。そ
のため絶縁基体と蓋体とを接合させ容器を気密封止する
ことによって半導体装置となす際、絶縁基体と蓋体とは
その外観形状を大きくすることなく両者の接合面積を広
くなすことができ、その結果、容器の気密封止の信頼性
を高いものとして、且つ半導体装置も小型となすことが
できる。
Furthermore, since the capacitive element is formed by fixing an external lead terminal to the upper part of an insulating base covered with a metallized metal layer via a glass member having a dielectric constant of 35.0, the semiconductor element on the insulating base is attached. There is no need to make the size of the recess particularly large in order to attach the capacitive element. Therefore, when forming a semiconductor device by bonding the insulating base and the lid and hermetically sealing the container, the bonding area between the insulating base and the lid can be increased without increasing the external shape. As a result, the reliability of the hermetic sealing of the container can be made high, and the semiconductor device can also be made smaller.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。 l・・・絶縁基体  2・・・蓋体 4・・・メタライズ金属層 5・・・外部リード端子 6・・・ガラス部材 6a  ・・ガラス材
FIG. 1 is a cross-sectional view showing an embodiment of the semiconductor element storage package of the present invention. l...Insulating base 2...Lid 4...Metalized metal layer 5...External lead terminal 6...Glass member 6a...Glass material

Claims (1)

【特許請求の範囲】[Claims]  半導体素子を収容するための凹部を有する絶縁基体と
蓋体とから成る半導体素子収納用パッケージにおいて、
前記絶縁基体はその上面にメタライズ金属層が被着され
、且つその上部に外部リード端子が酸化鉛60.0乃至
90.0重量%、酸化ホウ素5.0乃至15.0重量%
に、フィラーとしてのペロブスカイト型チタン酸塩を5
.0乃至50.0重量%含有させて成るガラス部材を介
し固定されるとともに該外部リード端子のうち半導体素
子の電源電極もしくは接地電極と接続される端子が前記
メタライズ金属層に電気的に接続されていることを特徴
とする半導体素子収納用パッケージ。
A semiconductor device storage package comprising an insulating base having a recess for accommodating a semiconductor device and a lid,
A metallized metal layer is deposited on the upper surface of the insulating substrate, and external lead terminals are formed on the upper surface of the insulating substrate by 60.0 to 90.0% by weight of lead oxide and 5.0 to 15.0% by weight of boron oxide.
In addition, perovskite titanate as a filler was added to
.. The metallized metal layer is fixed through a glass member containing 0 to 50.0% by weight, and a terminal of the external lead terminal that is connected to a power supply electrode or a ground electrode of the semiconductor element is electrically connected to the metallized metal layer. A semiconductor device storage package characterized by:
JP33282390A 1990-11-28 1990-11-28 Package for storing semiconductor elements Expired - Fee Related JP2808044B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33282390A JP2808044B2 (en) 1990-11-28 1990-11-28 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33282390A JP2808044B2 (en) 1990-11-28 1990-11-28 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH04196566A true JPH04196566A (en) 1992-07-16
JP2808044B2 JP2808044B2 (en) 1998-10-08

Family

ID=18259203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33282390A Expired - Fee Related JP2808044B2 (en) 1990-11-28 1990-11-28 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP2808044B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11163185A (en) * 1997-11-28 1999-06-18 Kyocera Corp High-frequency semiconductor device package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11163185A (en) * 1997-11-28 1999-06-18 Kyocera Corp High-frequency semiconductor device package

Also Published As

Publication number Publication date
JP2808044B2 (en) 1998-10-08

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