JPH0419579B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides a trace circuit that traces bus information of a CPU equipped with a queue buffer and queue information output by the CPU, which summarizes queue information for each bus cycle. The present invention relates to a trace circuit that uses a plurality of bits of queue change information to trace the queue change information and bus information for each bus cycle.

(Prior Art) Conventionally, a circuit shown in FIG. 3 has been used as a trace circuit for a CPU equipped with a queue buffer. That is, in FIG. 3, 1 is a trace circuit, and 2 is a CPU equipped with a queue buffer. The trace circuit 1 that traces the bus contents, bus control information, and queue information output by the CPU 2 includes a bus trace timing detection circuit 3,
It consists of a queue information trace timing detection circuit 4, a trace clock/frame information generation circuit 5, and a storage circuit 6. The bus trace timing detection circuit 3 is connected to the bus control information of the CPU 2, and creates the trace timing of a bus cycle consisting of a plurality of clocks. The queue information trace timing detection circuit 4 is connected with the queue information of the CPU 2 which changes every clock, and creates the trace timing of the queue information. The trace clock/frame information generation circuit 5 receives the bus cycle trace timing signal output from the bus trace timing detection circuit 3 and the queue information trace timing detection circuit 4.
The trace clock is output from both the queue information trace timing signal output from the queue information trace timing signal output from the queue information trace timing signal outputted from the queue information trace timing signal, and at the same time, frame information for distinguishing whether the clock is a bus trace timing or a queue information trace timing is outputted. The memory circuit 6 traces the bus contents, bus control information, queue information, and frame information output by the CPU 2 while updating the address of the memory circuit 6 every trace clock.

(Problems to be Solved by the Invention) However, the conventional trace circuit 1 operates the memory circuit 6 for each trace clock.
As shown in FIG. 4, cue information such as A, B, C, D, etc. may be generated continuously for each CPU clock, so the memory circuit 6 and the control circuit section of the memory circuit 6 may requires high-speed operation, and has the disadvantage that tracing must be completed with one CPU clock. Furthermore, even at the timing of tracing queue information, bus information and bus control information that do not originally need to be traced are also traced, resulting in a disadvantage that the storage circuit 6 is not used efficiently.

The present invention aims to solve the above-mentioned drawbacks, and uses a series of queue information generated from a certain predetermined singular point of a bus cycle to the singular point of the next bus cycle as queue change information. By capturing this queue change information as a pattern and converting it into a multi-bit code, and tracing the converted code captured as the queue change information between the singular points to a storage circuit, high-speed operation of the trace circuit is achieved. It is an object of the present invention to provide a trace circuit that can operate at a low speed and improve the usage efficiency of the memory circuit.

(Means for Solving the Problem) Therefore, the trace circuit of the present invention has a characteristic transition state that appears only once in every bus cycle in a trace circuit that traces queue change information of a CPU equipped with a queue buffer. A detection circuit that detects a singular point indicating a singularity of the bus cycle, and a detection circuit that expresses information on changes in queues that occur from a singular point of one bus cycle to a singular point of the next bus cycle in a multi-bit signal, and uses this signal to detect a singularity of the bus cycle. The present invention is characterized in that it includes a cue information conversion circuit that outputs the output after the point, and a storage circuit that stores the output of the cue information conversion circuit.

An embodiment of the present invention will be described below with reference to the drawings.

(Embodiment) FIG. 1 shows the configuration of an embodiment of a trace circuit according to the present invention, and FIG. 2 shows its time chart.

In FIG. 1, 11 represents a trace circuit, 12 a detection circuit, 13 a queue information conversion circuit, 14 a storage circuit, and 15 a CPU.

The trace circuit 11 traces the operation process of the CPU 15, which is the object of tracing, and traces the information appearing on the bus connected to the CPU 15, that is, addresses and data, and the CPU 15.
The bus control information and queue information outputted by the controller are selectively stored in the storage circuit 14 as necessary. The CPU 1 that is being traced by the trace circuit 11
5 has a finite number of queue buffers inside it, and once the instruction code taken in from the bus via a ROM (not shown) is input into the queue buffer, the contents of the queue buffer are stored asynchronously with the bus cycle of the CPU 15. are executed sequentially. The CPU 15 outputs queue information to indicate the process by which the contents of the queue buffer are executed.

On the other hand, the detection circuit 12 constantly monitors the bus control information output from the CPU 15, and detects a singular point that always occurs during every bus cycle of the CPU 15 and occurs only once.
Singular points in this bus cycle include, for example, the rising edge of a control signal indicating that the address appearing on the bus is valid, the falling edge of a control signal indicating that the address appearing on the bus is invalid, Alternatively, there is a signal output point at which the read signal and the write signal are ORed. By the detection circuit 12 detecting this singular point,
One bus cycle consists of multiple clocks.
It can be divided into sections.

FIG. 2 shows a time chart when the rise point of the control signal (address valid signal) indicating that the address appearing in the bus cycle becomes invalid is selected as this singular point, and the detection circuit 12 outputs its detection signal at the clock at the end of each bus cycle. From now on, this detection signal will be referred to as a timing signal.

The queue information conversion circuit 13 divides queue depth information, which will be described later, and queue information output from the CPU 15 using a timing signal output from the detection circuit 12, and divides the queue depth information and the queue information output from the CPU 15 into sections within one section divided by the timing signal. At least one of the cue information, the order of the cue information, and the cue depth information is taken as a pattern that can be easily guessed, and this pattern is encoded with a plurality of bits and output as cue change information. Here, the queue depth information is within the queue buffer of the CPU 15,
This refers to the number of instruction codes to be executed, and refers to information on the number of queue buffers currently in use obtained from queue information and bus control information.

The storage circuit 14 is a circuit that stores the queue change information for one section obtained by the queue information conversion circuit 13 and other bus information for each timing signal that separates one section. Then, the memory circuit 14 stores the cue change information, etc. using the next faster clock of one section, which is composed of a plurality of clocks.

Next, the operation of one embodiment of the present invention will be explained with reference to the time chart shown in FIG.

As explained in FIG. 1, the detection circuit 12 detects the peculiarity of the bus cycle from the bus control information, and in the above example, the singular point is the rising edge of the address valid signal at which the address appearing on the bus becomes invalid. Detected. Therefore, the detection circuit 12
A timing signal is output at each falling edge of the 1st clock, the 6th clock, and the 12th clock. By this timing signal, a bus cycle composed of a plurality of clocks is divided into one section, such as bus cycle 1 and bus cycle 2.

The CPU 15 outputs queue information for each clock, but since the trace circuit 11 traces the execution process of the CPU 15 that occurs in a bus cycle, the queue information output by the CPU 15 in a bus cycle divided as bus cycle 1 are now A, B, C, D, and the queue information output by the CPU 15 in the bus cycle divided as bus cycle 2 is B, C, A,
Let it be C. The queue information conversion circuit 13 converts series queue information A, B, C, D regarding the bus cycle sent within the divided bus cycle 1.
is regarded as one pattern, that is, “A,
The pattern "B, C, D" (including the order of A, B, C, D) is encoded with multiple bits as cue change information, and the cue change information "A, B, C, D" is encoded as cue change information. The code is stored in the storage circuit 14. Similarly, delimited bus cycle 2
The queue information B, C, A, C of the series about the bussail sent within is the pattern "B,
C, A, C", that is, "B, C, A, C", and this converted code is stored in the storage circuit 14.

The code converted into cue change information by the cue information conversion circuit 13 may be stored in the storage circuit 14 before the code converted to the next cue conversion information is generated in the cue information conversion circuit 13. Therefore, the high speed performance of the memory circuit 14 is relaxed. In other words, low-speed operation is possible.

In the CPU 15 having an internal queue buffer, the queue depth of the queue buffer, that is, the number of valid data stored in the queue buffer, is processed by the queue information conversion circuit 13 as follows. That is, the queue information conversion circuit 13 is prepared with a number of bit strings (using registers, etc., for example) corresponding to the number of storage stages of the queue buffer.
In addition, each storage stage of the queue buffer is in one-to-one correspondence with the above-mentioned bit string.

Then, at each final clock of bus cycle 1 and bus cycle 2 shown in FIG. 2, the contents of the bit string in the queue information conversion circuit 13 are transferred to the storage circuit 14 and stored therein.

In the above explanation, queue change information and queue depth were explained separately, but these are simultaneously processed in the queue information conversion circuit 13, that is, queue change information and queue depth, respectively, in separated bus cycles 1 and 2. depth information is stored in the storage circuit 14 as one piece of data. As is clear from this, since one piece of data is stored for each divided bus cycle, the storage circuit 14 is effectively used.

(Effects of the Invention) As explained above, according to the present invention, the queue change information and the queue depth are traced as one data that is divided at the singular point of the bus cycle and summarized for each bus cycle. The high-speed operation of the trace circuit can be reduced to a low-speed operation, and the usage efficiency of the memory circuit can be improved.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of the trace circuit according to the present invention, FIG. 2 shows its time chart, FIG. 3 shows an example of the configuration of a conventional trace circuit, and FIG. 4 shows its time chart. In the figure, 11 is a trace circuit, 12 is a detection circuit,
13 is a cue information conversion circuit, 14 is a storage circuit, 1
5 is a CPU.

Claims (1)

[Claims] 1. A detection circuit 12 that detects a singular point indicating a characteristic transition state that appears only once in every bus cycle in a trace circuit that traces queue change information of a CPU equipped with a queue buffer. and a queue information conversion circuit that expresses information on queue changes occurring from the singular point of one bus cycle to the singular point of the next bus cycle in a multi-bit signal, and outputs this signal after the singular point of the bus cycle. 13; and a storage circuit 14 for storing the output of the queue information conversion circuit.