JP2005250951A - Data column shaping device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data shaping device capable of successively transmit a processing result as it has the received length every receipt of data of word units. <P>SOLUTION: A combination logic circuit 5, which is connected to an input register 1, an output register 2, a storage register 3, and a decoder 4, sorts data of a byte unit group of the input register 1 and a byte unit group of the storage register 3 to a byte group of the storage register 3 and a byte group of the output register 2 according to the state of the combination logic circuit 5 itself and an evaluation signal of byte unit, and transits the state of the combination logic circuit 5 itself. According to this, processing of an escape character, a back space character or the like is performed as word streaming processing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data shaping apparatus, and more particularly to an apparatus capable of transmitting processing results sequentially in the received length each time data is received for each processing unit (this unit is called a word).

  In the conventional data string shaping device, since the processing unit is a byte unit, the data received by the input unit is once converted to the byte unit processing (for example, Patent Document 1). When the conventional data shaping process is implemented, the data received in word units, which is the processing unit, is converted to byte units, the data shaping process is performed, and the conversion back to word units is performed again to perform the processing after the shaping process. Had to do. In the conventional method, the processing performance depends on the conversion part to the byte unit. Since the processing unit is switched in this portion, there is a problem that the operation clock must be changed in order to design with H / W. In addition, in order to perform reverse conversion to word units, it is necessary to prepare a buffer for storing the processed byte sequence.

  The data after the shaping process is generally used to search for a predetermined pattern from the arranged data string. Since the pattern search is also a byte unit process, a method of including the pattern search in the shaping process has also been proposed (for example, Patent Document 1 and Patent Document 2).

Although this method does not require reverse conversion to word units, it still includes a conversion part from word units to byte units. In addition, it is difficult to implement because different processes are implemented together. In addition, there is a problem that the function cannot be separated, such as leaving the pattern search using the shaped data to the dedicated H / W.
JP-A-6-259498 JP-A-6-259475

  The present invention has been made in order to avoid the above-described problems, and an object of the present invention is to be able to mount a high-speed and reusable data string shaping device by an easy mounting technique.

  When the conventional data shaping process is implemented, the data received in units of words that are processing units must be converted into units of bytes.

  Since the processing unit is switched, mounting with H / W requires a dramatically fast operating frequency in the processing unit in byte units, which makes mounting difficult.

  In order to avoid reverse conversion from the byte unit to the word unit, in the form in which different processes are packaged together, the different processes are performed together, which makes the implementation itself difficult.

  In a form in which different processes are implemented together, there is a problem that it is difficult to separate the processes, such as entrusting a dedicated H / W with any process performed using the shaped data.

  In a form in which different processes are implemented together, there is a problem that it is necessary to review the embodiment every time the content of the shaping process is changed because the design is specialized for a series of processes including the data shaping process.

  There is a problem that it is difficult to reuse a created module in a form in which different processes are implemented together.

The data string shaping device according to the present invention has the following elements: (1) an input register for inputting input data for external processing units in an internal processing unit group; and (2) an output for external processing units. Output register for outputting data in internal processing unit group (3) Temporary data in the middle of data string shaping process, saving register for saving in internal processing unit group (4) Specific code for each internal processing unit of input data Decoder that evaluates whether there is a decoder and decodes it into an evaluation signal for each internal processing unit (5) Connected to input register, output register, storage register, and decoder, and states of combinational logic circuit itself, and said internal processing In response to the unit evaluation signal, the data of the internal processing unit group of the input register and the internal processing unit group of the storage register are newly transferred to the internal processing unit group of the storage register and the output level. Sorting the data with the internal processing unit group of static combinational logic circuit for shifting the state of the combinational logic circuit itself.

  Each time data in word units is received, the processing results can be sequentially transmitted with the received length.

Embodiment 1 FIG.
Hereinafter, the present invention will be described based on embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

  In FIG. 1, one word is 32 bits (= 4 bytes). The input register 1 (InputREGISTER) is a register for receiving data for one word, and the output register 2 (OutputREGISTER) is a register for sequentially transmitting data after data string shaping processing in units of words. The storage register 3 (ReserveREGISTER) is a register having the same size as one word for storing data less than one word because it is in the middle of processing. The four decoders 4 (Decoders) are decoders 4 for evaluating each input data in units of bytes and decoding the signals from 8 bits to 1 bit signals (examples of evaluation signals). The combinational circuit 5 (Combined Logic) performs combination processing.

  Here, the word unit is an example of an external processing unit, and the byte unit is an example of an internal processing unit.

  The problem for designing a word streaming type data string shaping device is that a combinational circuit 5 capable of sequentially processing appropriate processes from the input register 1 to the output register 2 in one cycle with respect to the input clock can be created. It is a problem. This configuration makes it possible to create a combinational circuit 5 that solves this problem.

  Next, the operation will be described.

  Here, an embodiment of the escape character decoding process, which is the simplest data string shaping process, will be described.

  In the escape character decoding process, when the character '%' represented by 8 bits comes, the lower 4 bits of any two characters 'C1', 'C2', and 'C1' that follow are upper 4 The character string “% C1C2” is replaced with the character “C3” using the character “C3” in which the lower 4 bits of the bit “C2” are the lower 4 bits. Here, this processing is expressed as C3 = m (C1, C2).

  First, data is received in units of words by the input register 1, and the data is evaluated for each byte in the four decoders 4 at the same timing. In this process, the decoder 4 outputs 1 if the character “%” is entered, and outputs 0 if any other character is entered. In the case of don't care, this paper uses the notation 'x'. If there is no output value, it is expressed using the notation '-'. The initial value of all the bits of the storage register 3 is 0.

  The data string shaping device for performing the word streaming process of the escape character decoding process is implemented as a circuit having the primary state transition machine shown in FIG. However, the decoding function m is as described in the table, and this is realized by the combinational circuit 5.

  The initial value of the state in the combinational circuit 5 is S0. The decoder 4 having 8 bits as input and 1 bit as output is D (Ix) using the 8-bit input Ix (x = 3, 2, 1, 0).

  As described above, input and output of input data can be repeated for each cycle while maintaining the word length. Since it can be designed in this way, it is possible to perform a data string shaping process without reducing the throughput.

  Even when a large amount of data is processed, a necessary storage area can be configured by only the storage register 3 for one word.

  In addition, since this apparatus performs processing with a predetermined word length, all the circuits from the data input unit to the output unit can be created with the same clock. This has the effect of facilitating the implementation of the apparatus.

  Further, as shown in FIG. 3, it is conceivable to attach an output enable (OutputENABLE) to this embodiment. This has the effect that the subsequent processing portion of the apparatus can efficiently receive the value of the output register 2.

Embodiment 2. FIG.
In the first embodiment described above, the escape character decoding process is performed. When the shaping process that combines the following overlapping spaces (hereinafter referred to as [SP]) is performed, this is performed in units of words. An embodiment to perform is shown.

  FIG. 4 shows a mounting form of the apparatus in such a case. In this implementation, since the target to be found is [SP], D ([SP]) = 1 and D (other than [SP]) = 0. Further, by attaching the upper 8-bit decoding circuit 6 of the storage register 3 to the first embodiment, it is possible to efficiently process erasure of [SP] existing at the word boundary.

  The combinational circuit 5 designed according to this embodiment can be designed by a first-order finite state machine shown in FIGS. The initial value of the state in the combinational circuit 5 is S0.

  Also in this embodiment, the input word unit data is processed and output as it is.

  Further, since both the input and output can be realized with the same clock and in one cycle, there is an effect that easy execution is possible.

Embodiment 3 FIG.
In the second embodiment described above, the shaping process for combining overlapping [SP] s into one can be performed. Next, backspace characters (hereinafter referred to as [BS]) and delete characters (hereinafter referred to as [DEL]). FIG. 6 shows an embodiment in which a character for erasing the previous character is found, and the entire series of character strings is shaped. An example of processing performed according to the present embodiment is shown in FIG.

  As an embodiment, a character string data shaping process based on [BS] and [DEL] will be described. However, as shown in FIG. 10, it is impossible to determine which character disappears without looking at the subsequent [BS] or [DEL].

  For this reason, in the present embodiment, reverse processing is performed in reverse order in units of words as preprocessing. This is necessary for accurate character deletion.

  In this embodiment, since the objects to be found are [BS] and [DEL], D ([BS]) = 1, D ([DEL]) = 1, and D (others) = 0. In the present embodiment, an offset (Offset) indicating how many bytes of data are stored in the storage register 3 is input. This is indicated by reference numeral 901 in FIG. The contents of the storage register 3 are necessary for creating the output register 2. However, only how much data is stored in the storage register 3 is sufficient to determine processing from input to output. Therefore, 901 has an effect of making the generation of output values more efficient.

  Reference numeral 902 denotes a counter for counting unprocessed [BS] or [DEL]. Reference numeral 903 denotes an adder, which adds using the input time 902 and the BS count (Bscount) addition value generated in the shaping process to obtain the value of the Bs counter in the next cycle.

  The combinational circuit 5 designed according to the present embodiment is realized as the combinational circuit 5 shown in FIGS. Also in this implementation, all the processing parts from input to output are processed with the word length unchanged. This has the effect of facilitating implementation.

  In addition, input and output are possible in each cycle of the clock, and there is an effect that processing can be performed with the same throughput as the data transfer bus.

  As described above, by using the basic configuration of the present invention, it is possible to create a data string shaping device capable of word streaming processing. In addition, since the embodiment can deal with various shaping processes only by simple extension, it is not necessary to review the configuration for each processing content. Since the same clock is used for all processes from input to output, the design is easy. Since input and output can be performed in one cycle, the data string shaping process can be performed without reducing the throughput. Since it can be designed specifically for the shaping process, a module that can be easily reused can be created. The storage area may be one word.

It is a block diagram which shows the basic composition of embodiment in this invention. It is the state transition table which performs the decoding process operation | movement of an escape character designed using this invention. It is a block diagram which shows an example of the change structure of embodiment in this invention. It is a block diagram for performing the shaping process which bundles duplication [SP] in one according to this invention. It is the state transition table (1/4) which performs the shaping process which bundles duplication [SP] into one designed by using this invention. It is a state transition table (2/4) which performs the shaping process which binds duplication [SP] into one designed using this invention. It is a state transition table (3/4) which performs the shaping process which bundles duplication [SP] into one designed by using this invention. It is a state transition table (4/4) which performs the shaping process which bundles duplication [SP] into one designed by using this invention. It is a block diagram for performing the appropriate shaping process according to the [BS] character according to the present invention. [BS] is an example of appropriate shaping processing due to characters. It is a state transition table (1/3) which performs an appropriate shaping process based on a [BS] character designed using this invention. It is a state transition table (2/3) which performs an appropriate shaping process based on a [BS] character designed using this invention. It is a state transition table (3/3) which performs an appropriate shaping process based on a [BS] character designed using this invention.

Explanation of symbols

  1 input register, 2 output register, 3 storage register, 4 decoder, 5 combinational circuit, 6 decoding circuit, 901 offset, 902 Bs counter, 903 adder.

Claims (8)

Data string shaping apparatus characterized by having the following elements: (1) Input register for inputting input data for external processing unit in internal processing unit group (2) Output data for external processing unit for internal processing unit Output register (3) output in group, temporary data in the middle of data string shaping process, save register in internal processing unit group (4) evaluate whether it is a specific code for each internal processing unit of input data, Decoder for decoding the evaluation signal for each internal processing unit (5) Connected to the input register, output register, storage register, and decoder, and to the state of the combinational logic circuit itself and the evaluation signal of the internal processing unit In response, the data of the internal processing unit group of the input register and the internal processing unit group of the storage register are newly processed. Sorting the data with the position group, a combination logic circuit for shifting the state of the combinational logic circuit itself. The external processing unit is a word unit, the internal processing unit is a byte unit,
The input register has four internal processing unit groups,
2. The data string shaping device according to claim 1, wherein the output register has four internal processing unit groups. The decoder evaluates whether it is an escape character as a specific code,
3. The data string shaping device according to claim 2, wherein the combinational logic circuit controls the escape character decoding process as a word streaming process.   3. The data string shaping device according to claim 2, wherein a decoding circuit is provided on the output side of the byte unit located above the storage register. The decoder evaluates whether the specific code is a space code,
5. The data string shaping device according to claim 4, wherein the combinational logic circuit controls a process of collecting overlapping space codes into one as a word streaming process.   2. The data string shaping device according to claim 1, wherein an offset for storing the amount of the internal processing unit group used for temporarily storing data in the storage register is connected to the logic circuit. A counter that stores the number of specific codes;
3. An adder for adding the value of the counter when inputting input data and the number of specific codes generated in the data string shaping process to store the sum value in the counter. Data string shaping device. The decoder evaluates whether it is a backspace character or a delete character as a specific code,
8. The data string shaping apparatus according to claim 7, wherein the combinational logic circuit controls the process of deleting characters as a word streaming process.

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