JPH04195347A - Latch circuit - Google Patents

Abstract

PURPOSE:To easily constitute a scan path where a flip-flop circuit and a latch circuit coexist by connecting the output of a main latch to the input of a subordinate latch and holding and outputting the output data of the main latch with trailing edge pulses of a pulse clock signal. CONSTITUTION:Data inputted from an input line 104 is latched in the main latch 1 with a leading edge pulse of the pulse clock signal 105, outputted from an output line 106, and inputted to the subordinate latch 2. The output data of the main latch 1 is set by the subordinate latch 2 with a trailing edge pulse of the pulse clock signal 105, outputted as scan data to an output line 108, and its contents are held until a next trailing edge of the pulse clock signal 105 and outputted. Consequently, when the scan path is constituted so that the latch circuit and flip-flop circuit coexist, racing need not be considered as well as a case wherein the scan path of only the flip-flop circuit is constituted.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to latch circuits.

[Conventional technology]

Conventionally, when the output of a flip-flop circuit is connected to a latch circuit, and the output of a latch circuit is connected to a latch circuit, the output of the flip-flop circuit is immediately set to the next-stage latch circuit, and the output of the latch circuit is immediately set to the next-stage latch circuit. In general, it is not allowed to configure a scan path in which latch circuits and flip-flop circuits are mixed, since this will cause racing if set in the latch circuit.

The above will be explained with reference to the drawings.

FIG. 5 is a block diagram showing an example of a conventional latch circuit, and FIG. 6 is a time chart showing this latch operation.

As shown in FIG. 5, in the conventional latch circuit, the latch 7 enters the through state at the leading edge S1 of the pulse clock signal 301, outputs the input data D^1 as it is from the output line 302 as output data, and outputs the input data D^1 as output data from the output line 302, signal 301
The input data DAI that has been input during the leading edge pulse S, -8,° is set, and the input data DAI is held until the next leading edge S2 of the pulse clock signal 301 and is output to the output line 302.

FIG. 7 is a block diagram showing an example of a flip-flop circuit, and FIG. 8 is a time chart that does not show the operations of the main latch 8 and sub-latch 9 that constitute this flip-flop circuit.

The flip-flop circuit shown in FIG.
5 and a sub latch 9 that sets the output data from the clock signal 304 at the trailing edge of the clock signal 304.

The main latch 8 is connected to the leading edge S of the clock signal 304.

The data DBI set in is held at the trailing edge S r't of the clock signal 304 and output to the output line 305 .

Further, the sub latch 9 is in a through state from the leading edge S1 of the clock signal 304, inputs the output data DBI from the output line 305 of the main latch 8, and outputs it as it is to the output line 306, and the trailing edge of the clock signal 304 The output data DBI is set in Sl', held until the leading edge S2 of the next clock signal 304, and output to the output line 306. The output data from the output line 306 of this sub latch 9 is the output of the flip-flop circuit.

FIG. 9 shows latch 7 of FIG. 5 and main latch 8 of FIG.
Details of the sub latch 9 are shown.

FIG. 10 shows the state of data movement when the output of the flip-flop circuit is connected to the latch circuit.

In the figure, the flip-flop circuit outputs data D up to the leading edge S1 of the clock signal. 1, the latch circuit receives the leading edge pulse 51-3 of the pulse clock signal. I want to set it with ', but since the flip-flop circuit is outputting the next data DC2 set with Sl, the latch circuit sets this data DC2 with the leading edge pulse 51-s of the pulse clock signal, ' .

FIG. 11 shows the state of data movement when the output of the latch circuit is connected to the latch circuit.

In the same figure, the latch circuit at the next stage wants to set the data that the latch circuit is outputting up to the leading edge Sl of the pulse clock signal to the leading edge pulse Sls of the pulse clock signal. Since the next data DD2 is output from the leading edge Sl, the latch circuit 2 receives the leading edge pulses s, -s1' of the pulse clock signal.
And data D. I end up setting 2.

[Problem to be solved by the invention]

As mentioned above, in conventional latch circuits, if the output of the flip-flop circuit is connected to the latch circuit, and the output of the latch circuit is connected to the latch circuit, lacing will occur. Each time a circuit and a latch circuit or a latch circuit and a latch circuit are connected, it is necessary to connect each of them using a separate route in consideration of racing.

For this reason, when a scan path is configured in an information processing device in which flip-flop circuits and latch circuits coexist, the configuration is restricted and becomes complicated.

[Means to solve the problem]

The latch circuit of the present invention includes a main latch that selects input data or scan data by a scan instruction signal and sets it at a predetermined level state of an input pulse clock; When the sub latch is set at a level opposite to the level state of the clock and the scan instruction signal is invalid, the pulse clock signal synchronized with the clock signal is distributed, and when the scan instruction signal is valid, the clock signal is distributed. and a pulse clock distribution circuit that distributes an inverted signal as the pulse clock signal.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a time chart showing its operation. As shown in FIG. 1, in this embodiment, input data 104 is set by the leading edge pulse of the pulse clock signal 105, and the main latch 1 and the main latch 1 set the input data 104 until the next leading edge of the pulse clock signal 105. 1 output data 106, is set by the trailing edge pulse of the pulse clock signal 105, holds the input data until the next trailing edge of the pulse clock signal 105, and outputs the input data to the scan data output line 108; , an inversion circuit 10 that inverts the scan instruction signal 100, an AND gate 11 that is opened by the scan instruction signal 100 and passes the scan data signal 101, and an inversion circuit 10 that inverts the scan instruction signal 100.
Data signal 1 is opened by a signal inverted by
AND gate 12 that allows 02 to pass through, and AND gate 1
1 or the output of the AND gate 12 to the main latch 1 as input data 104 to the main latch 1.
3, when the scan instruction signal 100 is O'', the clock signal 103 is differentiated and output as a pulse clock signal 1.05 in order to perform a normal latch operation, and when the scan instruction signal 100 is 1°, the clock signal is output as a pulse clock signal 1.05. The pulse clock signal distribution circuit 3 only inverts the signal 103 and outputs it as a pulse clock signal 105.

The pulse clock signal distribution circuit 3 includes two AND gates 14, 18 and three NAND gates 15, 16 .
17 and two AND gates] 9゜20 and OR gate 2
1.

Here, first, when the scan instruction signal 100 is "0", the AND gate 12 is open and the data signal 1
02 is input to main latch 1 through AND gate 12 and OR gate 13. Further, the AND gate 19 of the pulse clock signal distribution circuit 3 is closed, the Nant gate 15 and the AND gate 20 are open, and the clock signal 1
03 is differentiated by the Nant gates 15, 16, 17 and the AND gates 14, 1.8, and is applied to the main latch 1 through the AND gate 20 and the OR gate 21 as a pulse clock signal 105' for normal latch operation.
is output to sub latch 2. This pulse clock signal 10
5 leading edge pulses cause the main latch 1 to set the data signal 102 and hold the input data until the next leading edge of the pulsed clock signal 105 and output it on the output line 107.

FIG. 2(A) is a time chart of the latch circuit of FIG. 1 when the scan instruction signal 100 is "0".

In the figure, the main latch 1 has a pulse clock signal 105.
When the pulse clock signal 105 is 0'', it is in the through state, and when the pulse clock signal 105 is 0'', it is in the holding state. Therefore, the leading edge pulses s, -s,' of the pulse clock signal 105
During the period of the through state, the data D input from the input line 104 is output as is to the output line 106, but during the period of the trailing edge pulse S1''-82 of the pulse clock signal 105, it is held and the input data is D, is held and output to the output line 106.

Also, during this holding state, data D2 input to the main latch 1 from the input line 104 at S1°-82 is ignored;
As in the case of the data D1 described above, the pulse clock signal 10
When the main latch 1 enters the through state at the next leading edge S2 of 5, it is output to the output line 106 as output data, and throughout this through state period S2-82' and the subsequent holding state period S2°-83. The input data D2 is held and output to the output line 106.

On the other hand, the sub latch 2 receives the pulse clock signal 105 or "1'".
', it is in the holding state, and when the pulse clock signal 105 is "0", it is in the through state.Therefore, during the through state period of the trailing edge pulse S1-82 of the pulse clock signal 105 and the following leading edge pulse S2- The duration of the hold state of S2°, i.e. Sl.

At -82°, the main latch 1 passes or holds the data D1 set by the leading edge pulses 5l-s,' of the pulse clock signal 105 to the output line 108. Therefore, the sub latch 2 receives the output data of the main latch 1 by the pulse clock signal 1.
It is possible to output the signal to the output line 108 with a delay of 0.05 leading edge pulse width.

Next, the operation when the scan instruction signal 100 is "1" will be explained.

When the scan instruction signal 100 is "°1'", the AND gate 11 opens and the AND gate 12 closes.
Scan data signal 101 is input to main latch circuit 1 via antogenide 11 and OR gate 13. Further, since the AND gate 19 of the pulse clock signal distribution circuit 3 is opened and the Nand gate 15 and the AND gate 20 are closed, the clock signal 103 is transmitted to the AND gate 14.
The signal inverted by and Nant gate 18,
The pulse clock signal 105 is output as is through the AND gate 19 and the OR gate 21.

By the leading edge pulse of this pulse clock signal 105,
The main latch 1 sets data input from the input line 104, outputs it from the output line 106, and inputs it to the sub latch 2. The sub latch 2 sets the output data of the main latch 1 with the trailing edge pulse of the pulse clock signal 105, and outputs the output line 1.
08 as scan data, and its contents are held and output until the next trailing edge of the pulse clock signal 105.

That is, as shown in FIG. 2(B), when the scan instruction signal 100 becomes 1" while the tarock signal and pulse clock signal are stopped at the beginning of the transition to the scan state, the pulse clock signal 105 becomes 0. The data DA held in the main latch 1 is moved to the sub latch 2 and held there.

Then, when the clock signal starts moving to perform scanning again, the pulse clock signal 105 changes to the clock signal 10.
The inverted version of 3 is input. As a result, the main latch 1 of the latch circuit. The sub latch 2 operates at the same timing S2. The data is determined in S3 and held for the same period 52-s, s, -s4. Therefore, as shown in FIG. 3, when the output 200 of the flip-flop circuit 4 is connected to the latch circuit 5, and the scan data output 201 of the latch circuit 5 is connected to the latch circuit 6, the data movement state is as shown in FIG. It becomes as shown in . The details of latch circuits 5 and 6 in FIG. 3 are the same as in FIG. 1.

In FIG. 3, the flip-flop circuit 4 holds the scan data D set at So until S2 and outputs the data to the data output line 2.
00, and the latch circuit 5 at the next stage is inputted from the flip-flop circuit 4. Set the scan data D1 at 82, hold it until S4, and output the scan data output line 201.
Output to.

' Also, the scan data output 201 of the latch circuit 5
The next stage latch circuit 6 that receives the input is the previous stage latch circuit 5.
The latch circuit 6 at the next stage sets data Do at So, holds it until S2, and outputs it to the scan data output line 201, and sets it at S2, holds it until S4, and outputs it to scan data output &1202. In other words, the scanning operation can be performed without causing racing.

Therefore, when constructing a scan path by mixing the latch circuit of the present invention with a flip-flop circuit, it can be constructed without considering racing, as in the case of constructing a scan path using only flip-flop circuits.

〔Effect of the invention〕

As explained above, in the latch circuit of the present invention,
The output of the main latch is connected to the input of the sub latch, and the sub latch holds and outputs the output data of the main latch according to the trailing edge pulse of the pulse clock signal. The configuration is such that the data held in the main latch is held and output, and when the scan instruction signal is °゛1°°, a signal obtained by inverting the clock signal is input to the main latch and the sub latch as a pulse clock signal. This allows the operation of the latch circuit to match that of the flip-flop circuit. Therefore, by connecting the output of the secondary latch to a subsequent flip-flop circuit or similar latch circuit, and the output of the flip-flop circuit to this latch circuit, it is possible to connect the output of the secondary latch to a subsequent flip-flop circuit or similar latch circuit, without losing normal latch operation, and by connecting a separate This has the effect that it is possible to easily configure a scan canvas in which flip-flop circuits and latch circuits are mixed together without providing any ports.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the latch circuit of the present invention, FIG. 2 is a time chart of the latch circuit shown in FIG. 1, FIG. 3 is a configuration diagram of a scan path using the latch circuit of the present invention, and FIG.
5 is a block diagram showing an example of a conventional latch circuit. FIG. 6 is a time chart showing the operation of this latch circuit. The figure shows an example of a flip-flop circuit, FIG. 8 is a time chart showing the operation of the main latch and sub latch in the conventional example, and FIG. 9 is a configuration diagram of the latch circuit.
Figure 10 is a time chart showing the data movement state when the output of a flip-flop circuit is connected to a conventional latch circuit, and Figure 11 is a time chart showing the data movement state when the output of a conventional latch circuit is connected to a conventional latch circuit. It is a time chart showing a moving state. 1.8...Main latch, 2.9...Sub-latch, 3...
- Pulse clock signal distribution circuit, 4... flip-flop circuit, 5, 6... latch circuit, 7... latch,
10... Inversion circuit, 11, 12, 19.20... AND gate, 13.21... OR gate, 14.18
...and Nantes Gate, 15, 16, 17...
Nantes Gate.

Claims (1)

[Claims] A main latch that selects input data or scan data using a scan instruction signal and sets it at a predetermined level state of an input pulse clock; When the scan instruction signal is invalid, the pulse clock signal synchronized with the clock signal is distributed, and when the scan instruction signal is valid, the clock signal is distributed. A latch circuit comprising: a pulse clock distribution circuit that distributes an inverted signal as the pulse clock signal.