JPH04115719A - Logic circuit device - Google Patents

Abstract

PURPOSE:To attain transfer at a scan path without a skipped data by not outputting the data before a slower clock signal does not come in clock signals inputted through two signal lines. CONSTITUTION:A flip-flop SFF 13 storing an input data by any clock input in two clock signals and outputting the stored data with the input of a clock signal coming later is provided in a scan path. Thus, even when a clock skew takes place, since the SFF 13 is used, and if a signal change (0 to 1) of a clock pulse outputted from a clock driver 2b reaches earlier the SFF 13 than that of a clock driver 2c, a read data is not outputted from a data output terminal 5e of the SFF 13. Then a signal change (0 to 1) outputted from the driver 2c reaches the SFF 13 and a read data is outputted from the data output terminal of the SFF 13. Thus, it is not caused that the data from the SFF 3d is transferred to the SFF 3f while skipping the SFF 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit device designed in a scan manner using l-phase edge trigger type flip-flops.

[Conventional technology]

Figure 3 shows a scan path of a logic circuit device designed to scan using a conventional l-phase edge trigger type flip-flop (hereinafter referred to as SFF) having a scan function and a part of the clock signal input thereto. This is a logic circuit diagram, in which 1a to 1d are clock signal lines, 2a
2C is a clock driver, 3a to 3h are SFFs constituting a scan path, and 5FFs 3a to 3h are positive edge trigger type. 4a to 4h are shift input terminals, 5a to 5h are data out terminals, 6a to 6
h indicates a clock input terminal of the SFF, 7a to 7h indicate data input terminals, 9 indicates a control signal for switching the input mode of the 5FFs 3a to 3h, and 8a to 8h indicate mode switching terminals to which the control signals are input.

Generally, there is a limit to the driving ability of the output capacitance of a clock driver, so when driving a large number of 5FFs 3a to 3h, as shown in FIG.
It is common to configure c in multiple stages. In the case of this FIG. 3, the clock driver 2a is the clock driver 2b, 2
It has a two-stage configuration in which 2b and 2c drive the SFF.

FIG. 4 shows the internal configuration of the 5FFs 3a to 3h used in FIG. 3. In the figure, 10 indicates a logic gate,
1la-1id is a P channel type M○S transistor and N
A transmission gate formed using a channel type MOS transistor is shown, and the area inside the dashed-dotted lines 12a and 12b shows a latch circuit that holds data of 5FFs 3a to 3h.

Next, the operation will be explained.

When "1" is input to the shift mode switching terminal 8 shown in FIG.
When the clock input from 1 changes from "0" to "1", data is read by the positive edge clock signal input, and the read signal is sent to the latch circuit 12.
a and is output from the data out output terminal 5.

Next, when the clock changes from 1" to "O", the latch circuit 12b enters the holding state and the latch circuit 12a enters the data rewriting state.

Conversely, when "0" is input to the shift mode switching terminal 8, the same operation is performed for data input from the data input terminal 7 instead of from the data input terminal 4.

Hereinafter, it will be assumed that a change in the lock signal like this is an input of a clock pulse.

In the logic circuit of FIG. 3, when the signal controlling the scan mode is "0", the signal values input to the data input terminals 7a to 7h are read by the 5FFs 3a to 3h by the input of the clock pulse, The data is output from the data out terminals 58 to 5h and is held as long as there is no input of the next tarok pulse. On the other hand, when the signal controlling the scan mode is "l", the signal values input to the shift data input terminals 4a to 4h are changed to 5FF3a to 3h by the input of the clock pulse.
The data is read by the data out terminals 5a to 5h, and is held until the next clock pulse is input, and the same operation is repeated by the input of the next clock pulse. At this time, with one clock pulse input, the shift data input terminal 4d of 5FF3d
The signal value that had been input to 5FF3e is input to the shift data input terminal 4e of 5FF3e, and upon input of one more clock pulse, that signal value is input to the shift data input terminal 4f of 5FF3f(7). Also, first, 5FF3
The signal value input to the shift input terminal 4e of e is the clock signal at the input of the first clock pulse mentioned above, and is 5.
It is input to the shift data input terminal 4f of FF3f, and when the second clock pulse is input, the signal value becomes SFF3g.
The data is input to the shift data input terminal 4g of the shift data input terminal 4g. In this way, each 5FF3 is
The data input to the shift data input terminals 4a to 4h of a to 3h are transferred to the next stage SFF along the scan path.

[Problem to be solved by the invention]

There were eight problems related to the conventional one-phase clock architecture.

That is, in FIG. 3, the time when the clock pulse reaches the SFFs constituting the scan canvas, for example, the time when it reaches 5FF3d and the time when it reaches 5FF3e, is due to the difference in the length of the wiring driven by each of the clock drivers 2b and 20. Differences may occur due to differences in output capacitance due to factors such as differences in output capacitance, or differences in driving ability for driving the output capacitance of the clock driver. This is a time difference called clock skew. When this clock skew occurs, for example, 5F
5FF3 before the clock pulse reaches F3e
If the clock pulse reaches d, 5FF3e
Before reading the input signal value to the shift data input terminal 4e using a clock pulse, the signal value input to the shift data input terminal 4d of 5FF3 (i
The signal value that is output from the data output terminal 5d of 5FF3e and input to the shift data low input terminal 4e of 5FF3e is updated, and the signal value that should be output from the data output terminal of 5FF3d is changed by inputting one clock pulse. 5FF3e
A problem arises in that the data is skipped and transferred to 5FF3f.

Therefore, in conventional devices, it is necessary to eliminate or sufficiently reduce clock skew and set data transfer so that one SFF is transferred with one pulse. 2b and 20, it is necessary to adjust the output capacitance driven by the clock driver, the ability to drive the output capacitance of the clock driver, or both to make the delay times of the clock drivers equal.

Therefore, restrictions had to be placed on circuit design to prevent clock skew from occurring.

This invention was made to solve the above-mentioned problems, and is an edge trigger type SF with l-phase lock.
An object of the present invention is to obtain a logic circuit device scan-designed using F, which can transfer data without skipping the SFF even if a clock skew occurs.

[Means to solve the problem]

In order to achieve such an object, the present invention provides a logic circuit device scan-designed using an edge trigger type SFF with a single-phase clock, in which an SFF constituting a scan path is connected to the clock input terminal of the adjacent SFF before and after it. When the clock signal lines input to the two signal lines are driven by different clock drivers, the function of the SFF is to accept both clock signal lines as input and to output the slower clock signal inputted by the two signal lines. Data is output only in response to a clock signal.

[Effect]

In the logic circuit device of this invention scan-designed using an edge trigger type SFF with a single-phase clock,
When the clock signal lines input to the clock input terminals of the SFF are driven by different clock drivers, as a function of one of the SFFs, both clock signal lines are input, and the clock signal input by the two signal lines is input. Since data is first output by the slower clock signal, even if a clock skew occurs, an SFF that performs a transfer operation in a scan path can be transferred without skipping data.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a logic circuit device scan-designed using an edge-trigger type SFF that performs transfer using an l-phase clock according to an embodiment of the present invention. ~2c13a~3h1
4a~4h15a~5h, 6a~6h, 7a~
7h, 8a to 8h, and 9 are equivalent to FIG. 3 showing the prior art. Further, reference numeral 13 indicates an SFF according to an embodiment of the present invention having two clock signal input terminals 14 and 15, and FIG. 2 shows an internal logic circuit diagram of this SFF 13.

In FIG. 2, 14.15 indicates a clock input terminal, and 10.15 indicates a clock input terminal. 11a to 11d, 12a=12b are the same as in FIG.

Next, the operation will be explained.

As an example, the internal operation of the positive edge trigger type scan flip-flop shown in FIG. 2 when the clock TI is input before the clock T2 will be explained using a timing chart.

The input of T1 changes from "0" to "l" at the change point 18 shown in FIG.
”, the output 17 of the NOR gate with inputs T1 and T2 changes from “1” to “0”, and the latch circuit 12a in FIG. Transmission gate lla is open and transmission gate llb is closed in FIG. This shows that even if the output of the gate 10 in FIG. 2 changes, the data held by the latch circuit 12a does not change.

Next, the clock signal to clock T2 is from “0” to “
1”, the output 16 of the NAND gate that inputs TI and T2 changes from “l” to “0”, and the latch circuit 12b changes from the latched state (same as 12a) to the rewritten state (
12a), then the input of TI changes from "l" to "0" at the change point 20 shown in FIG. 5, and the output 16 of the NAND gate changes from "0" to "1". , the latch circuit 12b changes from the rewriting state to the latching state. Finally, the input of T2 changes from "l" to "0" at the change point 21 shown in FIG.
” and the output 17 of the NOR gate changes from “0” to “1”.
", and the latch circuit 12a changes from the holding state to the rewriting state. This completes the data reading and output operation.

Next, FIG. 1 relating to an embodiment of the present invention using SFF I 3 shown in FIG. 2 will be explained. The logic circuit in FIG.
0'', the input of the clock pulse changes the signal value input to the data input terminals 7a to 7h to 5FF3.
a~3h, and the data out terminals 5a~
The data is output from 5h and is held until the next clock pulse is input. When the signal controlling the scan mode is 9 or "1", the signal values input to the shift data input terminals 4a to 4h are changed to SFF3a to 3d, 13.3 by the input of the clock pulse.
Read by f~3h, data out terminal 5a~
The data is output from 5h and held until the next clock pulse is input, and the same operation is repeated by the next clock pulse input.

At this time, with one clock pulse input, the signal value inputted to the shift data input terminal 4d of 5FF3d is inputted to the shift data input terminal 4e of SFF13, and one more clock pulse is input. When the pulse is input, its signal value is input to the shift data input terminal 4f of the 5FF 3f.

Also, the signal value that was initially input to the shift input terminal 4e of the SFF 13 is a clock signal when the first clock pulse is inputted, and is input to the shift data input terminal 4f of the 5FF 3f, and then the second clock pulse is input. The signal value is input to shift data input terminal 4g of SFF3g.
is input. In this way, each 5FF3a to 3d, 13.3f to 3
The data input to the shift data input terminals 4a to 4h of the shift data input terminal 4a to 4h of the shift data input terminal 4h is transferred to the next stage SFF along the scan canvas.

In FIG. 1, the time when the clock pulse reaches 5FF3a to 3d and 13.3f to 3h forming the scan path, for example, the time when the clock pulse reaches 5FF3d and the time when it reaches 5FF3e, are driven by the clock drivers 2b and 20, respectively. Differences may occur due to differences in the output capacitance due to differences in the length of the wiring, etc., or differences in the driving ability of the clock driver to drive the output capacitance. In other words, even if a clock skew occurs, the logic circuit shown in FIG.
Since the SFF 13 is used, if the signal change from "0" to "1" of the clock pulse output from the clock driver 2b reaches the SFF 13 before that of the clock pulse 20, the data output terminal 5d of the 5FF3d will change. Shift data Read data from data input terminal 4e, SFF 1
The read data is not output from the data output terminal 5e of No.3.

Next, a signal change from "1" to "0" of the clock pulse output from the clock driver 2C arrives, and the read data is output from the data output terminal of the 5FF13.

Therefore, data is not transferred from 5FF3d to 5FF3f by skipping 5FF13. Even when the signal values from the clock driver change in the reverse order, the same operation is performed, so the data changes from 5FF3d to SFF13.
will not be skipped and transferred to 5FF3f.

Although the above embodiment shows an example in which a positive edge trigger clock signal is used, a negative edge trigger type clock signal and a negative edge trigger type SFF may also be used, and the same effect as in the above embodiment can be obtained. have

[Effects of the Invention] As described above, according to the present invention, in a logic circuit device scan-designed using an edge trigger type SFF with a single-phase clock, an SFF constituting a scan path is connected to two adjacent 5FFs ( 7) If the clock signal line input to the clock input terminal is driven by a different clock driver, input both drive signal lines,
Among the clock signals input through the two signal lines, data is output only by the slower clock signal, so even if clock skew occurs, the transfer operation on the scan path can be performed without data skipping. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing a scan path of a logic circuit device designed using an edge-trigger type SFF for one-phase clock transfer according to an embodiment of the present invention and a part of a clock signal input thereto; The figure is a logic circuit diagram of the SFF of the present invention used in Figure 1, and Figure 3 is an example of the scan path of a logic operation device designed using an edge-trigger type SFF with one-phase clock transfer according to an example of the conventional technology, and its input. Figure 4 is a logic circuit diagram of the SFF used in Figure 3, and Figure 5 shows the internal operation timing of the positive edge trigger type scan flip-flop in Figure 2. It is a chart diagram. In the figure, 1a to 1d are clock signal lines, 2a to 2c
is a clock driver, 3a to 3h are SFFs forming the scan path, 4a to 4h are shift input terminals, and 5a
~5h are data out terminals, 6a~6h are SFF clock input terminals, 7a~7h are data input terminals, 8a~8
h is a mode switching terminal, 9 is a control signal for switching the SFF mode, 10 is a logic gate, lla to li
d is a transmission gate formed using a P-channel type MOS transistor and an N-channel type MO3) run lister, 12a and 12b are latch circuits, and 13 is an SFF.
, 14.15 are SFF clock signal input terminals. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 2

Claims (1)

[Claims] (1) In a logic circuit device in which a scan path that transfers data using a single-phase clock is designed using multiple flip-flops and multiple clock drivers, two different clock drivers are generated from the same clock signal source. The scanning path is characterized by comprising a flip-flop in the scan path that stores input data according to one of the two clock signals transmitted through the clock input, and outputs the stored data according to the input of the slower clock signal. Logic circuit device.