JPH01236728A - Clock signal switching device - Google Patents

Abstract

PURPOSE:To require no switching signal to simplify the device constitution by alternatively switching and outputting one clock signal or another. CONSTITUTION:When a clock signal CKA is inputted, the q output of an FF 24 set by a pulse P2 is switched to the low level by the signal CKA and the D input of an FF 25 goes to the low level at the timing when a pulse P1 is inputted to the FF 25. Consequently, the Q output of the FF 25 is kept in the low level and an AND circuit 29 continues to close the gate to stop the output of a clock signal CKD. When the signal CKA is inputted, an FF 26 keeps the inverted Q output in the high level and an AND circuit 28 continues to open the gate and the signal CKA is outputted as an output clock signal CKO through an OR circuit 30. Thus, gates of circuits 28 and 29 are opened and closed to alternatively switch the signal CKO to the signal CKA or the signal CKD.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a clock signal switching device, and in particular is applied to a laser printer or a display device, in which these devices transfer data (for example, image data) from a host device. The present invention also relates to a clock signal switching device that switches to its own clock signal when the clock signal from a host device disappears when receiving a clock signal and processing data based on the clock signal.

(Prior Art) Devices that process image data (hereinafter referred to as image processing devices) such as laser printers, scanners, and CRT display devices process images by receiving clock signals along with image data from host devices such as computers and word processors. There is.

In such an image processing device, if a clock signal is not input from the host device, there is a risk that the device will stop.

For example, in a laser printer, as shown in Figure 3,
There is a control time between scan lines, and during this control time, there are cases where no image data is input, and no clock signal is input either. In addition, as shown in FIG. 4, the laser printer 1 and the host
Even when the connector 3 connecting to the device 2 is disconnected, the clock signal is no longer input to the host device 2.

In such a case, in order to prevent the operation of the laser printer 1, which is an image processing device, from stopping, a conventional clock signal switching device is used to switch to an internal clock signal from an oscillator built into the laser printer 1. 1 operation is ensured.

Conventionally, a clock signal switching device as shown in the fifth example has been used. That is, the clock signal switching device 4 includes an AND circuit 5.6, an OR circuit 7, and an inverter circuit 8. The clock signal Sc is selectively switched by a switching signal Su and outputted as an output clock signal SO.

However, this conventional clock signal switching device 4
Since the basic clock signal Sk and the internal clock signal Sc are simply switched, a glitch g occurs in the output clock signal So, as shown in FIG. 6, which shows the waveforms of each signal. This may interfere with the operation of the image processing device.

Therefore, conventionally, as shown in FIG.
3.14.15.16, flip-flops 17 and 18, and an OR circuit 19 to prevent glitches from occurring in the output clock signal SO. That is, the flip-flop 17 is switched by the basic clock signal Sk.
The operation of the flip-flop 18 is controlled based on the ζ output of the flip-flop 18 which is switched by the internal clock signal Sc, and the operation of the flip-flop 18 is controlled based on the ζ output of the flip-flop 17. The Q output of the flip-flop 18 is input to the AND circuit 15 to which the basic clock signal Sk is input to control the output of the basic clock signal Sk, and the Q output of the flip-flop 18 is input to the AND circuit 16 to which the internal clock signal Sc is input. controls the output of the internal clock signal Sc.

Therefore, as shown in the waveforms of each signal in FIG. 8, it is possible to selectively switch between the basic clock signal Sk and the internal clock signal Sc using the switching signal sh without causing glitches in the output clock signal So. .

(Problem to be Solved by the Invention) However, in such a conventional clock signal switching device, both clock signals are mutually used as operating signals for flip-flops that control the output of both clock signals. Furthermore, since these flip-flops are switched using a switching signal different from the clock signal, there is a risk that if one of the clock signals disappears midway through, no output clock signal will be output at all.

Furthermore, switching the clock signal always requires a switching signal separate from the clock signal.

(Purpose of the Invention) Therefore, the present invention detects the presence or absence of one clock signal based on the other clock signal, and when one clock signal disappears, switches to the other clock signal. When a clock signal is input, the output of the other clock signal is stopped and then switched to the first clock signal, thereby eliminating glitches in the output clock signal.
In addition, the purpose is to switch to and output another clock signal when one clock signal disappears without using a switching signal, and to stably operate an image processing device, etc. to which the clock signal switching device is applied. It is said that

(Structure of the Invention) In order to achieve the above object, the present invention includes a clock detection means that detects the presence or absence of one clock signal based on another clock signal, and a clock detection means that operates based on the other clock signal. a signal switching means that stops outputting another clock signal when one clock signal is detected and outputs another clock signal when one clock signal is not detected; and a signal switching means that operates based on the other clock signal. , timing adjustment means for outputting the first clock signal after the output of the other clock signal is stopped by the signal switching means when the first clock signal is once lost and then input again; It is characterized in that the clock signal and other clock signals are selectively switched and output.

Hereinafter, the present invention will be specifically explained based on examples.

Figure 1.2 (This is a diagram showing one embodiment of the civil engineering invention.

In FIG. 1, 21 is a laser printer, a scanner,
This is a clock signal switching device applied to CRT displays, etc., and the clock signal switching device 21 is connected to an inverter 22.
．． 23, flip-flops 24, 25, 26, a NAND circuit 27, AND circuits 28, 29, an OR circuit 30, an oscillator 31, a counter 32, and a decoder 33.

A basic clock signal (one clock signal') CKA is input to the laser printer 21 from a host device (not shown), such as a computer, and the basic clock signal CKA
is input directly to the AND circuit 28 and also to the T inputs of the flip-flop 24 and the flip-flop 26 via the inverter 22. The oscillator 31 outputs a clock signal CKB with a cycle four times that of the clock signal CKA to a counter 32 and a decoder 33, and the decoder 33, which is an octal counter, outputs a clock signal CKC with a cycle twice that of the clock signal CKA, which is the same as the clock signal CKA. An internal clock signal (another clock signal) CKD with a cycle and a clock signal CKE with a half cycle of the clock signal CKA are created. Clock signal CKCl Internal clock signal CK
D and the clock signal CKE are decoded by the counter 32 to produce a pulse P1 that goes low every eight pulses of the clock signal CKB, and a pulse P2 that is delayed from the pulse P by one pulse of the clock signal CKB. Further, the clock signal CKD is input to an AND circuit 29, and the Q output of the flip-flop 25 is further input to the AND circuit 29. Pulse P is input to the NAND circuit 27 and the T input of flip-flop 25 via inverter 23, and pulse P2 is input to the set input of flip-flop 24. The Q output of the flip-flop 24 becomes high at the falling edge of the pulse P2, and the clock signal CKA
It becomes low at the falling edge of .

That is, the flip-flop 24 is set by the pulse P2, and constitutes a clock detection means for detecting the presence or absence of the input of the clock signal CKA. The pulse P2 is a signal related to the clock signal CKD, and the flip-flop 24 detects whether or not the clock signal CKA is input based on a signal (pulse P2) based on the clock signal CKD. The Q output of the flip-flop 24 is input to the NAND circuit 27 and the D input of the flip-flop 25, and when the D input (Q output of the flip-flop 24) is high, the inverted signal of the pulse P1 is input to the flip-flop 25. At this rising edge, the Q output switches to high. The Q output of this flip-flop 25 is input to the AND circuit 29 as described above.
The basic clock signal CKD input to the other terminal of
controls the output of That is, flip-flop 2
5 detects the Q output (detection result of the clock detection means) of the flip-flop 24 according to the pulse P1, that is, based on the clock signal CKD, and when the clock signal CKA is not input, opens the AND circuit 29 to output the clock signal. Output CKD. The gate of this AND circuit 29 is opened by the pulse P based on the clock signal CKD.
This is when the Q output of the flip-flop 25 becomes high, so the occurrence of glitches is prevented. The Q output of the flip-flop 25 is the D output of the flip-flop 26.
The output of the NAND circuit 27 is input to the S input of the flip-flop 26.

Therefore, when the Q output of the flip-flop 25 is switched to low, the NAND circuit 27 switches its Q output to low based on the pulse P input via the inverter 23 and the NAND circuit 27, and the NAND circuit 28 switches its Q output to low. Close the gate. As a result, even if the clock signal CKA is input,
The clock signal CKA is not output from the AND circuit 28 until the d output of the flip-flop 2G becomes high, thereby preventing the occurrence of glitches. After the clock signal CKA is temporarily lost, it is input again, and the flip-flop 24
When the Q output of the flip-flop 25 becomes high, the Q output of the flip-flop 25 becomes low based on the pulse P, and then when the clock signal CKA is input, the flip-flop 26 sets its Q output to high and runs the AND circuit 28. open. Therefore, thereafter, the input clock signal CKA is input to the OR circuit 30 through the AND circuit 28, and the OR circuit 3
0 is output as the output clock signal CKO.

Therefore, the inverter 23, the NAND circuit 27, the flip-flop 25 and the AND circuits 28 and 29 are connected to the pulse P
1 (a signal related to another clock signal, the clock signal CKD), and the flip-flop 24
(clock detection means) detects the clock signal CKA (one clock signal), the clock signal CKD
(other clock signals) and outputs the clock signal CKD via the flip-flop 25 when the clock signal CKA is not detected.
The flip-flop 26 and the AND circuits 28 and 29 operate based on the pulse P1, and when the clock signal CKA is input again after the clock signal CKA is no longer input, the output of the clock signal CKD is stopped by the flip-flop 25, and then the AND circuits are activated. It constitutes a timing adjustment means 35 that opens the circuit 28 and switches the clock signal CKO to the clock signal CKA and outputs the clock signal CKA.

Next, the operation will be explained based on the timing chart shown in FIG.

When the clock signal CKA is input from the host device, the flip-flop 24 set by the pulse P2
At the timing when the Q output of the flip-flop 25 is switched to low by the clock signal CKA and the pulse P is input to the flip-flop 25, the D input of the flip-flop 25 is low. Therefore, the Q of flip-flop 25 is
The output remains low, the AND circuit 29 continues to close the gate, and the clock signal CKD input to the AND circuit 29
Stop outputting. On the other hand, since the Q output of the flip-flop 25 is high and the Q output of the flip-flop 24 is low at the timing when the pulse P is input, the NAND circuit 27 is closed. Therefore, when the clock signal CKA is input, the flip-flop 26 maintains its Q output high, keeps the gate of the AND circuit 28 open, and outputs the clock signal CKA as the output clock signal CKO via the OR circuit 30. do.

When the clock signal CKA from the host device is no longer input, the flip-flop 24 set by the pulse P2 detects that the input of the clock signal CKA is no longer switched to low by the clock signal CKA, and the flip-flop 24 continues to maintain its Q output high. Therefore, the D input of the flip-flop 25 becomes high at the manual timing of pulse P, and the Q output of the flip-flop 25 becomes high, opening the gate of the AND circuit 29. At the same time, the Q output of the flip-flop 24 becomes high and the NAND circuit 27
, the pulse P1 is input to the S input of the flip-flop 26, and the Q output of the flip-flop 26 switches to low. Therefore, the gate of the AND circuit 28 is closed and the output clock signal CKO becomes the clock signal C
KA is switched to clock signal CKD.

After that, when the clock signal CKA is input again, the Q output of the flip-flop 24 is switched to low again, the Q output of the flip-flop 25 is switched to low by the pulse P, and the buying output of the flip-flop 26 is switched to high. Switch to . Therefore, clock signal CKO is switched from clock signal CKD to clock signal CKA.

In this way, the presence or absence of input of the clock signal CKA is detected based on the pulse P2 related to the clock signal CKD,
Opening and closing the gates of the AND circuit 28 and the AND circuit 29,
The output clock signal CKO can be selectively switched between the clock signal CKA and the clock signal CKD. Therefore, no separate switching signal is required, and the configuration of the laser printer 21 can be simplified. Further, since the gates of the AND circuit 28 and the AND circuit 29 are opened and closed by the pulse P1 related to the clock signal CKD,
It is possible to prevent glitches from occurring when switching the output clock signal CKO, and the radar printer 21
Devices to which this technology is applied can operate stably without causing malfunctions.

(Effects) According to the present invention, there is no ε that causes glitches in the output clock signal, and there is no need to use a switching signal.
When one clock signal disappears, it is possible to switch to and output another clock signal, and it is possible to stably operate an image processing device or the like in which the clock signal switching device is used.

[Brief explanation of the drawing]

1.2 are diagrams showing one embodiment of the clock signal switching device of the present invention, FIG. 1 is a circuit diagram thereof, and FIG. 2 is a timing chart of signals of each part thereof. FIG. 3.4 is an explanatory diagram showing a state in which a timing signal inputted from the outside to the image processing apparatus disappears. 5.6 is a diagram showing an example of a conventional clock signal switching device, FIG. 5 is its circuit diagram, and FIG. 6 is its signal timing chart. 7.8 is a diagram showing another example of a conventional clock signal switching device, FIG. 7 is its circuit diagram, and FIG. 8 is its signal timing chart. 21...Clock signal switching device 22.23...
...Inverter, 24...Flip-flop (clock detection means), 25.26...Flip-flop, 27.
... NAND circuit, 28.29 ... AND circuit, 30 ... OR circuit, 31 ... Oscillator, 32 ... Counter, 33. ... Decoder, 34 ... Signal switching means, 35 ... Timing adjustment means.

Claims (1)

[Claims] clock detection means for detecting the presence or absence of one clock signal based on the other clock signal; a signal switching means that stops the output and outputs another clock signal when the first clock signal is not detected; and timing adjustment means for outputting one clock signal after the output of the other clock signal is stopped by the signal switching means, and selectively switching between the one clock signal and the other clock signal. A clock signal switching device characterized by outputting a clock signal.