JPH04188675A - Manufacture of non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable a non-volatile semiconductor memory device provided with a tunnel oxide film very small in area to be easily and efficiently formed by a method wherein a thin tunnel oxide film is formed in a self-aligned manner taking advantage of a phenomenon that an oxide film is selectively formed on a semiconductor part doped with impurities at thermal oxidation. CONSTITUTION:An ion injection mask 8 provided with an ion injection window H is formed on a semiconductor substrate 1 provided with a gate oxide film 6, and impurity ions are implanted into the surface of the semiconductor substrate 1 under the window H. The gate oxide film 6 is removed by etching through the window H to form a substrate exposed part 9 wider than the window H, the expose part 9 is subjected to an oxidizing treatment to enable its center correspondent to an impurity implantation region to be oxidized, and the peripheral part 101 is made to serve substantially as a non-oxidized selective oxidation layer 10. The semiconductor substrate 1 is thermally oxidized to form an impurity diffusion region 7, and the non-oxidized part 101 is oxidized to form a tunnel oxide film 2. By this setup, a non- volatile semiconductor memory device provided with the tunnel oxide film 2 small in area can easily and efficiently be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a method of manufacturing a nonvolatile semiconductor memory device. More specifically, the present invention relates to a nonvolatile semiconductor memory device (EEP[70M) in which memory contents can be electrically written/erased.

(b) Conventional technology Conventionally, as the above-mentioned nonvolatile semiconductor memory device,
As shown in Fig. 4, a FLOTOX-type EEPIliO-
It has been known. In the figure, l is a silicon semiconductor substrate, 2 is a tunnel oxide film, 3 is a floating gate, 4 is a control gate, 5 is a select gate, 6 is a gate oxide film, and 7 and 11 are impurity diffusion regions, respectively. . In such an EEPROM, a gate insulating film that partially has an ultra-thin tunnel oxide film is used, and depending on whether or not electrons are injected into the floating gate through this tunnel oxide film, the number of electrons in units of humans, words, etc. is remembered.

(c) For the purpose of invention or problem to be solved, the equivalent circuit of g2FLOTOX type EEFROM is
Shown in the figure. Here, the voltage applied to the tunnel oxide film Vox
.

has the following relationship with respect to the program voltage Vp.

That is, the voltage applied to the tunnel oxide film is the coupling ratio Rc = c +/(c t + c
C2 largely depends on the area of the tunnel region, and the larger Rc is, the more suitable it is for reducing the size of the device.

Second, it is more advantageous to reduce the area of the write/erase window, that is, the area of the tunnel oxide film.

However, since the area of the tunnel oxide film depends on the accuracy of microfabrication technology using photoetching, there is a limit to its reduction. Furthermore, in the conventional method, misalignment between the tunnel oxidation region and the impurity diffusion region occurs, causing a problem of increasing the cell size.

This invention was made under such circumstances, and in particular, an EEFROM having a tunnel oxide film of a minute area.
The purpose is to provide a simple and efficient manufacturing method without misalignment.

(d) Means for Solving the Problems Thus, according to the present invention, a write/il! is provided with a floating gate having a tunnel oxide film on a semiconductor substrate. forming an ion implantation mask having an ion implantation window on a semiconductor substrate on which the tunnel oxide film forms a (2L) gate oxide film; b) implanting impurity ions into the surface layer of the semiconductor substrate below the window region through the ion implantation window and the gate oxide film; (c) etching the gate oxide film of the semiconductor substrate by etching through the ion implantation window; (d) removing the substrate to form an opening-like exposed portion of the substrate wider than the window;
forming a selective oxidation layer in which the central portion corresponding to the impurity ion implantation region is oxidized and the peripheral portion is substantially non-oxidized by subjecting the exposed portion of the substrate to oxidation treatment;
) heat-treating the semiconductor substrate to form an impurity diffusion region to cover the tunnel region; (f) cleaning the non-oxidized portions of the selective oxidation layer and then oxidizing the non-oxidized portions to perform tunnel oxidation; A method of manufacturing a nonvolatile semiconductor memory device is provided, which comprises a step of obtaining a film.

In order to achieve the above object, the present invention makes it possible to form a thin tunnel oxide film in a self-aligned manner by taking advantage of the fact that an oxide film is selectively formed on a semiconductor region doped with impurities during thermal oxidation. It is composed of

(e) Effect After doping with impurities, the exposed portion of the substrate, which is formed by isotropic etching or the like, and is in the form of a wide open hole, consists of a region doped with an impurity in the center and an undoped region around it. Here, a relatively thick oxide layer is formed by thermal oxidation on the impurity-doped region, but virtually no oxide layer is formed around it (undoped region) (20 Å
below).

The width of the non-oxidized region corresponds to a region slightly expanded from the notch of the ion implantation window, and is therefore very narrow and small in area. Therefore, by subjecting this portion to tunnel oxide film formation conditions, a tunnel oxide film with a significantly reduced area can be accurately formed in a self-aligned manner.

(f) Example FIG. 1 shows an example of EEPRO! manufactured by the method of the present invention. FIG.

As shown in the figure, this EEFROM comprises a floating gate 3 and a control gate 4 made of polysilicon on a silicon semiconductor substrate 1 with a gate insulating film 6 having a tunnel oxide film 2 interposed therebetween. Note that 7 in the figure indicates each impurity diffusion region.

The manufacturing process of such an EEFROM will be described in detail below with reference to Fig. 2.

First, as shown in FIG. 2(A), a gate oxide film 6 (film thickness of about 300 μm) is formed on a P-type silicon semiconductor substrate l, a resist 8 is formed on it, and a predetermined portion of this resist 8 is formed. An ion implantation window (H) of a predetermined size is formed by photolithography.

Next, using this resist 8 as a mask, ions are implanted through the window (H) and the gate insulating film 6 to remove the substrate! The surface layer of the substrate is doped with impurity ions (for example, B ions). These impurity ions may be N-type or P-type and are determined in consideration of the conductivity type of the substrate.

The width of the doped region thus formed is the window (H)
The opening width is approximately the same as that of the opening width.

Next, through this window (H), anisotropic etching (
ion etching), followed by isotropic etching (RI
E) The gate oxide film 6 is etched (
Measure 2 (B)). As a result, a substrate exposed portion 9 is formed in the ζ gate oxide film 6, which is wider than the opening size of the window (H). In this example, the increase width (X) is approximately 0.1
It is ATM.

After forming the substrate exposed portion 9 in this manner, the substrate is subjected to thermal oxidation conditions. The thermal oxidation can be carried out, for example, by a low temperature dry oxidation method at a temperature of 700° C. or lower. Through such thermal oxidation, a thermal oxidation layer is formed on the substrate surface, especially on the exposed portion, but the formation is selectively performed on the central impurity-doped portion, and substantially no oxide layer is formed on the peripheral portion 101. (Figure 2 (C)). In this example,
An oxide layer 10 of approximately 200 layers is formed in the center, and the oxidation layer 10 of about 200 layers is formed in the periphery, at most a layer of oxide molecules below the measurement limit (20 Å or less).

Next, after etching and cleaning the peripheral portion 101, an annealing heat treatment (approximately 900° C.) is performed to thermally diffuse impurities in the impurity doped portion and form an impurity diffusion region 7 (FIG. 2(D)). ). Thereafter, by subjecting the substrate to thermal oxidation conditions again, a tunnel oxide film 2 having a thickness of approximately 80 mm is formed as shown in FIG. 2(E). The tunnel oxide film 2 has a narrow width and a small area, comparable to the width (X) in FIG. 2(B).

After forming the tunnel oxide film 2 in a self-aligned manner in this manner, a floating gate 3, a control gate 4, a select gate 5, a select gate diffusion region 11, etc. made of polysilicon are formed by a known method. , an EEPROM as shown in FIG. 4 is obtained.

(G) Effects of the Invention According to the manufacturing method of the present invention, a nonvolatile semiconductor memory device having a small-area tunnel oxide film and capable of higher integration can be easily and efficiently manufactured. Furthermore, since this tunnel oxide film is formed in a self-aligned manner, misalignment is also eliminated.

Therefore, the usefulness of this invention in this field is extremely large.

[Brief explanation of the drawing]

FIG. 1 shows the EEFR obtained by the manufacturing method of the present invention.
Main part configuration explanatory diagram illustrating OM, Fig. 2 (A)-(E)
are process explanatory diagrams of the manufacturing method of this invention, FIGS. 3 and 4.
The figures are an equivalent circuit diagram and a configuration explanatory diagram of an EEPROM, respectively. 1...Silicon semiconductor substrate, 2...Tunnel oxide film, 3...Floating gate, 4...
Control gate, 5... Select gate, 6... Gate insulating film, 8... Resist, 7.11... Impurity diffusion region, H...・・・
・Ion implantation window, 9...Substrate exposed portion, 10...
...Selective oxidation layer. My agent is a lawyer. 1 fat d vote mi R 1st Sono 4th picture

Claims (1)

[Claims] 1. A writable/erasable nonvolatile semiconductor memory device comprising a floating gate having a tunnel oxide film on a semiconductor substrate is manufactured, the tunnel oxide film comprising: (a) forming an ion implantation mask having an ion implantation window on a semiconductor substrate having a gate oxide film; (b) through the ion implantation window and the gate oxide film;
a step of implanting impurity ions into the surface layer of the semiconductor substrate below the window region; (c) etching away the gate oxide film of the semiconductor substrate by etching through the ion implantation window to form a substrate with an opening wider than the window; forming an exposed portion; (d) subjecting the exposed portion of the substrate to an oxidation treatment to form a selective oxidation layer in which the central portion corresponding to the impurity ion implantation region is oxidized and the peripheral portion is substantially non-oxidized; (e) heat-treating the semiconductor substrate to form an impurity diffusion region to cover the tunnel region; (f) cleaning the non-oxidized portions of the selective oxidation layer, and then oxidizing the non-oxidized portions; A method for manufacturing a non-volatile semiconductor memory device, comprising the steps of: processing to obtain a tunnel oxide film.