JPH03250669A - Mos-type semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To realize a MOS type semiconductor device provided with an LDD structure which is effective for suppressing the hot electron effect by making an interlayer insulating layer between a first gate electrode and a second gate electrode in a laminated structure and constituting the shape of the laminated insulating layer larger than the shape of the first gate electrode. CONSTITUTION:8-bit memory transistors 6 which are formed in series on a principal surface of a p-type silicon substrate 20 has a floating gate 14 formed on the principal surface via a first gate silicon oxide film (first gate insulating layer) 17 and a control gate 7 formed on the floating gate 14 via an interlayer insulating layer (second gate insulating layer) 25. The control gate 7 is formed longer in gate length than the floating gate 14. Further the p-type silicon substrate 20 comprises an impurity region in a so-called LDD structure comprising a highly concentrated n-type memory connection impurity diffusion layer 22 and a relatively low concentrated n-type impurity region 24 connected to the layer 22. Thus while this lead transistor 10 is operating, a hot carrier effect caused by a high electric field in the vicinity of a drain region can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type semiconductor device, and more particularly to a structure of a MOS transistor with a double gate structure and a method of manufacturing the same.

[Prior art and its problems] As one of the semiconductor devices using MOS transistors, E
EPROM (Elcct+1cally Erasa
ble and P+og+amable Read
0nly M! There is Below is this EEP
MOS with conventional double gate structure using ROM as an example
The structure of a transistor and its problems will be explained.

FIG. 9 is a block diagram showing a generally known conventional EEPRO-1 capable of writing and erasing electrical information.

Referring to FIG. 9, this EEPROM is
A memory array 50 including cells, a row address buffer 51 that receives row address signals from the outside, a column address buffer 52 that receives column address signals, and word lines and memory cells that decode these address signals and are connected to specific memory cells. A row decoder 53 and a column decoder 54 apply voltages to the bit lines, a sense amplifier 56 reads out signals stored in memory cells designated by the two decoders via a Y gate 55, and outputs the read signals. and a control signal manual buffer 5 that receives control signals from the outside and gives them to each part.
8.

In operation, sense amplifier 56 amplifies the signal stored in the memory cell and provides it to ratio buffer 57. 10
The figure shows the memory array 50 and Y shown in FIG.
5 is a circuit diagram showing an example of a gate 55. FIG.

Referring to FIG. 10, Y gate 55 includes a transistor 60 connected between I10 line 59 and bit line 31;
A transistor 63 connected between a CG line 61 and a control gate line 62 is included. A Y gate signal Y2 is applied to the gates of transistors 60 and 63. The transistors to which the Y gate signal Y1 is applied are similarly connected.

In memory array 50, 4-bit memory cells are shown. One memory cell includes a memory transistor 6 having a floating gate and a selection transistor 3 whose gate is connected to a word line 32 and which applies a signal stored in the memory transistor 6 to a bit line 31. Also,
Another selection transistor 3 a has a gate connected to the word line 32 and is connected to apply a signal from the control gate line 62 to the gate of the memory transistor 6 .

In operation, memory transistor 6 stores a binary signal depending on whether or not electrons are stored in its floating gate. When electrons are stored, the threshold voltage of memory transistor 6 becomes high. This turns off memory transistor 6 in the read operation. When no electrons are stored, the threshold voltage of the memory transistor 6 becomes negative. As a result, memory transistor 6 is turned on in a read operation.

The voltage for the subsequent outgoing connection is applied to the bit line 31 via the transistor 60, and this voltage is further applied to the memory transistor 6 via the selection transistor 3. This allows the sense amplifier to detect whether or not current flows through the memory transistor 6, and therefore allows the signal stored in the memory transistor 6 to be read.

FIG. 11 shows E E with a conventional floating gate.
FIG. 3 is a plan view of F ROM. FIG. 12 is a diagram showing a cross-sectional structure taken along the cutting line xn-xm in FIG. 11.

The structure of the EEPROM will be explained with reference to FIGS. 11 and 12.

The EEPROM includes a memory transistor 6 formed on the main surface of a p-type silicon semiconductor substrate 20 and a selection transistor 3. The memory transistor 6 includes a tunnel impurity diffusion layer 9 formed on the main surface of a semiconductor substrate 20 and serving as a drain region, and a thin tunnel insulating film formed in a predetermined region on the source region 2 and the tunnel impurity diffusion layer 9. a floating gate 14 made of polysilicon formed on the semiconductor substrate 20 via the insulating film 17 in a region including at least the tunnel insulating film 16; and an interlayer silicon oxide film 1 on the floating gate 14.
5 and a control gate 7 formed through the control gate 5.

The control gate 7, the floating gate 14, and the interlayer silicon oxide film 15 between them form a capacitor in the region where they overlap each other. floating gate 1
4, the tunnel impurity diffusion layer 9 connected to the connecting impurity diffusion layer 5, and the tunnel insulating film 16 form a capacitor. Furthermore, in the region excluding the tunnel insulating film 16,
The floating gate 14, the semiconductor substrate 20, and the insulating film near the tunnel insulating film 16 form a capacitor. Floating gate 14 stores charge. Charges are released/injected between the floating gate 14 and the tunnel impurity diffusion layer 9 via the tunnel insulating film 16 in accordance with the voltage applied between the control gate 7 and the connection impurity diffusion layer 5 . The selection transistor 3 is connected to the semiconductor substrate 2
0, a connecting impurity diffusion layer 5 and a drain region 1 are formed at intervals on the surface of the cell 0, and a selection gate electrode 4 forming a word line is formed therebetween. Selection gate electrode 4
A selection gate silicon oxide film 13 is formed between the main surface of the semiconductor substrate 20 and the main surface of the semiconductor substrate 20 . Drain region 1 is connected to bit line 31 via contact hole 11 .

Next, the operation of the EEFROM will be explained. EEPROMs have three basic modes of operation: read, erase, and write.

The table below shows the voltages applied to each element when writing, erasing, or reading information charges to the floating gate 14.

■PP is the program voltage, VF is the potential when floating, and ■. , VE indicate the potential of the floating gate 14 during each operation.

As shown in the above table, in the case of continuous output, 5V is applied to the selection gate electrode 4, 2V is applied to the bit line 31, and the control gate 7 and source line 12 are grounded.

When erasing a memory cell, Vpp is applied to selection gate electrode 4, and bit line 31 and source line 12 are grounded. During this erase cycle, a positive charge is applied onto the floating gate 14.

During writing, Vpp is applied to the selection gate electrode 4 and the bit line 31, the control gate 7 is grounded, and the source line 12 is placed in a floating state. As a result, negative charges are extracted from the floating gate 14.

In such EEPROMs, technological development is underway with the aim of increasing the storage capacity. That is, EEFR
OMs are becoming more highly integrated, and element structures are becoming finer. One of the phenomena that poses an obstacle in the miniaturization of device structures is the hot electron effect. This is M
This phenomenon has become apparent with the miniaturization of O8 field effect transistors, and refers to a phenomenon in which electrons called hot electrons are injected into the gate oxide film. That is, as the transistor structure becomes finer, a high electric field is generated particularly near the drain, and electrons generated by impact ionization are partially captured by traps in the gate oxide film and act as negative charges. The influence of this negative charge causes a decrease in reliability, such as a fluctuation in the threshold voltage of the transistor or a decrease in channel conductance. EEFROM
With the miniaturization of semiconductor devices, it is predicted that a similar hot electron effect will occur, for example, in the read transistor 10 shown in FIG. If the hot electron effect causes a change in the threshold voltage of the read transistor 10, there is a possibility that the read transistor 10 malfunctions when reading stored information. Malfunction of the read transistor 10 impairs reliability as a memory and becomes a fatal problem for the EEPROM. Note that, at present, in the EEFROM, the hot electron effect occurring in the read transistor 10 is not a big problem. However, in view of the fact that memory cell structures of EEPROMs will become more highly integrated in the future, it can be predicted that the adverse effects caused by the hot electron effect will become a serious problem. Also,
Not limited to this EEFROM, M with double gate structure
In OS transistors as well, the emergence of hot electron effects due to miniaturization of device structures poses a major problem.

In the field of MO8 field effect transistors, the so-called LDD (Lightly D
(opened drain) structure and the like are generally known. Furthermore, in the EPROM, there is an EPROM to which a structure similar to the LDD structure is applied for another purpose, as disclosed in, for example, Japanese Patent Laid-Open No. 140472/1983.

Therefore, the present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a MOS type semiconductor device having an LDD structure as a countermeasure against hot electrons, and a method for manufacturing the same.

[Means for Solving the Problems] The present invention is a MOS type semiconductor device having a double gate structure, and includes a semiconductor substrate of a first conductivity type having a main surface. A first gate insulating layer is formed on the main surface of the semiconductor substrate. A first gate electrode kept in an electrically floating state is formed on the first gate insulating layer. A second gate insulating layer having a stacked structure of first and second insulating layers is formed on the surface of the first gate electrode. A second gate electrode larger than the first gate electrode is formed along the gate length direction on the surface of the second gate insulating layer. Furthermore, a pair of relatively lightly doped second conductivity type impurity regions are formed in the semiconductor substrate so as to sandwich the first gate electrode from both sides. Furthermore, a pair of relatively high concentration second conductivity type impurities are arranged in the semiconductor substrate, facing each other in a direction away from the channel region on the surface of the semiconductor substrate sandwiched between the pair of relatively low concentration impurity regions. A region is formed.

Further, in the method of manufacturing a MOS type semiconductor device according to the present invention, first, a first insulating layer, a first conductive layer, jl! A second insulating layer and a third insulating layer are sequentially formed. Next, an etching mask of a predetermined shape is formed on the surface of the third insulating layer, the third insulating layer and the second insulating layer are patterned using the first etching method, and the first conductive layer is patterned using the mask. The layer is patterned using a second etching method having a different etching selectivity than the first etching method to form a first gate having a width narrower than the patterned third insulating layer. Then, using the patterned third insulating layer and first gate electrode as a mask, impurity ions are implanted obliquely into the main surface of the semiconductor substrate to form a relatively low concentration impurity region in the semiconductor substrate. do. Then, using the patterned third insulating layer, highly concentrated impurity ions are implanted almost perpendicularly to the main surface of the semiconductor substrate to form a relatively highly concentrated impurity region.

[Function] The MOS type semiconductor device according to the present invention includes an impurity region of a so-called LDD structure consisting of a relatively low concentration impurity region and a relatively high concentration impurity region. L.D.
The low concentration impurity region constituting the D structure prevents the hot electron effect by relaxing the concentration of electric field near the impurity region and suppressing the generation of hot electrons.

Further, in the method for manufacturing an MO3 type semiconductor device, a third insulating layer is formed on the first gate electrode, and the first gate electrode is etched using the etching selectivity between the third insulating layer and the first gate electrode. An eaves region of the third insulating layer is formed above the third insulating layer. By using the eaves-shaped part of the third insulating layer as a mask to define the boundary position between the low concentration and high concentration impurity regions, and combining this with oblique ion implantation and vertical ion implantation, LDD can be achieved in a simple process. It becomes possible to manufacture structures.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a planar structural diagram of an EEFROM memory array according to an embodiment of the present invention, and FIG. 2 is a cross-sectional structural diagram taken along the cutting line ■-■ in FIG. FIG. 3A is a cross-sectional structural diagram taken along the cutting line ■--■ in FIG. 1, and FIG. 3B is a cross-sectional structural diagram taken along the tangential plane rV-IV.

With reference to FIGS. 1 to 3B, E according to the present invention
The EPROM has an 8-bit memory transistor 6 formed in series on the main surface of a p-type silicon substrate 20, and an 8-bit memory transistor formed at one end of the memory transistor 6 for connecting it to a drain electrode 11. , and a source line 12 connected to the other end of the memory transistor 6 . Each memory transistor 6 includes a read transistor region 10 and a tunnel impurity diffusion layer 9, separated in the source/drain direction by a memory connection impurity diffusion layer 22 formed on the main surface of a semiconductor substrate 20, and perpendicular thereto. The directions are separated by an element isolation field oxide film 23. Note that the read transistor region 10 and the tunnel impurity diffusion layer 9 are separated by a region isolation field silicon oxide film 21. Each memory transistor 6 has a floating gate 14 formed on the main surface via a first gate silicon oxide film (first gate insulating layer) 17, and an interlayer insulating layer (second gate insulating layer) on the floating gate 14. 2
5 and a control gate 7 formed through the control gate 5.

Floating gate 14 and control gate 7
is made of, for example, polycrystalline silicon or metal.

Furthermore, the p-type silicon substrate 20 is provided with an impurity region having a so-called LDD structure, which is composed of a high concentration n-type memory connection impurity diffusion layer 22 and a relatively low concentration n-type impurity region 24 connected thereto. . A part of this relatively low concentration n-type impurity region 24 is connected to the floating gate 14.
A relatively high concentration memory connection impurity diffusion layer 22 extending under the interlayer insulating layer 25 is formed in substantially self-alignment with the interlayer insulating layer 25 . The reason why a part of the relatively lightly doped n-type impurity region 24 is formed under the floating gate 14 is because the positions of the lightly doped n-type impurity region 24 and the floating gate 14 are offset for each read transistor. This is to prevent the reliability of the transistors from deteriorating because the characteristics of each lead transistor will differ if the conditions are different or overlap. The interlayer insulating layer 25 has a laminated structure including an interlayer insulating oxide film 25a covering the floating gate 14 and an interlayer insulating nitride film 25b formed on the upper surface thereof.

Furthermore, the control gate 7 formed on the surface of the interlayer insulating layer 25 is formed to have a longer gate length than the floating gate 14 .

Further, the tunnel impurity diffusion layer region includes an n-type tunnel impurity diffusion layer 9 in the p-type silicon substrate 20 . A floating gate 14 is provided on the surface of this tunnel impurity diffusion layer 9 via a tunnel oxide film 16 which is thinner than the first gate silicon oxide film 17 of the read transistor 10.
is formed. The floating gate 14 is connected to the Fowler-N via the tunnel insulating film 16.
Charge injection is performed by ordheim tunneling.

Further, a region on the surface of the p-type silicon substrate 20 is covered with a thick insulating layer 26 with thermally oxidized pus 40 interposed therebetween. The insulating layer 26 contains impurities such as boron therein. This impurity serves to flatten the surface of the insulating layer 26 by lowering the viscosity of the insulating layer 26. Therefore, oxide film 40 is provided to prevent impurities in insulating layer 26 from entering control gate 7 .

As described above, the feature of the present invention in the EEPROM described above is that the so-called LDD structure is applied to the impurity region of the υ-doped transistor 10. This makes it possible to suppress the hot carrier effect generated by the high electric field near the drain region during the operation of the read transistor 10. Note that in the above embodiment, NA
It shows the memory cell structure of NDW EEPROM,
Regarding this, the same applicant's previous eight patent applications No. 63173
402 in detail.

Next, the manufacturing process of the EEFROM memory cell, particularly the read transistor 10 shown in FIG. 3A, will be explained with reference to FIGS. 48 to 4F.

Referring to FIG. 4A, a field oxide film (not shown) is formed in a predetermined region on the surface of p-type silicon substrate 20 by selective oxidation. Thereafter, a first gate silicon oxide film 17 is formed on the surface of the p-type silicon substrate 20 by thermal oxidation. Further, on the surface of the first silicon oxide film 17, C
A polycrystalline silicon layer 14a is formed by the VD method. Furthermore, an oxide film 25a1 is formed on the surface of the polycrystalline silicon layer 14a.
and a silicon nitride film (S13N4) 25b are sequentially formed.

Next, referring to FIG. 4B, nitriding [25b] is performed using a photolithography method and an etching method.

Oxide film 25a and polycrystalline silicon layer 14a are patterned into a predetermined shape. This etching process is divided into two etching processes. The first etching step is (
The nitride film 25b1 and the oxide film 25a are etched to predetermined dimensions using plasma etching in an atmosphere of CHF3+O2'. Next, in the second etching step, the etching gas is (Freon 114 (C2Cl3 F4) + 5F
The polycrystalline silicon layer 14a is etched by performing plasma etching in an atmosphere containing a mixture of 1.2 and 2.s). In this second etching step, the nitride film 25b patterned in the first etching step,
Since the selectivity of oxide film 25a and polycrystalline silicon layer 1.4a is different, only polycrystalline silicon layer 14a is etched. By controlling the etching time, it is possible to form a floating gate 14 in which the polycrystalline silicon layer 14a is set back from the width of the patterned nitride film 25b. That is, a nitride film 25b and an oxide film 25a having an eave-like protruding portion are formed on the surface of the floating gate 14. In addition,
The protruding portion of this nitride film 25b is approximately 1000 to 3000A.
Formed to a certain degree.

Furthermore, as shown in FIG. 4C, using the patterned silicon nitride film 25b as a mask, the p-type silicon substrate 2
Low concentration n-type impurity ions 27 are implanted into the surface of the substrate 0 using an oblique rotational ion implantation method. Through this step, low concentration impurity regions 24 and 24 are formed in the p-type silicon substrate 20.

Note that the oblique rotational ion implantation method involves tilting the silicon substrate at a predetermined angle and facing it with respect to the emission direction of impurity ions.
In this method, the silicon substrate is further rotated around an axis perpendicular to the main surface of the substrate to perform ion implantation. In this step, for example, the length of the protrusion of the nitride film 25b is set to 30
In the oblique ion implantation process, the rotation speed of the substrate is 1.7 rps, the implantation angle is 45°, the implantation energy is 40keV, and the implantation dose is 3X1013/Cm2.
In this case, the amount of overlap between the lightly doped n-type impurity region 24 and the floating gate 14 is approximately 0.15μ.
formed in m.

Next, as shown in FIG. 4D, low-temperature wet oxidation at about 800° C. is performed to form a sidewall oxide film 28 on the sidewalls of the floating gate 14 and the like.

In this thermal oxidation, a thin oxide film is also formed on the surfaces of silicon nitride film 25b and oxide film 25a.

Furthermore, as shown in FIG. 4E, a polycrystalline silicon layer is formed using the CVD method and patterned into a predetermined shape using a resist pattern 29. As shown in FIG.

As a result, control gate 7 is formed.

The film thickness of control gate 7 is approximately 2000 to 3000
It is about A.

Thereafter, as shown in FIG. 4F, the resist pattern 29
Using control gate 7 and sidewall oxide film 28 as a mask, n-type impurity ions 30 are implanted at a high concentration into the surface of p-type silicon substrate 20 almost perpendicularly to the surface of silicon substrate 20 . As a result, the high concentration impurity region 22.2
2 is formed. Then, a so-called LDD structure is completed.

As described above, in the above manufacturing method, the sidewall oxide film 28 is used as a mask to configure the LDD structure, and the oblique rotational ion implantation method for the low concentration impurity region and the vertical ion implantation method for the high concentration impurity region are combined. Manufactured together. The sidewall oxide film 28 is controlled by the film thickness on the sidewall of the floating gate 14 or the oxidation resistance of the silicon nitride film 25b. Therefore, the diffusion width of the relatively low concentration impurity region 24 can be controlled by the thickness of the sidewall oxide film 28, that is, the length of the paper portion of the silicon nitride film 25b. Further, this sidewall oxide film 28 is formed by thermal oxidation treatment at a relatively low temperature. As a result, the p-type silicon substrate 2
Unnecessary reduction in the channel length due to thermal diffusion of the lightly doped impurity region 24 formed in the 0-200 nm can be prevented. Further, the interlayer insulating layer 25 has a laminated structure of an oxide film 25a and a nitride film 25b. The oxide film 25a is usually formed by a thermal oxidation method. However, since this thermal oxidation method involves high-temperature processing, diffusion of the impurity region in the silicon substrate 20 occurs in the same manner as described above. Therefore, in the present invention, the thermal oxidation treatment time of the silicon oxide film 25a is shortened, the film thickness of the oxide film 25a is suppressed to about 200 to 300A, and furthermore, in order to ensure the insulation properties as an interlayer insulating layer,
The air nitride film 25b is laminated to a certain extent. Further, on the surface of this nitride film 25b, several dozen thin oxide films are formed at the same time when the sidewall oxide film 28 is formed.

This makes it possible to compensate for defects such as pinholes that are likely to be formed in the thin nitride film 25b.

As described above, the lead transistor of the EEF ROM memory cell can be formed by using the steps shown in FIGS. 4A to 4F, but these steps can be applied directly to the general MOS
) Can be used in the transistor manufacturing process.

Next, a modification of the manufacturing process of the read transistor will be described. FIG. 5A is a cross-sectional structural diagram showing the process of forming the highly-concentrated impurity region 22. FIG. This step is the fourth step mentioned above.
This step is performed subsequent to the step of forming the lightly doped impurity region 24 shown in FIG. That is, using the nitride film 25b having an eave-like protrusion as a mask, n-type impurity ions 30 are
Ions are implanted into the surface of the silicon substrate 20 at a high concentration. As a result, high concentration impurity regions 22.22 are formed which are self-aligned with the nitride film 25b.

Furthermore, another modification is shown using FIG. 5B.

This step is performed after the step of forming the sidewall oxide film 28 shown in FIG. 4D. That is, the process of forming the high concentration impurity region 22 involves forming the sidewall oxide film 28 and the nitride film 25.
It is formed by vertical ion implantation using a mask such as b. As a result, an impurity region having an LDD structure is formed in the silicon substrate 20. After this, control gate 7 is formed on the surface of nitride film 25b.

Next, another embodiment of the read transistor 10 of the EEPROM memory cell according to the present invention will be described. 6 is a cross-sectional structural diagram taken along the cutting line IF-If in FIG. 1, and FIG. 7 is a cross-sectional structural diagram taken along the cutting line m-m in FIG. It is a diagram. The read transistor 10 according to this example is formed such that an interlayer insulating oxide film 25a, an interlayer insulating nitride film 25b, and a control gate 7 cover a part of the side wall of the floating gate 14. The impurity regions of the read transistor 10 include a low concentration n-type impurity region 24, 24 that is self-aligned with the floating gate 14, and a high concentration n-type impurity region that is self-aligned with the control gate 7 or the interlayer insulating nitride film 25b.
It has an LDD structure consisting of type impurity regions 22 and 22. The interlayer insulating layer 25 has a laminated structure of a silicon oxide film 25a and a silicon nitride film 25b. - When the silicon oxide film 25a is formed on the top surface and side walls of the floating gate 14 for boat fishing, a phenomenon occurs in which the thickness of the silicon oxide film 25a becomes thinner at the corners of the floating gate 14 having a rectangular cross section. In such a case, the silicon oxide film 25
In the case of a single layer film a, electric field concentration occurs around the corners, which tends to cause dielectric breakdown. However, in the present invention, by forming the silicon nitride film 25a on the surface of the silicon oxide film 25a, a predetermined thickness of the insulating layer is ensured and deterioration of the dielectric breakdown voltage is prevented.

Next, the manufacturing process of the read transistor 10 shown in FIG. 7 will be explained using FIGS. 88 to 8E.

First, as shown in FIG. 8A, a field isolation oxide film (not shown) is formed in a predetermined region on the surface of the p-type silicon substrate 20 by selective oxidation. Furthermore, a first gate silicon oxide film 17 is formed on the surface of the p-type silicon substrate 20 using a thermal oxidation method.

Further, a polycrystalline silicon layer 14a is formed on the surface using the CVD method.

Next, as shown in FIG. 8B, the polycrystalline silicon layer 14a is patterned into a predetermined shape using the patterned resist 31 using photolithography and etching as a mask. As a result, floating gate 14 is formed.

Furthermore, resist 31 and floating gate 14
Using as a mask, n-type impurity ions 27 are implanted at a low concentration into the surface of the p-type silicon substrate 20. As a result, relatively low concentration n-type impurity regions 24 and 24 are formed.

Furthermore, as shown in FIG. 8C, a silicon oxide film 25a and a silicon nitride film 25b are formed on the surface of the silicon substrate 20.
are formed sequentially.

Then, as shown in FIG. 8D, the resist pattern 32
Using the mask as a mask, the silicon nitride film 25b and the silicon oxide film 25a are patterned into a predetermined shape. The patterned silicon nitride film 25b and silicon oxide film 25a are patterned to cover the surface and side surfaces of the floating gate 14. Then, high concentration n-type impurity ions 30 are implanted into the surface of the p-type silicon substrate 20 using the resist pattern 32 or the patterned silicon nitride film 25b as a mask. As a result, highly concentrated n-type impurity regions 22.22 are formed. Then, an impurity region having a so-called LDD structure is completed.

Then, as shown in FIG. 8E, after removing the resist 32, a polysilicon layer is deposited on the entire surface and patterned into a predetermined shape. Thereby, polysilicon control gate 7 is formed on the surface of silicon nitride film 25b. Through the above steps, a read transistor 10 having an impurity region having an LDD structure is manufactured.

In the above embodiments, the read transistor 10 formed on the p-type silicon substrate 20 has been described, but the invention is not limited to this, and for example, a read transistor 10 formed in a well region or a transistor of the opposite conductivity type may be used. It may also be formed on a silicon substrate having a silicon substrate.

[Effects of the Invention] As described above, in the MO3 type semiconductor device according to the present invention, in a transistor having a double gate structure, the interlayer insulating layer between the first gate electrode and the second gate electrode has a laminated structure, By configuring the shape of this laminated insulating layer to be larger than the shape of the first gate electrode, a so-called LDD structure is constructed in the semiconductor substrate. Therefore, without using processes such as sidewall formation, M
An O3 type semiconductor device can be realized.

[Brief explanation of drawings]

FIG. 1 is a plan view of a memory cell of an EEPROM according to an embodiment of the present invention. FIG. 2 is a cross-sectional structural diagram taken along the cutting line ■-■ in FIG. 1. Third
Figure A is a cross-sectional structural view taken along the cutting line ■-■. FIG. 3B is a cross-sectional structural view taken along the cutting line IV-rV. 4A, 4B, 4C, 4D, 4E, and 4F are cross-sectional views of the manufacturing process of the read transistor of the EEPROM memory cell shown in FIG. 3. Figure 5A is
FIG. 4F is a manufacturing process sectional view showing a modification of the manufacturing process shown in FIGS. Furthermore, FIG. 5B is a manufacturing process sectional view showing still another modification. FIG. 6 is a cross-sectional structure diagram of a memory cell of an EEPROM according to another embodiment of the present invention, and in particular corresponds to the cross-sectional structure taken from the direction along the cutting line -H in the diagram shown in FIG. It is something. Furthermore, like FIG. 6, FIG. 7 is a cross-sectional structural diagram corresponding to the cross-sectional structure taken along the cutting line mm in FIG. 1. 8A, 8B, 8C, 8D, and 8E are sectional views showing the manufacturing process of the read transistor 10 shown in FIG. 7. FIG. 9 is a block diagram showing the configuration of a boat fishing EEPROM. FIG. 10 shows the EEFROM shown in FIG.
FIG. 2 is an equivalent circuit diagram of a memory cell array of FIG. Figure 11 shows
10 is a partial plan view of the structure of the memory cell shown in FIG. 10; FIG. FIG. 12 is a schematic cross-sectional structural diagram taken along the cutting line x--xn in FIG. 11. In the figure, 6 is a memory transistor, 7 is a control gate, 9 is a tunnel impurity diffusion layer, 10 is a read transistor, 14 is a floating gate, 16 is a tunnel insulating film, 17 is a first gate silicon oxide film, and 20 is p-type silicon 22 is a memory connection impurity diffusion layer (high concentration impurity region), 24 is a low concentration impurity region, 25 is an interlayer insulating layer, 25a is an interlayer insulating oxide film, 25b is an interlayer insulating nitride film, 27 is an n-type impurity ion, Reference numeral 28 indicates a sidewall oxide film. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Patent a applicant: Mitsubishi Electric Corporation.

Claims (2)

[Claims] (1) A MOS type semiconductor device having a double gate structure, comprising: a semiconductor substrate of a first conductivity type having a main surface; a first gate insulating layer formed on the main surface of the semiconductor substrate; a first gate electrode formed on the top of one gate insulating layer and maintained in an electrically floating state; and a first gate electrode formed on the surface of the first gate electrode and having a laminated structure of a first and a second insulating layer. a second gate electrode formed on the surface of the second gate insulating layer and larger than the first gate electrode along the gate length direction; and a second gate electrode formed on the surface of the second gate insulating layer; a pair of relatively low concentration impurity regions of a second conductivity type formed in the semiconductor substrate so as to be sandwiched therebetween; and the semiconductor substrate sandwiched between the pair of relatively low concentration impurity regions. a pair of relatively high concentration second conductivity type impurity regions formed in the semiconductor substrate and facing each other in a direction away from a channel region on the surface;
type semiconductor device. (2) A method for manufacturing a MOS type semiconductor device having a double gate structure, which comprises: forming a first insulating layer, a first conductive layer, a second conductive layer on the main surface of a semiconductor substrate;
forming an etching mask of a predetermined shape on the surface of the third insulating layer, and etching the third insulating layer and the second insulating layer using the mask; patterning using a first etching method, and further patterning the first conductive layer using a second etching method having a different selectivity from the first etching method, so that the patterned third insulating layer forming a narrow first gate electrode; using the patterned third insulating layer and the first gate electrode as a mask, impurity ions are implanted obliquely into the main surface of the semiconductor substrate; forming a relatively low-concentration impurity region in the semiconductor substrate; and ion-implanting high-concentration impurity ions almost perpendicularly to the main surface of the semiconductor substrate using the patterned third insulating layer. and forming a relatively high concentration impurity region.