JPH04188626A - Method of thermally treating compound semiconductor wafer - Google Patents

Abstract

PURPOSE: To uniformize As deposit distributed on the surface and in the inside of a GaAs wafer by utilizing the liquid shape of Ga solution for which poly- crystalline GaAs is dissolved and heat-treating the GaAs wafer. CONSTITUTION: After positioning a compound semiconductor wafer 11 at the groove 13 of a slider 15, putting a sample 21 into the well 19 of a holder 17 and sealing the entrance of the well 19 by a sealing material 23, primary heat is applied and the sample 21 is melted. Then, after moving the slider 15, matching the groove 13 and the well 19 and making the molten sample 21 cover the entire surface of the wafer 11, secondary heat is applied and the surface of the wafer 11 is homogenized. Then, after separating the groove 13 and the well 19 and rapidly cooling them at a normal temperature, tertiary heat is applied and heat induction stress is removed. Thus, the As deposit is uniformly distributed on the surface of the wafer 11 and in the inside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for heat treating compound semiconductor wafers, and particularly to a method for heat treating compound semiconductor wafers containing highly volatile elements.

(Prior Art) With the recent rapid development of information and communication society, the need for ultra-high speed computers, ultra-high frequency and optical communication has further increased. However, existing elements using Sl have a limit in that they cannot meet these requirements. Therefore, research into compound semiconductors with excellent material properties is actively progressing.

When an ingot of GaAs, which is a typical compound semiconductor, grows, defects such as dislocation vacancy lattice points, interstitial rings f-, and As precipitates occur inside the crystal.

Since such defects are unevenly distributed within the crystal, the general L
When devices are manufactured using wafers made from ingots produced by the EC (encapsulated liquid) method, device characteristics become non-uniform and reliability decreases. Therefore, the wafer is subjected to a predetermined heat treatment to uniformly distribute defects and the like so that it has uniform electrical characteristics.

FIG. 2 shows a conventional heat treatment method for compound semiconductor wafers. First, a protective wafer 3 of the same type as the heat treatment wafer 1 is brought into contact with both sides of the heat treatment wafer 1, and the wafer 1 and the excess sample 5 are placed in a tube 7 made of quartz or the like.

Next, the inside of the tube 7 is evacuated and sealed, and then the tube 7 is heated with a heater 9 and maintained at about 800 to 900° C. for several tens of minutes to several hours, and then cooled. In the above heat treatment wafer 1, since the volatilization temperature of As is much lower than that of Ga in the case of GaAs, volatilization of As easily occurs during the heat treatment process. Therefore, the excess sample 5 is used to create an As atmosphere inside the tube 7 in a vacuum state, and the wafer 1 for heat treatment is
This suppresses As from volatilizing. Furthermore, the protective wafer 3 and the like not only suppress the volatilization of As in the heat treatment wafer 1, but also supply As to the heat treatment wafer 1. The reason why the tube 7 is evacuated before performing the heat treatment process is to prevent the heat treatment wafer 1 from being oxidized and contaminated.

In the above-described heat treatment method, heat is applied to the inside of a tube in a vacuum state to turn As into a gaseous state, and the composition of As within the wafer is controlled by the As gas pressure.

(Problems to be Solved by the Invention) However, As precipitates are unevenly distributed on the wafer before the heat treatment process is performed. When performing a heat treatment process due to the non-uniformly distributed As precipitates, it is difficult to uniformly volatilize and internally diffuse As on the surface of the wafer. Furthermore, when a heat treatment process is performed on a non-uniform interface between a solid and a gas, defects such as surface roughness and empty lattice points may occur non-uniformly.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for heat treating a compound semiconductor wafer, which allows As precipitates to be uniformly distributed on the surface of the wafer and inside the wafer.

Another object of the present invention is to provide a method for heat-treating a compound semiconductor wafer in which defects such as vacancy lattice points and surface roughness can be uniformly distributed.

[Structure of the Invention] (Means for Solving the Problems) This invention for achieving the above objective 1 is a method for heat treatment of a compound semiconductor wafer containing a highly volatile element. the sample is placed in the well of the holder, the entrance of the well is sealed with a sealing material, and the sample is melted by applying primary heat, and the slider is moved to align the groove and the well to melt the sample. After the sample was made to cover the entire surface of the compound semiconductor wafer, there was a step of applying secondary heat to homogenize the surface of the compound semiconductor wafer, and separating the grooves and wells and rapidly cooling them at room temperature. The method is characterized by comprising a step of applying tertiary heat to remove thermally induced stress.

(Example) Hereinafter, the present invention will be described in detail with reference to the attached drawings.

FIGS. 1A to 1C show a method of heat treating compound semiconductor wafers according to the present invention. Referring to FIG. 1A, semi-insulating GaA prepared by a predetermined cleaning process
Position the S wafer 11 in the groove 13 of the slider 15,
10 g to maintain the stoichiometry of this wafer 7111.
A sample 21 mixed with 300 to 1000 mg of polycrystalline GaAs per Ga is placed in the well 19 of the holder 17, and after sealing the second well 19 with a sealing material 23, the sample 21 is pushed into the reaction tube 25 of an electric furnace. Above 13 wafers
1 is positioned with a gap t of about 50 μm. Further, in the electric furnace, the outside of the reaction tube 25 is covered with a heater 27 so as to maintain a uniform temperature distribution.

Next, the heater 27 is heated to maintain the temperature of the reaction tube 25 at about 600 to 700° C. for 1 to 5 hours. At this time, the above-mentioned sample 21 etc. are melted, and the Ga contained in Ga is
2O3 is slagged with the sealant 23. In the above, the sealing material 23 is usually B20. is used in cake form.

In the above, 8203 has a H and O content of 200 to 400 p.
The amount of Ga2O produced by the reaction between the molten sample 21 and oxygen is reduced so that the molten sample 21 is in a rolling state of about pm.

Referring to FIG. 1B, when the slider 15 is moved to align the groove 13 with the well 19, the surface of the wafer 11 is covered with the molten sample 21. Next, when the temperature is raised to 900° C. or more and maintained for 2 to 5 hours, the As precipitates that were unevenly distributed on the surface of Ueno 111 are re-resolved. Referring to FIG. 1C, the slider 1
5 to a predetermined position to separate the groove 13 and the well 19, and then cooled to room temperature at a cooling rate of 300 to 1200° C./hr. At this time, an epitaxial layer having a void thickness t is formed on the surface of the Ueno\11. Since the epitaxial layer 29 is rapidly cooled in the above manner, the diffusion time of As is minimized, and As precipitates are reprecipitated in a small and uniform size.

Furthermore, during the cooling process, there is a large amount of residual stress due to heat between the Ueno X11 and the epitaxial layer 29.

Therefore, the heater 27 is heated again and maintained at a temperature of about 600 to 700° C. for 5 to 30 hours to remove the thermally induced residual stress between the wafer 11 and the epitaxial layer 29. At this time, As is diffused centering around the small and uniformly sized nuclei reprecipitated during the rapid cooling, and As precipitates of uniform size are formed.

Next, after cooling the wafer 11, a polishing process is performed to remove the epitaxial layer 29 formed on the surface to form a wafer with a good quality mirror surface. Additionally, defects such as empty lattice points on the surface and inside of the wafer and roughness on the surface of the wafer are removed during the heat treatment process described above.

As mentioned above, GaAs was explained as an example of the present invention, but as long as it does not deviate from the idea of this invention, InAs, In
It can also be applied to P, GaP, etc.

〔Effect of the invention〕

Therefore, as mentioned above, in this invention, a GaAs wafer is heat-treated using a liquid Ga solution in which polycrystalline GaAS is dissolved, so that As precipitates and defects distributed on the surface and inside of this GaAs wafer are uniformized. This has the advantage of uniform electrical characteristics.

[Brief explanation of the drawing]

1A to 1C show semi-insulating GaAs according to the present invention.
A diagram showing a method of heat treatment of wafers, FIG. 2 shows conventional semi-insulating GaAs. / % is a diagram showing a heat treatment method. 11...Compound semiconductor one;-ノ＼ 13...Groove 15...Slider 17...Holder 19...Well 2]...Sample 23...Sealing material 25...Reaction tube 27 ...Heater 29...Epitaxial layer FIG, 1 (C)

Claims (1)

[Claims] (1) In a heat treatment method for a compound semiconductor wafer containing a highly volatile substance, the compound semiconductor wafer is positioned in a groove of a slider, a sample is placed in a well of a holder, and the entrance of the well is sealed with a sealing material. After that, a first heat is applied to melt the sample, and a second heat is applied after the slider is moved to match the groove and the well so that the melted sample covers the entire surface of the compound semiconductor wafer. A compound semiconductor wafer comprising the steps of: homogenizing the surface of the compound semiconductor wafer by adding a heat treatment method. (2) The method for heat treatment of a compound semiconductor wafer according to claim (1), wherein the depth of the groove is adjusted so as to have a gap of about 50 μm with the compound semiconductor wafer. (3) The sample is a polycrystalline material with the same composition as a compound semiconductor wafer per 10 g of a highly volatile non-material.
2. The method for heat treatment of a compound semiconductor wafer according to claim 1, wherein the materials are mixed at a ratio of 1000 mg. (4) The method for heat treating a compound semiconductor wafer according to claim (1), wherein the sealing material is B_2O_3. (5) B_2O_3 has a water content of 200 to 400p
5. The method for heat treatment of a compound semiconductor wafer according to claim 4, wherein the heat treatment method is about pm. (6) The method for heat treatment of a compound semiconductor wafer according to claim (1), wherein the first heat is applied so that the sample is maintained at 600 to 700°C for 1 to 5 hours. (7) Claim (1) characterized in that the secondary heat is applied so that the sample is maintained at 900°C or higher for 2 to 5 hours.
) A method for heat treatment of a compound semiconductor wafer as described in . (8) The method for heat treatment of a compound semiconductor wafer according to claim (1), characterized in that the compound semiconductor wafer is rapidly cooled to room temperature in the step of removing stress at a cooling rate of 300 to 1200° C./hr. (9) The method for heat treatment of a compound semiconductor wafer according to claim (1), wherein the compound semiconductor wafer is a III-V group compound semiconductor wafer. (10) The method for heat treatment of a compound semiconductor wafer according to claim 9, wherein the III-V compound semiconductor wafer is one of GaAs, InAs, GaP, and InP.