KR20090059251A - Method of fabricating high resistivity silicon wafer - Google Patents

Abstract

A method for manufacturing a silicon wafer with high resistivity is provided to remove the contaminated part of the silicon wafer in a thermal process by removing the silicon wafer surface part with an oxide film after the thermal process. An oxide film with the thickness of 50 - 150 angstrom is formed in a silicon wafer surface(S1). The silicon wafer is thermally processed(S2). The oxide film and the silicon wafer surface within 5 um are removed(S3). The oxide film is removed by the hydrofluoric acid solution or the BOE(Buffered Oxide Etchant). The silicon wafer surface is physically removed by using a polishing device.

Description

Method of fabricating high resistance silicon wafer {Method of fabricating high resistivity silicon wafer}

The present invention relates to a silicon wafer manufacturing method, and more particularly to a high resistance silicon wafer manufacturing method.

High-resistance silicon wafers are used in the manufacture of radio frequency (RF) devices and integrated passive devices (IPDs), which are essential for wireless communication devices. Conventionally, high resistance silicon wafers manufactured by the floating zone (FZ) method were mainly used. However, in view of large diameter and uniform resistance of the silicon wafer, the silicon wafers manufactured by the Czochralski (CZ) method were heat treated. There is a tendency to use a lot of high-resistance silicon wafer to manufacture.

In the CZ method, oxygen is mixed into the molten metal from the quartz crucible and oxygen is mixed into the grown silicon single crystal ingot. Therefore, the lattice oxygen is present at a high concentration in the silicon wafer which cuts and manufactures the single crystal ingot, and the mixed oxygen is 400 to 450, which is a temperature when the sintering heat treatment is performed after metal deposition in the semiconductor device manufacturing process. It develops into a thermal donor at 占 폚, reducing the substrate resistance. Therefore, in order to fabricate a high-resistance silicon wafer having a resistivity of 100 Ω · cm or more, it is necessary to adjust the mixed oxygen to a predetermined content or less so that the oxygen does not act as a thermal donor. Doing.

However, since boron (B) is adsorbed on the surface of the silicon wafer after being adsorbed to the surface of the silicon wafer in the atmosphere or in the air, and then diffused into the bulk of the silicon wafer during the high temperature heat treatment process, lowering the specific resistance of the bulk region from the surface of the silicon wafer. The so-called "boron pileup phenomenon" occurs. In order to further increase the resistivity, a long time high temperature heat treatment is required, thereby increasing the possibility of boron pile up due to the silicon wafer surface contamination.

To date, there is no way to control this phenomenon in the field of high-resistance silicon wafers. However, a method of removing a natural oxide film on a contaminated silicon wafer surface, which is a method used to control impurities in the manufacture of an anneal silicon wafer or an Altipy (RTP) heat-treated silicon wafer, which generally requires high temperature heat treatment, It is thought only to be available.

When manufacturing annealing silicon wafer or Altipi heat treatment silicon wafer, it is mainly used to remove the natural oxide film adsorbed by the pollutant before the heat treatment with hydrofluoric acid (HF) solution and to burn with hydrogen (H ₂ ) gas during heat treatment. come. In the case of annealed silicon wafers or Altipi silicon wafers, although the subsequent heat treatment is high temperature, but the heat treatment time is not long, the diffusion distance is shortened, so that simply removing the contaminated area before or during the heat treatment usually controls this phenomenon. Can be reduced.

However, in removing the natural oxide film before the heat treatment, it is impossible to completely remove the source of contamination, rather it is more likely to be externally contaminated during or after the hydrofluoric acid removal process. Pollutants that cannot be completely removed during the heat treatment process are diffused to the outside or into the bulk of the silicon wafer, so that the pollutant is deposited in the silicon wafer bulk after the heat treatment. As the diffusion is repeated, the spreading distance into the bulk becomes very deep, and the control of the boron pile-up phenomenon is not easy.

The problem to be solved by the present invention is to provide a method for controlling the phenomenon that the specific resistance of the surface of the silicon wafer is lowered by external contamination in the development of a high resistance silicon wafer having a uniform high specific resistance.

In order to solve the above problems, the present invention can protect the surface of the silicon wafer from an external contaminant, and propose a method of controlling the external contaminant when it is diffused into the silicon wafer bulk. A high resistance silicon wafer manufacturing method according to the present invention comprises the steps of: forming an oxide film having a thickness of 50 ~ 150 에 on the silicon wafer surface; Heat-treating the silicon wafer on which the oxide film is formed; And removing the oxide film and the silicon wafer surface portion within 5 μm.

According to the present invention, by forming an oxide film to protect the surface of the silicon wafer, it is possible to further prevent contamination of the inside of the silicon wafer during the heat treatment process. Since the silicon wafer surface portion is removed together with the oxide film after the heat treatment, even if the inside of the silicon wafer is contaminated during heat treatment due to incomplete removal of the contaminant, the contaminated portion does not exist in the silicon wafer in the final state. Therefore, there is no region contaminated with boron and the like, so that the resistivity is reduced, and thus a high resistivity silicon wafer can be manufactured in which the resistivity is maintained evenly at a high level as a whole.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, only this embodiment is to complete the disclosure of the present invention, those skilled in the art to which the present invention belongs It is provided to fully inform the scope of the invention, and the invention is defined only by the scope of the claims.

In order to prevent contamination from external sources as much as possible, the present invention proposes to form a thick protective film on the silicon wafer surface before heat treatment. This is in contrast to the removal of the native oxide film on the contaminated silicon wafer surface from conventional anneal silicon wafers or Altipi heat treated silicon wafers. The thick protective film is an oxide film, which can prevent contamination of the silicon wafer surface and inside or before the heat treatment.

1 is a flowchart of a method of manufacturing a high resistance silicon wafer according to the present invention, and FIG. 2 is a cross-sectional view of the process sequence of the method of manufacturing a high resistance silicon wafer according to the present invention.

First, the silicon wafer 10 is prepared by performing a process such as cutting, polishing, and cleaning the silicon ingot (FIG. 2A). Although it is better that the silicon wafer 10 is clean without being contaminated, some sources of contamination may be attached to the surface of the silicon wafer 10 due to exposure to outside air.

Next, an oxide film 20 having a thickness of 50 to 150 GPa is formed on the surface of the silicon wafer 10 (step s1 in FIG. 1 and (b) in FIG. 2). The oxide film 20 may be formed using an existing general oxide film forming apparatus, and may be a separate film deposition apparatus or a heat treatment furnace in an oxidizing atmosphere in which general heat treatment may be performed. It is preferable to grow the oxide film 20 at a low temperature of 700 ° C. or lower to shield it from external contamination, and it is important to form a high quality oxide film (high density) to eliminate any possibility of contamination. Thicknesses less than 50 mm may be vulnerable to penetration of external contaminants and thicknesses greater than 150 mm will be 50 to 150 mm 3 because they are somewhat inconvenient to remove in subsequent processes. Preferably, it is formed at about 100 kPa.

Although there is a possibility that some contamination sources exist during the unintentional contamination of the silicon wafer 10 itself and the formation of the oxide film 20, the contamination source 30 may be included in the oxide film 20 as shown in FIG. The oxide film 20 can be prevented from further contaminating the surface of the silicon wafer 10 from external contamination sources, so that the oxide film 20 primarily protects the surface of the silicon wafer 10.

The silicon wafer 10 on which the oxide film 20 is formed is heat-treated (step s2 in FIG. 1 and (d) in FIG. 2). The heat treatment herein refers to a general heat treatment performed to make a high-resistance silicon wafer, and in detail, a heat cycle including a heat treatment for forming a dezoned zone (DZ) and a heat treatment for forming a bulk micro defect (BMD) is used. It may be.

The reason for the long diffusion region in the silicon wafer bulk is when the source of contamination is continuously supplied to the surface of the silicon wafer during the heat treatment process. Therefore, if the source of contamination does not exist on the surface of the silicon wafer, the boron pile-up phenomenon is weak. do. The pollutant 30 included in the oxide film 20 and / or the external pollutant 35 such as boron included in the heat treatment atmosphere may enter the bulk of the silicon wafer 10, but may not penetrate the external pollutant 35 during the heat treatment process. In some respects, the oxide film 20 protects the silicon wafer 10. In other words, at least an external contaminant 35 such as boron penetrates the oxide film 20 into the silicon wafer 10 and is newly blocked.

After completion of the heat treatment, the oxide film 20 and the silicon wafer surface portion 10 'within 5 µm are removed (steps s3 in FIG. 1 and (e) and (f) in FIG. 1).

First, the oxide film 20 is removed as shown in Fig. 2E. When the oxide film 20 is removed by an aqueous hydrofluoric acid solution or a buffered oxide etchant (BOE), contaminants 30 and 35 other than the contaminant in some silicon wafer bulks may be removed together with the oxide film 20. Some contaminants 30, 35 may be present within a certain depth d from the silicon surface portion 10 ', ie, the silicon wafer 10 surface.

Next, the silicon wafer surface portion 10 'is removed. It can be seen to remove the boron pile up area where the resistivity concentration is slightly lower. The polishing apparatus used in the last step of the current silicon wafer processing process is used to physically remove a portion of the surface of the silicon wafer to obtain a silicon wafer 10a having a uniform resistivity.

Although the present invention proceeds in the direction of removing further contamination by forming the oxide film 20 in a state in which the surface of the silicon wafer 10 is partially contaminated from external contamination, the source of contamination is not completely removed. In addition, even if completely removed before the heat treatment does not exclude the possibility of diffusion into the bulk of the silicon wafer 10 when there is a source of contamination during the heat treatment process. In the case of high-resistance silicon wafers, it is necessary to completely control the boron pile-up phenomenon in order to guarantee the resistivity during the high temperature heat treatment process. Therefore, in order to achieve perfection, the surface of the silicon wafer is physically removed so that the entire silicon wafer can have a uniform resistivity distribution.

Here, the removed portion is a silicon wafer surface portion 10 ′ within 5 μm, and 5 μm corresponds to a thickness of a general boron pile up portion of a high resistance silicon wafer manufactured by a conventional manufacturing method. When the oxide film 20 is formed as described above, the boron pile up portion may have a smaller thickness. Therefore, the thickness to be removed is up to 5㎛ and the minimum is not significant because it depends on the thickness of the oxide film 20 and the heat treatment environment.

3 is a graph showing a boron pile up phenomenon as a resistivity graph measured in a depth direction from a surface of a conventional high resistance silicon wafer. As shown by the dotted circle, the portion where the specific resistance is reduced from the surface of the silicon wafer to a predetermined depth occurs.

4 is a resistivity graph measured in a depth direction from a surface of a high resistance silicon wafer manufactured by the method of manufacturing a high resistance silicon wafer according to the present invention. Since the oxide film and the surface of the silicon wafer are removed after the heat treatment is performed after the oxide film is formed, there is no region where the specific resistance is reduced on the surface of the silicon wafer. Therefore, it can be seen that a silicon wafer having a uniform high resistivity can be produced.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made by those skilled in the art within the technical idea of the present invention. Is obvious.

1 is a flowchart of a method for manufacturing a high resistance silicon wafer according to the present invention.

2 is a cross-sectional view of the process sequence of the method of manufacturing a high resistance silicon wafer according to the present invention.

3 is a graph showing a boron pile up phenomenon as a resistivity graph measured in a depth direction from a surface of a conventional high resistance silicon wafer.

4 is a resistivity graph measured in a depth direction from a surface of a high resistance silicon wafer manufactured by the method of manufacturing a high resistance silicon wafer according to the present invention.

Claims (2)

Forming an oxide film having a thickness of 50 to 150 Å on a silicon wafer surface; Heat-treating the silicon wafer on which the oxide film is formed; And Removing the oxide film and the silicon wafer surface portion within 5 μm. The method of claim 1, wherein removing the oxide film and the silicon wafer surface portion within 5 μm, Removing the oxide film by hydrofluoric acid solution or BOE (Buffered Oxide Etchant); And And physically removing the silicon wafer surface portion using polishing equipment.

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