JP2906120B2 - Method for manufacturing GaAs substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a GaAs substrate, and more particularly to a wafer annealing technique after crystal growth.

[0002]

2. Description of the Related Art As a method of manufacturing a single crystal of a compound semiconductor such as GaAs, a liquid-sealed Czochralski (LE) is used.
C) method, gradient freezing (GF) method, vertical Bridgman (VB) method, horizontal Bridgman (HB) method, and the like. In any of these methods, a temperature gradient is provided between the crystal and the melt. Since the crystal is grown by solidifying the crystal, it is inevitable that the characteristics in the grown crystal become non-uniform. Therefore, even if an electronic device is manufactured using a thin wafer cut from such a grown crystal as a substrate, there is a problem that device characteristics vary greatly within the wafer surface and the yield is reduced. For example, in many ion-implanted FETs (Field-Effect Transistors) fabricated on undoped or Cr-doped GaAs single crystal wafers, the threshold voltage Vth of each FET is reduced due to the non-uniform characteristics described above. There is a problem of dispersion.

[0003] The applicant of the present invention has proposed that a wafer cut out of a grown crystal is placed in a vacuum quartz ampoule at 1100 ° C.
The first stage annealing is carried out at a temperature higher than the melting point and lower than the melting point for 30 minutes or more, then cooled to room temperature at a temperature lowering rate of 1 to 30 ° C./min, the wafer is etched, and then, in a non-oxidizing atmosphere. At a temperature of 750 ° C or more and 1100 ° C or less
A heat treatment method has been proposed in which the second-stage annealing is performed for at least 0 minute and then cooled to room temperature (described in JP-A-2-192500). According to this proposal, the cathodoluminescence image is uniform, that is, the in-plane characteristics of the wafer are uniform, and A
It is possible to obtain a wafer having few micro defects (egg-shaped pits) appearing by the B etching, and to use such a wafer as a substrate to obtain an effect that an electronic device having extremely stable characteristics can be manufactured with a high yield.

[0004]

However, according to our research after that, in the above-mentioned two-step annealing method, when ion implantation is performed in a device manufacturing process, depending on the conditions of the manufacturing process, ions such as silicon implanted into a GaAs wafer are implanted. It has been found that the activation rate of is not as high as expected.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a GaAs substrate in which the activation rate of implanted ions such as silicon is increased by wafer annealing as compared with the conventional method.

[0006]

One of the factors inhibiting the activation of implanted ions is that there are many arsenic site vacancies and the implanted ions enter there. In other words, when silicon as a donor is implanted by entering a gallium site, most of the silicon enters an arsenic site and becomes an acceptor, and the silicon which has entered the gallium site and becomes a donor is compensated. The conversion rate falls.

Therefore, the present inventors thought that the activating rate could be improved by reducing the number of arsenic site vacancies and bringing the inside of the substrate into an arsenic excess state. Then, in order to bring the inside of the substrate into an arsenic excess state, focusing on EL2 which is considered to be an intrinsic defect related to excess arsenic, it was considered effective to increase the concentration of EL2 in the substrate. That is, E
If the L2 concentration is high, it is considered that vacancies in the arsenic sites are small, and even if vacancies are formed in the arsenic sites in the device manufacturing process or the like, excess arsenic is replenished and the vacancies remain as vacancies. This is because it is considered difficult. Based on these considerations, the present inventors
Annealing of a GaAs wafer grown by a method or the like is performed in two stages. First, a first depth annealing from the surface of the wafer (a depth greater than a normal surface polishing amount, for example, several tens to hundreds It was thought that a GaAs substrate in an arsenic-rich state could be obtained by diffusing excess arsenic to a range of up to μm) and then performing a second-stage anneal to keep the wafer at the EL2 generation temperature. Experiments were repeated to realize the idea, and the present invention was completed.

According to the first aspect of the present invention, the grown GaAs
The wafer cut out of the s single crystal is placed in an arsenic pressure atmosphere at least twice the stoichiometric equilibrium vapor pressure at a temperature of 1000 ° C.
First-stage annealing is performed at a temperature of 0 ° C. or less for a predetermined time, then cooled to 400 ° C. or less, and then second-stage annealing is performed at a temperature of 800 ° C. or more and less than 1000 ° C. in an arsenic pressure atmosphere. The method is characterized in that after performing, cooling to room temperature is performed.

Then, as in the second aspect of the present invention, the Ga is cooled to room temperature after the completion of the second step annealing.
The surface of the As substrate is mirror-polished by a predetermined amount, and ion implantation of impurities is performed from the polished surface.

Here, in this specification, the stoichiometric equilibrium vapor pressure refers to “Journal of Crystal Growth 99 (199).
0) 1-8 “STOICHIOMETRY CONTROL FOR GROWTH OF III-V
CRYSTALS ")" on the right column of page 3 from line 11 to twelfth
Equation described in the line: P _{GaAs, opt} = 2.6 × 10 ⁶ exp [−1.05 (eV)
/ (KT)] Torr, which is defined as P _{GaAs, opt} Torr.

[0011]

According to the first and second aspects of the present invention, excessive arsenic is diffused from the surface of the wafer to a depth equal to or larger than the normal surface polishing amount by the first-step annealing, or arsenic is removed from the wafer. Scattering is prevented, EL2 is generated by the second-stage annealing, and at least a portion near the substrate surface used for manufacturing an electronic device such as an ion-implanted FET can be prevented from becoming arsenic-deficient. Can be in excess of normal bulk crystals. Therefore, if the surface of such a substrate is mirror-polished by a predetermined amount and silicon or the like is ion-implanted, the activation rate of the implanted ions is increased.

[0012]

EXAMPLES The features of the present invention will be clarified below with reference to examples and comparative examples. It goes without saying that the present invention is not limited at all by the following examples.

(Embodiment) First, a diameter of 11 was obtained by the LEC method.
0mm, straight body 120mm semi-insulating undoped Ga
An As single crystal was grown. Then, the upper and lower ends of the single crystal were cut and subjected to cylindrical grinding to form an orientation flat, followed by wafer ring. Each of the obtained wafers was etched by about 30 μm per side with a NaOH-based etchant, and then washed. Thereafter, a total of 100 wafers were sealed in vacuum in a plurality of quartz ampoules together with 88 dummy GaAs wafers, 12 wafers each.

Subsequently, each of the quartz ampoules was set in a heat treatment furnace, and the first stage annealing was performed at a temperature of 1000 to 1080 ° C. Thereafter, each quartz ampoule was once cooled to around room temperature, and then heated again to 800 ° C.
The second stage annealing was performed at a constant temperature of less than 1000.degree. Thereafter, each quartz ampule was cooled to room temperature and taken out of the heat treatment furnace. In addition, an appropriate amount of arsenic is sealed in advance in each quartz ampule together with the wafer, and the arsenic pressure PAS in each quartz ampule becomes twice or more of the stoichiometric equilibrium vapor pressure during the first-stage annealing (that is, The following equations (1) and (2) are satisfied).

PAS ≧ F (T) Aexp (B / kT) ‥‥ (1) F (T) = 2.0 ‥‥ (2) where k is Boltzmann's constant, and T is a heat treatment temperature expressed in absolute temperature. , A = 2.6 × 10 ⁶ Torr, B = −1.05
eV. The arsenic pressure in the quartz ampoule in the second stage annealing is determined by the amount of arsenic sealed in the ampoule and the annealing temperature.

Specifically, the heat treatment conditions for each quartz ampoule are as shown in Table 1 for sample No. 1 to 4. In addition,
When the stoichiometric equilibrium vapor pressure is expressed as Pi, Pi is the same as PGaAs _{, opt} described above, and Pi = PGaAs _{, opt} = 2.6 × 10 ⁶ exp [−1.05
(EV) / (kT)] Torr, and the arsenic pressure ratio (PAS / Pi) during the first stage annealing
Is equal to F (T).

[0017]

[Table 1]

The wafer surface of each of the obtained samples was 60 μm.
m, and after performing an activation heat treatment by implanting silicon ions from the polished surface, the Van der Pa
The activation rate was determined by measuring the sheet carrier concentration by the uu method.

The temperature of the first annealing is 1000
It is suitably from -10 to 80 ° C, preferably from 1030 to 1070 ° C. The reason is that if it is less than the lower limit value, arsenic precipitates that cause deterioration of characteristics of electronic devices and the like will occur,
However, when the EL2 concentration does not increase and the uniformity of the resistivity deteriorates, the dissociation pressure of As increases exponentially when the upper limit is exceeded, and the scattering of As cannot be prevented. Is worse, and the activation rate is lower.

Further, the arsenic pressure PAS of the first stage annealing needs to satisfy the above formulas (1) and (2), otherwise, scattering of As and diffusion of As to the substrate become insufficient. This is because the activation rate decreases.

Further, the temperature of the second stage annealing is 800
C. to less than 1000 C., preferably 900 to 950 C. because it is necessary to maintain the EL2 generation temperature (800 to 1000 C.) in order to generate EL2 by the second-stage annealing.

Further, cooling is performed to a temperature near room temperature between the first-stage annealing and the second-stage annealing. At this time, a middle donor having an energy level of 0.40 to 0.45 eV is not generated. The temperature may be 400 ° C. or less.

COMPARATIVE EXAMPLE As a first comparative example, a total of 100 wafers together with 88 dummy GaAs wafers and an appropriate amount of arsenic were prepared from 12 undoped GaAs single crystals produced in the same manner as in the above embodiment. Vacuum sealed in a plurality of quartz ampoules. As shown in 5 to 10, at 1030 ° C or 1070 ° C, the above (1)
The value of F (T) in the formula is 1.0 or 1.5, or 110
First-stage annealing was performed under the condition that the value of F (T) was 2.0 or 3.0 at 0 ° C., and once cooled to around room temperature.
The second stage annealing was performed at a constant temperature of 50 ° C.

As a second comparative example, an undoped GaAs single crystal made in the same manner as in the above embodiment was used.
A total of 100 wafers together with 88 dummy GaAs wafers together with 88 dummy GaAs wafers are vacuum-sealed in a quartz ampoule together with an appropriate amount of arsenic. Pressure atmosphere (arsenic pressure PAS = 0.
42atm), and then cooled to near room temperature and taken out of the quartz ampule.
Annealing was performed again at a constant temperature of 950 ° C. in a nitrogen atmosphere.

The activation rates of the wafers of the first and second comparative samples thus obtained were examined in the same manner as in the above-described embodiment.

The activation ratio obtained from each of the samples of the above embodiment and the first comparative example and the arsenic pressure ratio (PAS
/ Pi = F (T)) is shown in FIG. From the figure, the temperature at the time of the first stage annealing is 1030 ° C. or 1070 ° C.
It was also found that the activation rate was high when the arsenic pressure ratio was 2.0 or more. Further, the value of the activation rate at the time of being high corresponds to 103 to 109% of the activation rate obtained from the sample of the second comparative example, and the activation rate of the implanted ions was improved by applying the present invention. It was confirmed that.

However, GaAs obtained by applying the present invention
For the s substrate, Japanese Patent Application Laid-Open No.
Although it is slightly inferior to the GaAs substrate obtained by the invention of No. 92500 in terms of the uniformity of the cathode luminescence image and the pit density by AB etching, there is no practical problem. According to the present invention, the variation in resistivity is 4 to 6%, the variation in mobility is 3%, which is equivalent to that of the prior application, and the σVth of the FET is 6 to 8 mV, which is better than that of the previous application. In addition, there is an effect that the activation rate is improved.

[0028]

According to the method of manufacturing a GaAs substrate according to the present invention, a wafer cut from a grown GaAs single crystal is subjected to a temperature of 1000 ° C. to 1080 in an arsenic pressure atmosphere at least twice the stoichiometric equilibrium vapor pressure. First annealing at a temperature of not more than 400 ° C. for a predetermined time, then cooling to 400 ° C. or less, and subsequently in an arsenic pressure atmosphere at 800 ° C. to 100 ° C.
After performing the second-stage annealing at a temperature lower than 0 ° C. for a predetermined time, the substrate is cooled to room temperature, so that the first-stage annealing causes an excessive area from the surface of the wafer to a depth equal to or more than the normal surface polishing amount. Since arsenic is diffused or arsenic is prevented from being scattered from the wafer and EL2 is generated by the second-stage annealing, at least the ion-implanted FE
A portion near the substrate surface used for manufacturing an electronic device such as T is in an arsenic excess state, and a substrate having a high activation rate of implanted ions when silicon or the like is implanted can be obtained.

[Brief description of the drawings]

FIG. 1 is a characteristic diagram showing a relationship between an activation rate of each sample of an example to which the present invention is applied and a comparative example thereof and an arsenic pressure ratio at the time of first-stage annealing.

Claims (2)

(57) [Claims] 1. First-stage annealing in which a wafer cut from a grown GaAs single crystal is kept at a temperature of 1,000 ° C. to 1080 ° C. for a predetermined time in an arsenic pressure atmosphere at least twice the stoichiometric equilibrium vapor pressure. And then at 400 ° C.
Manufacturing a GaAs substrate, wherein the GaAs substrate is cooled down to a temperature below 800 ° C. and then maintained at a temperature of 800 ° C. or more and less than 1000 ° C. for a predetermined time, and then cooled to room temperature. Method. 2. The method according to claim 1, wherein the surface of the GaAs substrate cooled to room temperature after completion of the second-step annealing is mirror-polished by a predetermined amount, and ion implantation of impurities is performed from the polished surface. A method for manufacturing a GaAs substrate.