JPH08259396A - Gaas substrate and its production - Google Patents

Abstract

PURPOSE: To obtain a GaAs substrate wherein the concentration of EL2, an inherent defect placed at a deep position, is higher at a place near the surface of a thin substrate than at its inner place, by annealing a GaAs wafer at two stages whose conditions are different from each other. CONSTITUTION: In the first annealing stage, a wafer cut out from a GaAs single crystal is vacuum-sealed in a quartz ampule together with a suitable amount of arsenic and subsequently held in the atmosphere of an arsenic pressure of 0.8 times or higher a stoichiometric equilibrium steam pressure at a temperature of 1000-1100 deg.C for a prescribed time (e.g. 2hr). In the second annealing stage, the treated wafer is cooled to 400 deg.C, held in the atmosphere of an arsenic pressure of 2 times or higher the stoichiometric equilibrium stream pressure at 800-1000 deg.C for a prescribed time (e.g. 3hr), and subsequently cooled to room temperature. In the obtained GaAs substrate, the concentration of EL2 is higher at a place near the surface than at an inside place, and the EL2 concentration at a place deep by at least 60μm from the surface of the substrate is >=1.6×10<16> cm<-3> .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GaAs substrate and a method for manufacturing the same, and more particularly to a GaAs substrate having a high EL2 concentration near the surface of the substrate and a wafer annealing technique for manufacturing the same.

[0002]

2. Description of the Related Art Liquid-encapsulated Czochralski (LE) is used as a method for producing a single crystal of a compound semiconductor such as GaAs.
There are C) method, gradient freezing (GF) method, vertical Bridgman (VB) method, horizontal Bridgman (HB) method, etc., and all of them have a temperature gradient between the crystal and the melt. Since the crystal is grown by solidifying, it is unavoidable that the characteristics in the grown crystal become non-uniform. Therefore, even if an electronic device is manufactured by using a thin plate-shaped wafer cut out from such a grown crystal as a substrate, there is a problem that the device characteristics greatly vary within the wafer surface and the yield decreases. For example, in many ion-implanted FETs (Field-Effect Transistors) manufactured on a wafer made of undoped or Cr-doped GaAs single crystal, the threshold voltage Vth of each FET is There is a problem of variation.

Therefore, the applicant of the present invention cuts a wafer cut from a grown crystal at 1100 ° C. in a vacuum quartz ampoule.
The first stage annealing is performed by holding the temperature above the melting point and below the melting point for 30 minutes or more, then cooling to room temperature at a temperature decreasing rate of 1 to 30 ° C./min, etching the wafer, and then in a non-oxidizing atmosphere. , 2 at temperatures above 750 ° C and below 1100 ° C
A heat treatment method has been proposed in which the second stage annealing is performed for 0 minutes or more and then cooled to room temperature (described in JP-A-2-192500). According to this proposal, the cathode luminescence image is uniform, that is, the in-plane characteristics of the wafer are uniform, and A
It is possible to obtain a wafer with few microdefects (oval pits) that appear by B etching, and by using such a wafer as a substrate, it is possible to produce an electronic device having very stable characteristics with a high yield.

[0004]

However, according to our research after that, in the above two-step annealing method, when ion implantation is performed in the device manufacturing process, ions such as silicon implanted in the GaAs wafer may be formed depending on the manufacturing process conditions. It was found that the activation rate of P. does not increase as expected.

One of the factors that hinder the activation of implanted ions is that many arsenic site holes are filled with implanted ions. In other words, when silicon that serves as a donor is injected by entering the gallium site, most of it enters the arsenic site and becomes an acceptor, which compensates the silicon that entered the gallium site and became a donor. The rate of conversion will decrease.

By the way, EL2 which forms a deep level is
It is considered to be an intrinsic defect related to excess arsenic such as arsenic antisite and gallium site vacancies. Therefore, if the EL2 concentration is high, it is considered that there are few vacancies in the arsenic site, and even if vacancies are generated in the arsenic site in the device manufacturing process, etc., excess arsenic will be replenished and the vacancies will remain. It is thought that it is hard to exist in. Therefore, to increase the activation rate of implanted ions,
It is considered important to increase the EL2 concentration in the vicinity of the surface of the substrate used for manufacturing the device.

However, it has been reported that when a wafer is heat-treated in a vacuum atmosphere, the concentration of deep levels near the surface thereof becomes low, while the concentration of deep levels near the surface thereof, especially the concentration of EL2, becomes high. Therefore, it is considered difficult to increase the EL2 concentration in the vicinity of the surface. Further, it is known that if a grown GaAs crystal is annealed as an ingot, the EL2 concentration in the grown crystal is determined to be a constant value depending on the annealing temperature.
It seems that it is still difficult to raise the L2 concentration higher than the inside.

The present invention has been made to solve the above problems, and its purpose is to improve the activation rate of implanted ions by increasing the concentration of EL2 in the portion close to the substrate surface than in the inside. To provide a substrate.

Another object of the present invention is to provide a method for manufacturing a GaAs substrate in which the EL2 concentration in the portion close to the substrate surface can be made higher than that in the interior by heat treatment.

[0010]

In order to achieve the above object, the inventor of the present invention performs annealing of a GaAs wafer grown by the LEC method or the like in two steps, and first of all, anneals the wafer by the first first step annealing. Depth from the surface (depth greater than the normal amount of surface polishing, for example, tens to hundreds of tens μm)
It was thought that it is possible to obtain a GaAs substrate in which the concentration of EL2 in the portion close to the substrate surface is higher than that in the interior by diffusing the excess arsenic in the range up to and producing EL2 by the subsequent second-stage annealing. Then, experiments were repeated to realize the idea, and the annealing conditions at each stage were found to complete the present invention.

According to the first aspect of the present invention, in the GaAs substrate, the portion nearer to the surface than the inside of the thin plate substrate made of GaAs is an intrinsic defect that forms a deep level.
It is characterized in that the concentration of 2 is high.

Specifically, for example, as in the second aspect of the invention, the EL2 concentration is at least 1.6 × 10 ¹⁶ cm ^{-3 at} least in the portion having a depth of 60 μm from the substrate surface.

According to the third aspect of the present invention, the concentration of EL2, which is an intrinsic defect forming a deep level, is higher in the portion closer to the surface than inside the thin plate-shaped substrate.
In manufacturing the substrate, a wafer cut out from the grown GaAs single crystal was processed to a stoichiometric equilibrium vapor pressure of 0.
1000 ° C to 1110 ° C in an arsenic pressure atmosphere of 8 times or more
First-stage annealing is performed at the following temperature for a predetermined time, then cooled to 400 ° C or lower, and then 800 ° C or higher in an arsenic pressure atmosphere at twice the stoichiometric equilibrium vapor pressure or higher.
It is characterized in that after performing the second stage annealing in which the temperature is kept at 000 ° C. or lower for a predetermined time, it is cooled to room temperature.

In this specification, the stoichiometric equilibrium vapor pressure means "Journal of Crystal Growth 99 (199
0) 1-8 “STOICHIOMETRY CONTROL FOR GROWTH OF III-V
CRYSTALS ”)”, page 3, right column, lines 11-12
The formula described in the line: P _{GaAs, opt} = 2.6 × 10 ⁶ exp [−1.05 (eV) / (kT)] Torr is defined as P _{GaAs, opt} Torr.

[0015]

According to the invention described in claims 1 and 2, since the EL2 concentration is higher in the portion closer to the surface than in the inside of the substrate,
The EL2 concentration in the portion close to the substrate surface is higher than in the conventional case, and the activation rate of implanted ions in the portion near the substrate surface used for manufacturing an electronic device such as an ion-implanted FET is improved.

According to the third aspect of the invention, excess arsenic diffuses into the region from the surface of the wafer to a depth equal to or larger than the normal surface polishing amount by the first step annealing, and arsenic diffuses by the second step annealing. EL2 is generated in the depth region, and the EL2 concentration in the portion close to the substrate surface becomes higher than that in the inside. The EL2 concentration inside the substrate is E in the conventional substrate.
Since the L2 concentration is the same as the L2 concentration, the EL2 concentration in the vicinity of the surface of the GaAs substrate according to the present invention is higher than the conventional one.

[0017]

EXAMPLES The features of the present invention will be clarified below with reference to Examples and Comparative Examples. Needless to say, the present invention is not limited to the following examples.

(Example 1) First, a diameter of 8 was obtained by the LEC method.
Conductive silicon dope G with a length of 4 mm and a straight body length of 120 mm
An aAs single crystal (doping amount: 6 × 10 ¹⁶ cm ⁻³ ) was grown. Then, the upper and lower ends of the single crystal were cut, cylindrical grinding was performed to form an orientation flat, and then a wafer ring was performed. For each obtained wafer, N
After etching with an aOH-based etchant in an amount of about 30 μm per side, cleaning was performed. Then, 12 wafers each, together with 88 dummy GaAs wafers, were vacuum sealed in a plurality of 100 quartz ampules.

Subsequently, each quartz ampoule was set in a heat treatment furnace and first-stage annealing was performed at a temperature of 1000 to 1110.degree. Then, after cooling each quartz ampoule to near room temperature, the temperature is raised again to 800-
The second stage annealing was performed at a constant temperature of 1000 ° C. Then, each quartz ampoule was cooled to room temperature and taken out from the heat treatment furnace. In addition, an appropriate amount of arsenic is enclosed in advance in each quartz ampoule together with the wafer, and the arsenic pressure P in each quartz ampoule becomes 0.8 times or more of the stoichiometric equilibrium vapor pressure during the first-stage annealing. (That is, the following formula (1) is satisfied), and the stoichiometric equilibrium vapor pressure is doubled or more during the second stage annealing (that is, the following formula (2) is satisfied).

P ≧ 0.8 Aexp (B / kT) (1) P ≧ 2A exp (B / kT) (2) where k is the Boltzmann constant, T is the heat treatment temperature expressed in absolute temperature, A = 2.6 × 10 ⁶ Torr, B = −1.05
eV.

Specifically, the heat treatment conditions for each quartz ampoule were as shown in Table 1.

[0022]

[Table 1]

The surface of the wafer of each obtained sample was
Mirror-polishing with a polishing amount of μm, 60 μm, 75 μm, 90 μm, 120 μm and 150 μm, a Schottky electrode and an ohmic electrode are formed on the polished surface by photolithography, and DLTS (Deep Level Transient Spe
The deep level concentration was measured by the ctroscopy method. As a result, the distribution of the EL2 concentration in the depth direction of all the samples was as shown in FIG. 1 when the depth from the substrate surface immediately after heat treatment was up to 60 μm, that is, the polishing amount of mirror polishing was up to 60 μm. The distribution was such that the EL2 concentration in the region was higher than the EL2 concentration inside the substrate. In particular, the EL2 concentration of the polishing amount of 60 μm is the highest, 1.6 × 10 ¹⁶ cm ⁻³ or more, and the polishing amount of 150 μm.
20% higher than the EL2 concentration of (corresponding to the commonly known value)
% Was high.

The temperature of the first stage annealing is 1000
Suitably, it is -1110 ° C, preferably 1010-1100 ° C. The reason is that if the amount is less than the lower limit, arsenic precipitates that cause deterioration of characteristics of electronic devices and the like are generated.
The EL2 concentration near the surface of the substrate does not increase, and the uniformity of the resistivity deteriorates. On the other hand, when the upper limit is exceeded, the dissociation pressure of As increases exponentially, and As scatters. This is because the EL2 concentration cannot be prevented and the EL2 concentration in the portion near the surface does not increase.

Further, the arsenic pressure P of the first-stage annealing must satisfy the above expression (1) because if it is not satisfied, the scattering of As and the diffusion of As into the substrate will be insufficient.
2 This is because the concentration does not increase.

Further, the temperature of the second stage annealing is 800
The reason why the temperature is ˜1000 ° C., preferably 900 to 950 ° C. is that it is necessary to maintain the EL2 generation temperature (800 to 1000 ° C.) in order to generate EL2 by the second stage annealing.

Furthermore, the arsenic pressure P of the second stage annealing
Must satisfy the above formula (2) because A from the surface
This is because scattering of s can be prevented and a decrease in EL2 concentration can be prevented.

Further, between the first-stage annealing and the second-stage annealing, the temperature is cooled to a temperature near room temperature, but at this temperature, a middle donor having an energy level of 0.40 to 0.45 eV is not generated. The temperature may be 400 ° C. or lower.

(Embodiment 2) First, a diameter of 8 is obtained by the LEC method.
Semi-insulating undoped Ga with a length of 4 mm and a straight body length of 200 mm
After growing an As single crystal and performing wafer ring, etching and cleaning in the same manner as in Example 1, 100 wafers including dummy wafers were vacuum-sealed in each of the obtained wafers. Then, for each quartz ampoule, in the same manner as in Example 1 above, 1000 to 1110
First-stage annealing at a temperature of ℃, once cooling to near room temperature, second-stage annealing at a constant temperature of 800 to 1000 ° C., and cooling to room temperature were continuously performed. Example 2
However, as in the case of Example 1, the arsenic pressure P in each quartz ampoule during the annealing in the first step and the second step was the same as in the above (1).
An appropriate amount of arsenic was enclosed in each quartz ampule so as to satisfy the formula and the formula (2).

Specifically, the heat treatment conditions for each quartz ampoule were as shown in Table 2.

[0031]

[Table 2]

Based on the distribution result of the EL2 concentration in the depth direction obtained in the above-mentioned Example 1, the wafer surface of each sample obtained in this Example 2 was mirror-polished by 60 μm,
After activating the heat treatment for activation by implanting silicon ions from the polished surface, the concentration of the sheet carrier was measured by the Van der Pauw method to examine the activation rate.

Comparative Example 1 For comparison, 12 wafers made of silicon-doped GaAs single crystal (doping amount: 6 × 10 ¹⁶ cm ⁻³ ) manufactured in the same manner as in Example 1 were used as dummy GaAs wafers 88. A total of 100 sheets together with a proper amount of arsenic were vacuum-sealed in a quartz ampoule, and a relatively low arsenic pressure atmosphere (arsenic pressure P = 0.42 atm) that did not satisfy the above formula (1) at 1100 ° C. in a heat treatment furnace. Annealing was carried out, the wafer was taken out from the quartz ampoule once cooled to around room temperature, and then annealed again at a constant temperature of 950 ° C. in a nitrogen atmosphere.

The surface of the wafer of the comparative sample thus obtained was mirror-polished with various polishing amounts in the same manner as in Example 1 above, Schottky electrodes and ohmic electrodes were formed, and a deep level was obtained by DLTS. When the concentration was measured, E
The distribution of the L2 concentration in the depth direction is such that the EL2 concentration in a region where the depth from the substrate surface immediately after the heat treatment is relatively shallow is lower than the EL2 concentration inside the substrate and shows a saturation tendency inside the substrate. Met.

(Comparative Example 2) As a comparison, 100 wafers made of undoped GaAs single crystal and dummy wafers produced in the same manner as in Example 2 had an As pressure of 1. 65
A quartz ampoule was vacuum-sealed together with arsenic in an amount of atm, annealed at 950 ° C. in a heat treatment furnace, and after cooling, the wafer was taken out from the quartz ampoule. The EL2 concentration according to the DLTS method had an almost constant value (about 1.5 × 10 ¹⁶ cm ⁻³ ) without any distribution in the depth direction.

(Comparative Example 3) For comparison, 100 wafers made of undoped GaAs single crystal and dummy wafers produced in the same manner as in Example 2 above were vacuum-sealed together with an appropriate amount of arsenic in a quartz ampoule and heated in a heat treatment furnace. 11
Annealing is performed in a relatively low arsenic pressure atmosphere (arsenic pressure P = 0.42 atm) that does not satisfy the above formula (1) at 00 ° C., and once cooled to around room temperature, the wafer is taken out from the quartz ampoule, and then nitrogen is removed. Annealing was performed again at a constant temperature of 950 ° C. in the atmosphere.

The surface of the wafer of the comparative sample thus obtained was mirror-polished by 60 μm in the same manner as in Example 2, and silicon ions were implanted from the polished surface to carry out activation heat treatment, and then Van. The activation rate was investigated by measuring the sheet carrier concentration by the der Pauw method. Comparing this Comparative Example 3 with the above Example 2, the activation rate of Example 2 is 103 to 109% of the activation rate of Comparative Example 3,
Had been improved.

However, GaA obtained by applying the present invention
In the case of the s substrate, Japanese Patent Application Laid-Open No. 2-1
Although it is slightly inferior to the GaAs substrate obtained by the invention of No. 92500 in terms of the uniformity of the cathode luminescence image and the pit density by AB etching, there is no problem in practical use. Further, according to the present invention, the variation in resistivity is 4 to 6%, the variation in mobility is 3%, which is equivalent to that of the previous application, and the σVth of the FET is 6 to 8 mV, which is better than that of the previous application. Moreover, there is an effect that the activation rate is improved.

[0039]

According to the GaAs substrate of the present invention, G
Since the concentration of EL2, which is an intrinsic defect forming a deep level, is higher in a portion closer to the surface than in the inside of the thin plate substrate made of aAs, for example, at least a portion having a depth of 60 μm from the substrate surface. EL2 concentration of 1.6 × 10 ¹⁶
cm ^-3 or higher, higher than before, and ion implantation type FET
It is possible to obtain an effect that the activation rate of implanted ions is improved in the vicinity of the surface of the substrate used for manufacturing electronic devices such as.

Further, according to the GaAs substrate manufacturing method of the present invention, excess arsenic is diffused into the region from the surface of the wafer to the depth equal to or more than the normal surface polishing amount by the first step annealing, and the second step annealing is performed. Causes EL2 to be generated in the depth region where arsenic is diffused, and E2 in a portion near the substrate surface
The L2 concentration becomes higher than the inside. Since the EL2 concentration inside the substrate is the same as the EL2 concentration in the conventional substrate, a GaAs substrate in which the EL2 concentration in the vicinity of the surface of the substrate used for the manufacture of electronic devices is higher than in the conventional case and the activation rate of implanted ions is high. can get.

[Brief description of drawings]

FIG. 1 is a silicon-doped Ga produced by applying the present invention.
It is a schematic diagram showing distribution of EL2 density of an As substrate in the depth direction.

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[Procedure amendment]

[Submission date] May 12, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

(Comparative Example 2) For comparison, a silicon-doped GaAs single crystal ( d) prepared in the same manner as in Example 1 was used.
Amount: 6 × 10 ¹⁶ cm ^-3 ) and 10 consisting of dummy wafers
As wafer pressure of 1. A quartz ampoule was vacuum-sealed together with arsenic in an amount of 65 atm, annealed at 950 ° C. in a heat treatment furnace, and after cooling, the wafer was taken out from the quartz ampoule. The EL2 concentration according to the DLTS method does not have a distribution in the depth direction and has a substantially constant value (about 1.5).
× 10 ¹⁶ cm ^-3 ).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication C30B 25/18 C30B 25/18

Claims (3)

[Claims] 1. The concentration of EL2 which is an intrinsic defect forming a deep level is higher in a portion closer to the surface than in the inside of a thin plate substrate made of GaAs.
aAs substrate. 2. A depth of at least 60 μm from the substrate surface.
2. The GaAs substrate according to claim 1, wherein the EL2 concentration in the portion m is 1.6 × 10 ¹⁶ cm ⁻³ or more. 3. In manufacturing a GaAs substrate in which the concentration of EL2, which is an intrinsic defect forming a deep level, is higher in a portion closer to the surface than in the inside of a thin plate-shaped substrate,
A wafer cut from the grown GaAs single crystal,
First-stage annealing is carried out in an arsenic pressure atmosphere of 0.8 times the stoichiometric equilibrium vapor pressure or more at a temperature of 1000 ° C. or more and 1110 ° C. or less, then cooled to 400 ° C. or less, and then stoichiometrically. A GaAs substrate characterized by being cooled to room temperature after performing a second-stage annealing in which the temperature is kept at 800 ° C. or higher and 1000 ° C. or lower for a predetermined time in an arsenic pressure atmosphere that is at least twice the equilibrium vapor pressure. Manufacturing method.