KR930004120B1 - Thermal treating method of compound semiconductor wafer - Google Patents
Thermal treating method of compound semiconductor wafer Download PDFInfo
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- KR930004120B1 KR930004120B1 KR1019900016943A KR900016943A KR930004120B1 KR 930004120 B1 KR930004120 B1 KR 930004120B1 KR 1019900016943 A KR1019900016943 A KR 1019900016943A KR 900016943 A KR900016943 A KR 900016943A KR 930004120 B1 KR930004120 B1 KR 930004120B1
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 150000001875 compounds Chemical class 0.000 title claims abstract description 27
- 238000010438 heat treatment Methods 0.000 claims abstract description 28
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 7
- 229910000673 Indium arsenide Inorganic materials 0.000 claims abstract description 3
- 238000001816 cooling Methods 0.000 claims abstract description 3
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910005540 GaP Inorganic materials 0.000 claims abstract 2
- 239000000565 sealant Substances 0.000 claims description 5
- 238000010791 quenching Methods 0.000 claims description 4
- 230000000171 quenching effect Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims 1
- 238000007789 sealing Methods 0.000 abstract description 3
- 239000000155 melt Substances 0.000 abstract 1
- 230000008646 thermal stress Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 41
- 239000002244 precipitate Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 7
- 239000007789 gas Substances 0.000 description 3
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
제1도는 종래의 반절연성 GaAs 웨이퍼의 열처리 방법.1 is a heat treatment method of a conventional semi-insulating GaAs wafer.
제2(a)도∼제2(c)도는 이 발명에 따른 반절연성 GaAs 웨이퍼의 열처리 방법이다.2 (a) to 2 (c) are heat treatment methods for the semi-insulating GaAs wafer according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 화합물 반도체 웨이퍼 13 : 홈11: compound semiconductor wafer 13: groove
15 : 슬라이더 17 : 홀더15: slider 17: holder
19 : 웰 21 : 시료19: well 21: sample
23 : 밀봉제 25 : 반응관23 sealant 25 reaction tube
27 : 히터 29 : 에피택셜층27: heater 29: epitaxial layer
이 발명은 화합물 반도체 웨이퍼의 열처리 방법에 관한 것으로, 특히 높은 휘발성 원소를 포함하는 화합물 반도체 웨이퍼의 열처리 방법에 관한 것이다.TECHNICAL FIELD This invention relates to the heat treatment method of a compound semiconductor wafer, and especially the heat treatment method of a compound semiconductor wafer containing a high volatile element.
최근 정보통신 사회로 급격히 발전해감에 따라 초고속 컴퓨터, 초고주파 및 광통신에 대한 필요성이 더욱 증가되고 있다. 그러나 기준 Si를 이용한 소자로는 이러한 필요성을 만족시키는데 한계가 있다.With the rapid development of the information and telecommunications society, the need for high-speed computer, high-frequency and optical communication is increasing. However, the element using the reference Si has a limit to satisfy this need.
따라서 물질특성이 우수한 화합물 반도체에 관한 연구가 활발히 진행되고 있다. 화합물반도체의 대표적인 GaAs는 인고트(Ingot)를 성장시키면 결정내부에 전위(Dislocation), 빈격자점(Vacancy), 격자간원자(Interstitial Atom) 및 As 석출물등의 결함이 발생된다.Therefore, researches on compound semiconductors having excellent material properties have been actively conducted. Representative GaAs of compound semiconductors grow defects such as dislocations, vacancies, interstitial atoms, and As precipitates within crystals when ingots are grown.
이러한 결함들은 결정내에서 불균일하게 분포하므로 일반적인 LEC(Liquid Encapsulated Czochralski)법에 의해 생산된 인고트로 만든 웨이퍼(Wafer)를 이용하여 소자를 제작하면 소자특성이 불균일하게 되어 신뢰성을 저하시킨다.Since these defects are non-uniformly distributed in the crystal, if the device is fabricated using a wafer made of an ingot produced by a general Liquid Encapsulated Czochralski (LEC) method, the device characteristics become nonuniform and degrade reliability.
따라서 상기 웨이퍼를 소정의 열처리하여 결함들을 균일하게 분포시켜 균일한 전기적 특성을 갖도록 한다.Therefore, the wafer is subjected to a predetermined heat treatment to uniformly distribute the defects so as to have uniform electrical characteristics.
제1도는 종래의 화합물 반도체 웨이퍼의 열처리 방법을 나타내고 있다. 먼저, 열처리용 웨이퍼(1)의 양쪽면에 이 열처리용 웨이퍼(1)와 동일한 종류의 보호용 웨이퍼(3)들을 접촉시켜 과잉시료(5)와 함께 석영등으로 만든 튜브(Tube ; 7)안에 넣는다.1 shows a conventional heat treatment method for a compound semiconductor wafer. First, both surfaces of the heat treatment wafer 1 are brought into contact with the protection wafers 3 of the same type as the heat treatment wafer 1 and placed in a tube made of quartz or the like together with the excess sample 5. .
그 다음, 상기 튜브(7)의 내부를 진공상태로 만들고 밀봉한 후 히터(Heater ; 9)로 튜브(7)를 가열시켜 800∼900℃ 정도로 수십분∼수시간을 유지한 다음 냉각시킨다.Thereafter, the inside of the tube 7 is vacuumed and sealed, and the tube 7 is heated by a heater 9 to maintain several minutes to several hours at about 800 to 900 ° C., and then cooled.
상기에서 열처리용 웨이퍼(1)가 GaAs일때 Ga보다 As의 휘발온도가 매우 낮으므로 열처리 공정중에 As의 휘발(Dissociation)이 발생되기 쉽다.Since the volatilization temperature of As is much lower than that of Ga when the wafer 1 for heat treatment is GaAs, volatilization of As is likely to occur during the heat treatment process.
따라서, 과잉시료(5)로 As를 사용하여 진공상태의 튜브(7) 내부를 As 분위기로 만들어 열처리용 웨이퍼(1)에서 As가 휘발되는 것을 억제한다.Therefore, As is used as the excess sample 5, the inside of the tube 7 in the vacuum state is made into the As atmosphere, thereby suppressing the volatilization of As on the wafer 1 for heat treatment.
또한, 상기 보호용 웨이퍼(3)들은 열처리용 웨이퍼(1)에 As가 휘발되는 것을 억제할 뿐만 아니라 이 열처리용 웨이퍼(1)에 As을 공급하게 된다. 상기에서 열처리 공정을 하기전에 튜브(7)를 진공시키는 것은 열처리용 웨이퍼(1)가 산화 및 오염되는 것을 방지하기 위한 것이다. 상술한 열처리방법은 진공상태인 튜브의 내부를 열을 가하여 As 기체상태로 만들어 As 기체압력에 의해 웨이퍼내의 As의 조성을 제어하는 것이다.In addition, the protective wafers 3 not only suppress As from volatilizing the wafer 1 for heat treatment, but also supply As to the wafer 1 for heat treatment. The vacuum of the tube 7 before the heat treatment step is to prevent the heat treatment wafer 1 from being oxidized and contaminated. In the above heat treatment method, the inside of the tube in a vacuum state is heated to an As gas state to control the composition of As in the wafer by the As gas pressure.
그러나, 열처리공정을 하기전의 웨이퍼는 As의 석출물이 불균일하게 분포되어 있다. 상기 불균일하게 분포되어 있는 As의 석출물에 의해 열처리공정을 할때, 웨이퍼의 표면에서 As의 휘발 및 내부확산이 균일하도록 하기 어려운 문제점이 있었다.However, the precipitate of As is unevenly distributed in the wafer before the heat treatment step. When the heat treatment process is performed by the precipitates of As which are unevenly distributed, there is a problem that As volatilization and internal diffusion of As are uniform on the surface of the wafer.
또한, 고체와 기체의 불균일한 계면상태에서 열처리공정을 할때 표면의 거칠음 및 빈격자점등의 결함이 불균일하게 발생되는 문제점이 있었다.In addition, when the heat treatment process in a non-uniform interface state of the solid and gas there was a problem that the defects such as surface roughness and poor lattice point nonuniformly generated.
따라서, 이 발명의 목적은 웨이퍼의 표면 및 그 내부에 As 석출물을 균일하게 분포시킬 수 있는 화합물 반도체 웨이퍼의 열처리 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a heat treatment method for a compound semiconductor wafer capable of uniformly distributing As precipitates on the surface and inside thereof.
이 발명의 다른 목적은 빈격자점 및 표면의 거칠음등의 결함을 균일하게 분포시킬 수 있는 화합물 반도체 웨이퍼의 열처리방법을 제공함에 있다.Another object of the present invention is to provide a heat treatment method for a compound semiconductor wafer capable of uniformly distributing defects such as void lattice points and surface roughness.
상기와 같은 목적들을 달성하기 위하여 이 발명은, 높은 휘발성원소를 포함하는 화합물 반도체 웨이퍼의 열처리 방법에 있어서, 슬라이더의 홈에 화합물 반도체 웨이퍼를 위치시키며 홀더의 웰에 시료를 넣고 웰의 입구를 밀봉제로 밀봉한 후 제1차 열을 가하여 시료를 용융시켜 과정과, 상기 슬라이더를 이동시켜 상기 홈과 웰을 일치시켜 용융된 시료가 화합물 반도체 웨이퍼의 전표면을 덮게한 후 제2차 열을 가하여 화합물 반도체 웨이퍼의 표면을 균질화하는 과정과, 상기 홈과 웰을 분리하고 상온으로 급냉시킨 후 제3차 열을 가하여 열유기응력을 제거하는 과정으로 이루어지는 것을 특징으로 한다.In order to achieve the above objects, the present invention provides a heat treatment method for a compound semiconductor wafer containing a high volatile element, by placing the compound semiconductor wafer in the groove of the slider, the sample is put in the well of the holder and the inlet of the well is sealed. After sealing, the sample is melted by applying primary heat, and the slider is moved to match the groove and the well so that the melted sample covers the entire surface of the compound semiconductor wafer, and then the secondary heat is applied to the compound semiconductor. The process of homogenizing the surface of the wafer, and separating the groove and the well and quenching to room temperature, and then applying a third heat to remove the thermal organic stress.
이하, 첨부한 도면을 참조하여 이 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2(a)도∼제2(c)도는 이 발명에 따른 화합물 반도체 웨이퍼의 열처리 방법을 나타내고 있다. 제2(a)도를 참조하면, 소정의 세정(Cleaning) 공정에 의해 준비된 반절연성 GaAs 웨이퍼(11)를 슬라이더(Slider ; 15)의 홈(13)에 위치시키고, 이 웨이퍼(11)의 화학당론(Stoichiometry) 유지하기 위하여 10g의 Ga당 300∼1000mg의 다결정 GaAs를 혼합시킨 시료(21)를 홀더(Holder ; 17)의 웰(Well ; 19)속에 넣고 이 웰(19)을 밀봉체(23)로 밀봉한 후 전기로의 반응관(25)속에 밀어 넣는다. 상기에서 홈(13)에 웨이퍼(11)를 위치시킬때 50㎛ 정도의 공극(t)을 갖도록 한다.2 (a)-(c) show the heat treatment method of the compound semiconductor wafer which concerns on this invention. Referring to FIG. 2 (a), the semi-insulating GaAs wafer 11 prepared by a predetermined cleaning process is placed in the groove 13 of the slider 15, and the chemistry of the wafer 11 In order to maintain the toposiology, a sample 21 containing 300 to 1000 mg of polycrystalline GaAs per 10 g of Ga was placed in a well (19) of a holder (Holder; 17), and the well 19 was sealed. After encapsulating it, it is pushed into the reaction tube 25 of the electric furnace. When the wafer 11 is positioned in the groove 13 in the above, it is to have a gap t of about 50 μm.
또한 상기 전기로는 균일한 온도분포를 유지하도록 반응관(25)의 외부를 히터(27)로 감싼다. 그 다음 상기 히터(27)를 가열하여 반응관(25)의 온도를 600∼700℃ 정도로 1∼5시간 동안 유지시킨다.In addition, the electric furnace surrounds the outside of the reaction tube 25 with the heater 27 to maintain a uniform temperature distribution. Then, the heater 27 is heated to maintain the temperature of the reaction tube 25 at about 600 to 700 ° C. for 1 to 5 hours.
이때 상기 시료(21)들은 용융되며, Ga속에 있던 Ga2O3는 상기 밀봉제(23)로 슬래그(Slag)화 된다. 상기에서 밀봉제(23)는 상기 용융된 시료(21)와 반응하지 않고 휘발을 발생시키지 않는 물질로, 보통 B2O3가 케익(Cake) 형태로 이용된다. 상기에서 B2O3를 H2O의 함유량이 200∼400ppm 정도인 초건식(Super Dry) 상태가 되도록 하여 상기 용융된 시료(21)와 산소와 반응하여 생성되는 Ga2O3의 량을 줄이도록 한다.At this time, the samples 21 are melted, and Ga 2 O 3 in Ga is slagd into the sealant 23. The sealant 23 is a material that does not react with the molten sample 21 and does not generate volatilization. Usually, B 2 O 3 is used in the form of a cake. The amount of Ga 2 O 3 generated by reacting with the molten sample 21 and oxygen is reduced by B 2 O 3 to be in a super dry state where the content of H 2 O is about 200 to 400 ppm. To be.
제2(b)도를 참조하면, 상기 슬라이더(15)를 이동시켜 홈(13)을 웰(19)과 일치시키면 웨이퍼(11)의 표면이 용융된 시료(21)에 덮히게 된다. 그 다음, 온도를 900℃ 이상으로 상승시켜 2∼5시간 동안 유지시키면 웨이퍼(11) 표면에 불균일하게 분포되어 있던 As 석출물이 재고용된다.Referring to FIG. 2B, when the slider 15 is moved to match the groove 13 with the well 19, the surface of the wafer 11 is covered with the molten sample 21. Then, when the temperature is raised to 900 ° C. or higher and maintained for 2 to 5 hours, As precipitates which are unevenly distributed on the surface of the wafer 11 are reconsidered.
제2(c)도를 참조하면, 상기 슬라이더(15)를 소정위치로 이동시켜 홈(13)과 웰(19)을 분리시킨 후 300∼1200℃/hr의 냉각속도에 의해 상온까지 냉각시킨다. 이때 상기 웨이퍼(11)의 표면에 공극두께(t)를 갖는 에피택셜층(Epitaxial Layer ; 29)이 형성된다.Referring to FIG. 2 (c), the slider 15 is moved to a predetermined position to separate the groove 13 and the well 19, and then cooled to room temperature at a cooling rate of 300 to 1200 ° C / hr. At this time, an epitaxial layer 29 having a pore thickness t is formed on the surface of the wafer 11.
상기에서 에피택셜층(29)을 급속하게 냉각시키므로 As의 확산시간을 최소화하여 As 석출물이 작고 균일한 크기로 재석출된다.Since the epitaxial layer 29 is rapidly cooled in the above, the As precipitate is reprecipitated to a small and uniform size by minimizing the diffusion time of As.
또한, 상기 급냉시에 웨이퍼(11)와 에피택셜층(29)의 사이에 열에 의한 잔류응력이 많이 존재한다.In addition, there is a lot of residual stress due to heat between the wafer 11 and the epitaxial layer 29 during the quenching.
따라서 히터(27)를 다시 가열하여 600∼700℃ 정도의 온도로 5∼30시간 유지시켜 웨이퍼(11)와 에피택셜층(29) 사이의 열유기 잔류응력을 제거한다. 이때, 상기 급냉시에 재석출된 작고 균일한 크기를 갖는 핵을 중심으로 As가 확산되어 균일한 크기 As 석출물이 형성된다.Therefore, the heater 27 is heated again and maintained at a temperature of about 600 to 700 ° C. for 5 to 30 hours to remove the thermal organic residual stress between the wafer 11 and the epitaxial layer 29. At this time, As is diffused around a nucleus having a small and uniform size that is re-precipitated during the quenching to form a uniform size As precipitate.
그 다음, 상기 웨이퍼(11)를 냉각시킨 후 폴리싱(Polishing)공정을 통하여 표면에 형성된 에피택셜층(29)을 제거하여 양질의 거울면을 가지는 웨이퍼를 형성한다.Then, the wafer 11 is cooled and then the epitaxial layer 29 formed on the surface is removed through a polishing process to form a wafer having a high quality mirror surface.
또한, 상술한 열처리공정시에 웨이퍼의 표면 및 내부에 있는 빈격자점과 웨이퍼 표면의 거칠음등의 결함이 제거된다.In addition, defects such as the rough lattice point and the roughness of the wafer surface on the surface and inside of the wafer are eliminated during the above-described heat treatment step.
따라서 상술한 바와같이 이 발명은 다결정 GaAs가 용해된 Ga 용액의 액상을 이용하여 GaAs 웨이퍼를 열처리함으로써 이 GaAs 웨이퍼의 표면 및 내부에 분포되는 As 석출물 및 결함들이 균일하게 되어 전기적 특성이 균일해지는 잇점이 있다.Therefore, as described above, the present invention has the advantage that the AsA precipitates and defects distributed on the surface and the inside of the GaAs wafer are uniform by heat-treating the GaAs wafer using the liquid phase of the Ga solution in which the polycrystalline GaAs is dissolved. have.
이상에서와 같이 이 발명의 실시예를 GaAs를 설명하였으나 이 발명의 사상에 어긋나지 않게 InAs, InP 및 GaP등에 적용할 수 있다.As described above, the embodiment of the present invention has been described with GaAs, but it can be applied to InAs, InP, GaP and the like without departing from the spirit of the present invention.
Claims (10)
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| KR1019900016943A KR930004120B1 (en) | 1990-10-22 | 1990-10-22 | Thermal treating method of compound semiconductor wafer |
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