JPH0642489B2 - Heat treatment method for compound semiconductor wafer - Google Patents
Heat treatment method for compound semiconductor waferInfo
- Publication number
- JPH0642489B2 JPH0642489B2 JP31571390A JP31571390A JPH0642489B2 JP H0642489 B2 JPH0642489 B2 JP H0642489B2 JP 31571390 A JP31571390 A JP 31571390A JP 31571390 A JP31571390 A JP 31571390A JP H0642489 B2 JPH0642489 B2 JP H0642489B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- compound semiconductor
- heat treatment
- treatment method
- sample
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） この発明は化合物の半導体ウェーハの熱処理方法に係わ
り、特に高い揮発性元素を含む化合物の半導体ウェーハ
の熱処理方法に関する。The present invention relates to a heat treatment method for a compound semiconductor wafer, and more particularly to a heat treatment method for a compound semiconductor wafer containing a highly volatile element.
（従来の技術） 最近情報通信の社会へ急激に発展することにより超高速
コンピューター超高周波及び光通信に対する必要性が更
に増加している。しかし既存Ｓｉを利用した素子ではこ
のような必要性を満たすことに限界がある。従って物質
特性が優れた化合物の半導体に関する研究が活発に進行
している。(Prior Art) With the recent rapid development of information and communication societies, the need for ultra-high-speed computers, ultra-high-frequency and optical communications is increasing. However, there is a limit in the element using the existing Si to satisfy such a need. Therefore, research on compound semiconductors having excellent material properties is actively underway.
化合物半導体の代表的なＧａＡｓでは、インゴットが成
長すると結晶内部に転位空虚格子点、格子間原子及びＡ
ｓ析出物などの欠陥が発生する。このような欠陥などは
結晶内で不均一に分布することになるので、Ｚｏｃｈｒ
ａｌｓｋｉ氏による一般的なＬＥＣ（カプセルに包まれ
た液体）法によって生産されたインゴットから作られた
ウェーハを利用して素子を製作すると素子特性が不均一
になって信頼性が低下する。従って上記ウェーハを所定
の熱処理を行なって欠陥などを均一に分布させ、均一の
電気的特性を有するようにする。In GaAs, which is a typical compound semiconductor, when an ingot grows, dislocation void lattice points, interstitial atoms, and A
s Defects such as precipitates occur. Since such defects are distributed unevenly in the crystal, Zochr
When a device is manufactured using a wafer made of an ingot produced by the general LEC (Liquid Encapsulated Liquid) method by Alski, the device characteristics become non-uniform and the reliability is lowered. Therefore, the wafer is subjected to a predetermined heat treatment so that defects and the like are evenly distributed and have uniform electric characteristics.
第２図は従来の化合物半導体のウェーハの熱処理方法を
示している。先ず熱処理用ウェーハ１の両側面にこの熱
処理用ウェーハ１と同一の種類の保護用ウェーハ３など
を接触させ過剰試料５と共に石英などから作ったチュー
ブ７の中に入れる。次に、上記チューブ７の内部を真空
状態にして密封した後ヒーター９でチューブ７を加熱し
８００〜９００℃程度で数１０分〜数時間維持した後冷
却する。上記の熱処理用ウェーハ１では、ＧａＡｓ時の
ＧａよりＡｓの揮発温度が非常に低いので熱処理工程中
にＡｓの揮発が発生し易い。従って過剰試料５でＡｓを
使用して真空状態のチューブ７内部をＡｓ雰囲気にして
熱処理用ウェーハ１からＡｓが揮発することを抑制す
る。また、上記保護用ウェーハ３などは熱処理用ウェー
ハ１のＡｓが揮発することを抑制するだけでなくこの熱
処理用ウェーハ１にＡｓを供給するようになる。上記に
て熱処理工程を行なう前にチューブ７を真空にする理由
は熱処理用ウェーハ１が酸化及び汚染されることを防止
するためである。FIG. 2 shows a conventional heat treatment method for a compound semiconductor wafer. First, both sides of the heat treatment wafer 1 are contacted with a protection wafer 3 of the same type as the heat treatment wafer 1 and the like, and they are put together with an excess sample 5 into a tube 7 made of quartz or the like. Next, the inside of the tube 7 is evacuated and sealed, and then the tube 7 is heated by the heater 9 and maintained at about 800 to 900 ° C. for several tens of minutes to several hours and then cooled. In the above-mentioned heat treatment wafer 1, the volatilization temperature of As is much lower than that of Ga at the time of GaAs, so that As volatilizes easily during the heat treatment process. Therefore, in the excess sample 5, As is used and the inside of the tube 7 in a vacuum state is set to As atmosphere to suppress the volatilization of As from the heat treatment wafer 1. Further, the protection wafer 3 and the like not only suppress the volatilization of As of the heat treatment wafer 1, but also supply As to the heat treatment wafer 1. The reason why the tube 7 is evacuated before performing the heat treatment step is to prevent the heat treatment wafer 1 from being oxidized and contaminated.
上述の熱処理方法では真空状態のチューブの内部に熱が
加えられＡｓ気体状態にしてＡｓ気体圧力によってウェ
ーハ内のＡｓの組成が制御される。In the heat treatment method described above, heat is applied to the inside of the tube in a vacuum state to bring it into an As gas state, and the composition of As in the wafer is controlled by the As gas pressure.
（発明が解決しようとする課題） しかし、熱処理工程を行なう前のウェーハにはＡｓの析
出物が不均一に分布している。上記不均一に分布してい
るＡｓの析出物によって熱処理工程を行なう時、ウェー
ハの表面にてＡｓの揮発及び内部拡散を均一にするには
難しい問題点があった。また、固体と気体の不均一な界
面状態に熱処理工程を行なう時表面の荒さ及び空虚格子
点などの欠陥が不均一に発生する問題点があった。(Problems to be Solved by the Invention) However, As precipitates are unevenly distributed on the wafer before the heat treatment step. When the heat treatment process is performed by using the non-uniformly distributed As precipitates, it is difficult to uniformly vaporize and internally diffuse As on the surface of the wafer. Further, there is a problem that defects such as surface roughness and void lattice points are nonuniformly generated when a heat treatment process is performed on a nonuniform interface state of solid and gas.
従って、この発明の目的はウェーハの表面及びその内部
にＡｓ析出物が均一に分布することのできる化合物半導
体ウェーハの熱処理方法を提供することにある。Therefore, an object of the present invention is to provide a heat treatment method for a compound semiconductor wafer in which As precipitates can be uniformly distributed on the surface of the wafer and inside thereof.
この発明の他の目的は空虚格子点を表面荒さなどの欠陥
が均一に分布することのできる化合物半導体ウェーハの
熱処理方法を提供することにある。Another object of the present invention is to provide a heat treatment method for a compound semiconductor wafer in which defects such as surface roughness can be evenly distributed in vacant lattice points.
［発明の構成］ （課題を解決するための手段） このような目的を達成するためにこの発明は、高い揮発
性元素を含む化合物半導体ウェーハの熱処理方法におい
て、スライダーの溝に化合物半導体ウェーハを位置さ
せ、ホルダのウェルに試料を入れてウェルの入口を密封
材で密封した後第１次熱を加えて試料を溶融させる工程
と、上記スライダーを移動させ前記溝とウェルとを一致
させ溶融された試料が化合物半導体ウェーハの全表面を
覆うようにした後、第２次熱を加えて化合物半導体ウェ
ーハの表面を均質化する工程と、前記溝とウェルとを分
離して常温で急冷させた後第３次熱を加えて熱誘起応力
を除去する工程とから成ることを特徴とする。[Structure of the Invention] (Means for Solving the Problems) In order to achieve such an object, the present invention provides a method for heat treating a compound semiconductor wafer containing a highly volatile element, wherein the compound semiconductor wafer is positioned in the groove of the slider. Then, a step of putting the sample in the well of the holder and sealing the inlet of the well with a sealing material and then applying primary heat to melt the sample, and moving the slider so that the groove and the well are aligned and melted After the sample is made to cover the entire surface of the compound semiconductor wafer, a second heat is applied to homogenize the surface of the compound semiconductor wafer, and the groove and well are separated and rapidly cooled at room temperature. And a step of removing thermally induced stress by applying tertiary heat.
（実施例） 以下、添付した図面を参照してこの発明を詳細に説明す
る。(Example) Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
第１Ａ図乃至第１Ｃ図はこの発明による化合物半導体ウ
ェーハの熱処理方法を示している。第１Ａ図を参照する
に、所定の洗浄工程によって準備された半絶縁性ＧａＡ
ｓウェーハ１１をスライダー１５の溝１３に位置させ、
このウェーハ１１の化学量論を維持するために１０ｇの
Ｇａ当り３００〜１０００mgの多結晶ＧａＡｓを混合さ
せた試料２１をホルダ１７のウェル１９の中に入れ、こ
のウェル１９を密封材２３で密封した後電気炉の反応管
２５の中に押し込む。上記にて溝１３にウェーハ１１を
位置させる時５０μｍ程度の空隙ｔを有するようにす
る。また上記電気炉は均一の温度分布を維持するように
反応管２５の外部をヒーター２７で覆う。1A to 1C show a heat treatment method for a compound semiconductor wafer according to the present invention. Referring to FIG. 1A, semi-insulating GaA prepared by a predetermined cleaning process.
s Position the wafer 11 in the groove 13 of the slider 15,
To maintain the stoichiometry of the wafer 11, a sample 21 containing 300 to 1000 mg of polycrystalline GaAs per 10 g of Ga was placed in the well 19 of the holder 17, and the well 19 was sealed with the sealing material 23. It is pushed into the reaction tube 25 of the rear electric furnace. When the wafer 11 is positioned in the groove 13 as described above, a gap t of about 50 μm is provided. Further, in the electric furnace, the outside of the reaction tube 25 is covered with a heater 27 so as to maintain a uniform temperature distribution.
次に、上記ヒーター２７を加熱して反応管２５の温度を
６００〜７００℃程度で１〜５時間維持させる。この時
上記試料２１などは溶融され、Ｇａの中に含まれるＧａ
2Ｏ3は上記密封材２３でスラグされる。上記にて密封材
２３は上記溶融された試料２１と反応しないで揮発を発
生しない物質として通常Ｂ2Ｏ3がケーキ状で利用され
る。上記にてＢ2Ｏ3をＨ2Ｏの含有量が２００〜４００p
pm程度の超乾式状態になるようにして上記溶融された試
料２１と酸素とが反応して生成されるＧａ2Ｏ3の量を減
少させる。Next, the heater 27 is heated to maintain the temperature of the reaction tube 25 at about 600 to 700 ° C. for 1 to 5 hours. At this time, the sample 21 and the like are melted and are contained in Ga.
2 O 3 is slagged by the sealing material 23. In the above, the sealing material 23 is usually B 2 O 3 in the form of a cake that does not react with the melted sample 21 and does not generate volatilization. In the above, the content of B 2 O 3 and H 2 O is 200 to 400 p.
The amount of Ga 2 O 3 produced by the reaction of the melted sample 21 and oxygen is reduced so as to be in an ultra dry state of about pm.
第１Ｂ図を参照するに、上記スライダー１５を移動させ
溝１３をウェル１９と一致させるウェーハ１１の表面が
溶融された試料２１で覆われるようになる。次に、温度
を９００℃以上上昇させ２〜５時間維持するとウェーハ
１１の表面に不均一に分布していたＡｓ析出物が再固容
される。第１Ｃ図を参照するに、上記スライダー１５を
所定位置へ移動させ溝１３とウェル１９とを分離させた
後３００〜１２００℃／ｈｒの冷却速度によって常温ま
で冷却する。この時上記ウェーハ１１の表面に空隙の厚
さｔを有するエピタキシャル層が形成される。上記にて
エピタキシャル層２９を急速に冷却するので、Ａｓの拡
散時間は最小化されＡｓ析出物が小さく均一な大きさで
再析出される。また、上記冷却時にウェーハ１１とエピ
タキシャル層２９の間に熱による残留応力が多く存在す
る。従ってヒーター２７を再び加熱して６００〜７００
℃程度の温度で５〜３０時間維持しウェーハ１１とエピ
タキシャル層２９との間の熱誘起残留応力を除去する。
この時、上記急冷時に再析出された小さく均一な大きさ
を持つ核を中心としてＡｓが拡散され均一な大きさのＡ
ｓ析出物が形成される。Referring to FIG. 1B, the slider 15 is moved to align the groove 13 with the well 19, and the surface of the wafer 11 is covered with the melted sample 21. Next, when the temperature is raised to 900 ° C. or higher and maintained for 2 to 5 hours, the As precipitates that are non-uniformly distributed on the surface of the wafer 11 are solidified again. Referring to FIG. 1C, the slider 15 is moved to a predetermined position to separate the groove 13 and the well 19 and then cooled to room temperature at a cooling rate of 300 to 1200 ° C./hr. At this time, an epitaxial layer having a void thickness t is formed on the surface of the wafer 11. Since the epitaxial layer 29 is rapidly cooled as described above, the diffusion time of As is minimized and As precipitates are re-deposited in a small and uniform size. In addition, a large amount of residual stress due to heat exists between the wafer 11 and the epitaxial layer 29 during the cooling. Therefore, the heater 27 is heated again to 600 to 700.
The temperature is kept at about 5 ° C. for 5 to 30 hours to remove the thermally induced residual stress between the wafer 11 and the epitaxial layer 29.
At this time, As is diffused around the small and uniform size nuclei re-precipitated during the rapid cooling, and
s precipitates are formed.
次に、上記ウェーハ１１を冷却した後ポリシング工程を
経て表面に形成されたエピタキシャル層２９を除去し良
質の鏡面を有するウェーハを形成する。また、上述した
熱処理工程の時にウェーハの表面及び内部にある空虚格
子点及びウェーハの表面の荒さなどの欠陥が除去され
る。Next, after cooling the wafer 11, the epitaxial layer 29 formed on the surface is removed through a polishing process to form a wafer having a good mirror surface. In addition, defects such as voids on the surface and inside of the wafer and roughness of the surface of the wafer are removed during the heat treatment process described above.
以上のようにこの発明の実施例としてＧａＡｓを説明し
たが、この発明の思想に逸脱しない限りＩｎＡｓ，Ｉｎ
Ｐ及びＧａＰなどに適用することもできる。Although GaAs has been described as an embodiment of the present invention as described above, InAs, In
It can also be applied to P and GaP.
従って上述のごとく、この発明は多結晶ＧａＡｓが溶解
されたＧａ溶液の液状を利用してＧａＡｓウェーハを熱
処理するのでこのＧａＡｓウェーハの表面及び内部に分
布されるＡｓ析出物及び欠陥などが均一になり電気的特
性が均一になる利点がある。Therefore, as described above, according to the present invention, since the GaAs wafer is heat-treated by utilizing the liquid of Ga solution in which the polycrystalline GaAs is dissolved, As precipitates and defects distributed on the surface and inside of the GaAs wafer become uniform. There is an advantage that the electrical characteristics are uniform.
第１Ａ乃至第１Ｃ図はこの発明による半絶縁性ＧａＡｓ
ウェーハの熱処理方法を示す図、第２図は従来の半絶縁
性ＧａＡｓウェーハの熱処理方法を示す図である。 １１…化合物半導体ウェーハ １３…溝 １５…スライダー １７…ホルダ １９…ウェル ２１…試料 ２３…密封材 ２５…反応管 ２７…ヒーター ２９…エピタキシャル層1A to 1C are semi-insulating GaAs according to the present invention.
FIG. 2 is a diagram showing a heat treatment method for a wafer, and FIG. 2 is a diagram showing a conventional heat treatment method for a semi-insulating GaAs wafer. 11 ... Compound semiconductor wafer 13 ... Groove 15 ... Slider 17 ... Holder 19 ... Well 21 ... Sample 23 ... Sealing material 25 ... Reaction tube 27 ... Heater 29 ... Epitaxial layer
Claims (10)
ハの熱処理方法において、スライダーの溝に化合物半導
体ウェーハを位置させ、ホルダのウェルに試料を入れて
ウェルの入口を密封材で密封した後第１次熱を加えて試
料を溶融させる工程と、 前記スライダーを移動させ上記溝とウェルとを一致させ
溶融された試料が化合物半導体ウェーハの全表面を覆う
ようにした後第２次熱を加えて化合物半導体ウェーハの
表面を均質化する工程と、 前記溝とウェルとを分離して常温で急冷させた後第３次
熱を加えて熱誘起応力を除去する工程とから成る化合物
半導体ウェーハの熱処理方法。1. A heat treatment method for a compound semiconductor wafer containing a highly volatile substance, wherein the compound semiconductor wafer is positioned in a groove of a slider, a sample is put in a well of a holder, and an inlet of the well is sealed with a sealing material. Applying a second heat to melt the sample; moving the slider to align the groove with the well so that the melted sample covers the entire surface of the compound semiconductor wafer; A heat treatment method for a compound semiconductor wafer, comprising: a step of homogenizing a surface of a semiconductor wafer; and a step of separating the groove and the well, quenching them at room temperature, and then applying a third heat to remove thermally induced stress.
の空隙を有するように深さを調節されたことを特徴とす
る請求項（１）記載の化合物半導体ウェーハの熱処理方
法。2. The heat treatment method for a compound semiconductor wafer according to claim 1, wherein the groove has a depth adjusted to have a gap of about 50 μm with the compound semiconductor wafer.
り化合物半導体ウェーハと同一の組成の多結晶物質の３
００〜１０００mgの比率で混合された物質であることを
特徴とする請求項（１）記載の化合物半導体ウェーハの
熱処理方法。3. The sample is 3 g of a polycrystalline material having the same composition as the compound semiconductor wafer per 10 g of the material other than the highly volatile material.
The heat treatment method for a compound semiconductor wafer according to claim 1, wherein the substances are mixed in a ratio of 0 to 1000 mg.
求項（１）記載の化合物半導体ウェーハの熱処理方法。4. The heat treatment method for a compound semiconductor wafer according to claim 1, wherein the sealing material is B 2 O 3 .
m程度であることを特徴とする請求項（４）記載の化合
物半導体ウェーハの熱処理方法。5. B 2 O 3 has a water content of 200 to 400 pp
The heat treatment method for a compound semiconductor wafer according to claim 4, wherein the heat treatment is about m.
〜５時間維持されるように加えられたことを特徴とする
請求項（１）記載の化合物半導体ウェーハの熱処理方
法。6. The primary heat of the sample is 1 at 600 to 700.degree.
The method for heat treating a compound semiconductor wafer according to claim 1, wherein the heat treatment is performed for about 5 hours.
時間維持されるように加えられたことを特徴とする請求
項（１）記載の化合物半導体ウェーハの熱処理方法。7. The secondary heat is 2 to 5 when the sample is 900 ° C. or higher.
The heat treatment method for a compound semiconductor wafer according to claim 1, wherein the heat treatment is performed so that the time is maintained.
ハを常温へ急冷させる時３００〜１２００℃／ｈｒの冷
却速度を持つことを特徴とする請求項（１）記載の化合
物半導体ウェーハの熱処理方法。8. The heat treatment method for a compound semiconductor wafer according to claim 1, wherein the compound semiconductor wafer has a cooling rate of 300 to 1200 ° C./hr when the compound semiconductor wafer is rapidly cooled to room temperature in the stress removing step.
半導体ウェーハであることを特徴とする請求項（１）記
載の化合物半導体ウェーハの熱処理方法。9. The heat treatment method for a compound semiconductor wafer according to claim 1, wherein the compound semiconductor wafer is a III-V group compound semiconductor wafer.
ＧａＡｓ，ＩｎＡｓ，ＧａＰ及びＩｎＰ中の一つである
ことを特徴とする請求項（９）記載の化合物半導体ウェ
ーハの熱処理方法。10. The heat treatment method for a compound semiconductor wafer according to claim 9, wherein the III-V compound semiconductor wafer is one of GaAs, InAs, GaP and InP.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31571390A JPH0642489B2 (en) | 1990-11-22 | 1990-11-22 | Heat treatment method for compound semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31571390A JPH0642489B2 (en) | 1990-11-22 | 1990-11-22 | Heat treatment method for compound semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04188626A JPH04188626A (en) | 1992-07-07 |
| JPH0642489B2 true JPH0642489B2 (en) | 1994-06-01 |
Family
ID=18068644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31571390A Expired - Fee Related JPH0642489B2 (en) | 1990-11-22 | 1990-11-22 | Heat treatment method for compound semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0642489B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102004036435B4 (en) | 2003-08-07 | 2007-08-30 | Nanophotonics Ag | Holding device for disc-shaped objects |
-
1990
- 1990-11-22 JP JP31571390A patent/JPH0642489B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04188626A (en) | 1992-07-07 |
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