JPH04184949A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH04184949A
JPH04184949A JP31461890A JP31461890A JPH04184949A JP H04184949 A JPH04184949 A JP H04184949A JP 31461890 A JP31461890 A JP 31461890A JP 31461890 A JP31461890 A JP 31461890A JP H04184949 A JPH04184949 A JP H04184949A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
tab tape
surfaces
chip
pressure fixing
thermal pressure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31461890A
Inventor
Yuichi Asano
Kenji Kobayashi
Yusuke Suzuki
Original Assignee
Fujitsu Miyagi Electron:Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PURPOSE: To facilitate the increase in a device capacity by a method wherein the surfaces of two chips whereon elements are formed are bonded onto both surfaces of one TAB tape.
CONSTITUTION: An Au wire is fed from a capillary onto Al electrode pads formed on the surface of a chip 1 so as to form the Al ball bumps as outer connecting electrodes 2 by ultrasonic thermal pressure fixing step. Next, thic chip 1 and the Au bumps of a pattern chip 1 having mirror-inverted surface are aligned with the wirings printed on both surfaces of a TAB tape 3 by the alignment step using X-rays and then the TAB tape 3 comprising PI tape with a Cu foil stuck thereon is inner-lead bonded by the thermal pressure fixing step. Furthermore, the TAB tape 3 is outer-lead bonded onto the lead frames 4 comprising Cu-plated 42 alloy also by the thermal pressure fixing step. Finally, the whole body from the chips 1 to the lead frames 4 is seal-molded in epoxy base molding resin 5 using a molding machine to complete a memory IC.
COPYRIGHT: (C)1992,JPO&Japio
JP31461890A 1990-11-20 1990-11-20 Semiconductor device and manufacture thereof Pending JPH04184949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31461890A JPH04184949A (en) 1990-11-20 1990-11-20 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31461890A JPH04184949A (en) 1990-11-20 1990-11-20 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH04184949A true true JPH04184949A (en) 1992-07-01

Family

ID=18055475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31461890A Pending JPH04184949A (en) 1990-11-20 1990-11-20 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH04184949A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471369A (en) * 1993-07-09 1995-11-28 Fujitsu Limited Semiconductor device having a plurality of semiconductor chips
US5757080A (en) * 1995-03-30 1998-05-26 Sharp Kabushiki Kaisha Resin-sealed semiconductor device
US5793108A (en) * 1995-05-30 1998-08-11 Sharp Kabushiki Kaisha Semiconductor integrated circuit having a plurality of semiconductor chips

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471369A (en) * 1993-07-09 1995-11-28 Fujitsu Limited Semiconductor device having a plurality of semiconductor chips
US5579208A (en) * 1993-07-09 1996-11-26 Fujitsu Limited Semiconductor device having a plurality of semiconductor chips
US5724233A (en) * 1993-07-09 1998-03-03 Fujitsu Limited Semiconductor device having first and second semiconductor chips with a gap therebetween, a die stage in the gap and associated lead frames disposed in a package, the lead frames providing electrical connections from the chips to an exterior of the packag
US5757080A (en) * 1995-03-30 1998-05-26 Sharp Kabushiki Kaisha Resin-sealed semiconductor device
US5793108A (en) * 1995-05-30 1998-08-11 Sharp Kabushiki Kaisha Semiconductor integrated circuit having a plurality of semiconductor chips

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