JPH04184949A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH04184949A JPH04184949A JP2314618A JP31461890A JPH04184949A JP H04184949 A JPH04184949 A JP H04184949A JP 2314618 A JP2314618 A JP 2314618A JP 31461890 A JP31461890 A JP 31461890A JP H04184949 A JPH04184949 A JP H04184949A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- tab tape
- tape
- chips
- external connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000015654 memory Effects 0.000 abstract description 7
- 239000011347 resin Substances 0.000 abstract description 6
- 229920005989 resin Polymers 0.000 abstract description 6
- 238000000465 moulding Methods 0.000 abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 239000004593 Epoxy Substances 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000010931 gold Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000010949 copper Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明は、半導体装置の製造方法、特にＩＣチップのパ
ッケージへの搭載方法に関し。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for mounting an IC chip on a package.
メモリ等の半導体デバイスの容量アップを容易に行なえ
ることを目的とし。The purpose is to easily increase the capacity of semiconductor devices such as memory.
■ 素子形成された２個のチップの各々が、該チップの
素子形成面に形成された外部接続電極を介して、１個の
ＴＡ Ｂ （Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄ
ｉｎｇ）テープの両面に接合されているように。(2) Each of the two chips on which elements are formed is connected to one TA B (Tape Automated Bond) via an external connection electrode formed on the element forming surface of the chip.
ing) as bonded to both sides of the tape.
■ 素子形成されたチップの表面に外部接続電極を形成
する工程と、該外部接続電極が形成された２個の該チッ
プをそれぞれ、該外部接続電極を介してＴＡＢテープの
両面に接続する工程と、該ＴＡＢテープをリードフレー
ムにアウターリードボンディングする工程とを含むよう
に構成する。(2) A step of forming external connection electrodes on the surface of the chip on which elements have been formed, and a step of connecting each of the two chips on which the external connection electrodes are formed to both sides of the TAB tape via the external connection electrodes. and outer lead bonding of the TAB tape to a lead frame.
（産業上の利用分野〕
本発明は、半導体装置とその製造方法、特にＩＣのチッ
プのパッケージへの搭載方法に関する。(Industrial Application Field) The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a method for mounting an IC chip onto a package.
近年のメモリー系半導体は１年々大容量化が進んで来て
おり、ワンチップ内の回路設計上のみての対応が難しく
なってきている。In recent years, the capacity of memory semiconductors has been increasing year by year, and it has become difficult to accommodate this in terms of circuit design within a single chip.
また２回路内に組み込む事により、チップの大型化が進
み、従来のパッケージに搭載できなくなる恐れもある。Furthermore, by incorporating the chip into two circuits, the chip becomes larger and there is a possibility that it will not be possible to mount it in a conventional package.
第３図は従来例の説明図である。 FIG. 3 is an explanatory diagram of a conventional example.
図において、６はチップ、７は金（Ａｕ）バンブ。In the figure, 6 is a chip and 7 is a gold (Au) bump.
８はＴＡＢテープ、９はリードフレーム、 １０はモ
ールド樹脂である。8 is a TAB tape, 9 is a lead frame, and 10 is a mold resin.
従来は、同一のパッケージ内にメモリの２個の同一種類
のチップを搭載し、既存のチップでメモリー容量を２倍
にする方式が採られていた。Conventionally, two memory chips of the same type were mounted in the same package, doubling the memory capacity of the existing chip.
しかし、この従来方式では、第３図（ａ）に示すように
、チップ６の表面に形成されたアルミニウム（Ａｆ）パ
ッドの上に、 Ａｕワイヤーボールボンド方式によるＡ
ｕバンブ７を形成し、第３図（ｂ）に示すように、 Ａ
ｕバンブ７上にＴＡＢテープ８のインナーリードボンデ
ィングを熱圧着方式で行ない、続いて、第３図（Ｃ）に
示すように、リードフレーム４のアウターリードボンデ
ィングを熱圧着方式で行なった後、第３図（ｄ）に示す
ように。However, in this conventional method, as shown in FIG.
A U bump 7 is formed, as shown in FIG. 3(b).
Inner lead bonding of the TAB tape 8 is performed on the u-bump 7 by thermocompression bonding, and then outer lead bonding of the lead frame 4 is performed by thermocompression bonding as shown in FIG. 3(C). As shown in Figure 3(d).
チップ６の裏面を上向きに反転させる。Flip the back side of the chip 6 upward.
続いて、アウターボンディングの完了したチップ６に対
してミラー反転させたチップ６″を、先のチップ６と同
様にインナーリードボンディングまで行ない、第３図（
ｅ）に示すように、リードフレーム４のアウターリード
ボンディングを熱圧着方式で行ない、第３図（ｆ）に示
すように、リードフレーム４を含めて、チップ６全体を
モールド樹脂ｌＯで封止成形を行ない半導体装置を完成
する。 ゛
〔発明が解決しようとする課題〕
しかし、このチップの裏面同士を貼りつける方式は、２
個のチップの表側が外側に面するために。Next, the chip 6'', which is mirror-inverted with respect to the chip 6 for which the outer bonding has been completed, is subjected to inner lead bonding in the same manner as the previous chip 6, and as shown in FIG.
As shown in e), the outer lead bonding of the lead frame 4 is performed by thermocompression bonding, and as shown in FIG. Then, the semiconductor device is completed. [Problem to be solved by the invention] However, this method of attaching the back sides of chips to each other is
so that the front side of the chip faces outward.
実際の製造工程中においては、チップの表面にきずが入
りやすい。During the actual manufacturing process, scratches are likely to occur on the surface of the chip.
更に、ＴＡＢテープをあらかじめ鉤型に加工しておく必
要があり１作業性の点において問題があった０
本発明は９以上の点を鑑み、メモリ等の半導体デバイス
の容量アップを容易に行なえることを目的として提供さ
れるものである。Furthermore, it is necessary to process the TAB tape into a hook shape in advance, which poses problems in terms of workability.The present invention takes into account the above points and makes it easy to increase the capacity of semiconductor devices such as memories. It is provided for this purpose.
第１図は本発明の原理説明図、第２図は本発明の一実施
例の工程順模式断面図である。FIG. 1 is an explanatory diagram of the principle of the present invention, and FIG. 2 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps.
図において、ｌはチップ、２は外部接続電極。In the figure, l is a chip and 2 is an external connection electrode.
３はＴＡＢテープ、４はリードフレーム、５はモールド
樹脂である。3 is a TAB tape, 4 is a lead frame, and 5 is a mold resin.
本発明は、チップ２個を素子形成された表面同士を１個
のＴＡＢテープの両面に貼り合わせるものである。In the present invention, the surfaces of two chips on which elements are formed are bonded to both sides of one TAB tape.
この場合、ＴＡＢテープ及び外部接続電極のパッドやバ
ンブを介在するので、互いのチップの表面が接触する危
険性はない。In this case, since the TAB tape and the pads and bumps of the external connection electrodes are interposed, there is no risk that the surfaces of the chips will come into contact with each other.
即ち９本発明の目的は、第１図に示すように。That is, the object of the present invention is as shown in FIG.
素子形成された２個のチップ１の各々が、該チップｌの
素子形成面に形成された外部接続電極２を介して、１個
のＴＡＢテープ３の両面に接合されていることにより。Each of the two chips 1 on which elements are formed is bonded to both sides of one TAB tape 3 via the external connection electrode 2 formed on the element formation surface of the chip 1.
また、第２図（ａ）に示すように、素子形成されたチッ
プｌの表面に外部接続電極２を形成する工程と。Further, as shown in FIG. 2(a), a step of forming external connection electrodes 2 on the surface of the chip 1 on which elements have been formed.
第２図（ｂ）に示すように、該外部接続電極２が形成さ
れた２個の該チップｌをそれぞれ、該外部接続電極２を
介してＴＡＢテープ３の両面に接続する工程と。As shown in FIG. 2(b), the two chips 1 on which the external connection electrodes 2 are formed are respectively connected to both sides of the TAB tape 3 via the external connection electrodes 2.
第２図（Ｃ）に示すように、該ＴＡＢテープ３をリード
フレーム４にアウターリードボンディングする工程とを
含むことにより達成される。This is achieved by including the step of outer lead bonding the TAB tape 3 to the lead frame 4, as shown in FIG. 2(C).
この方式であれば、チップの表面に傷がつくこともなく
、ＴＡＢテープもわざわざ曲げて使う必要がなくなる。With this method, there will be no damage to the surface of the chip, and there will be no need to bend the TAB tape.
また、チップの裏側が外に向いているため、その後の工
程における作業性も良くなる。Additionally, since the back side of the chip faces outward, workability in subsequent steps is improved.
第２図は本発明の半導体装置の工程順模式断面図である
。FIG. 2 is a schematic cross-sectional view of the semiconductor device of the present invention in the order of steps.
第２図により本発明の一実施例について説明する。An embodiment of the present invention will be explained with reference to FIG.
先ず、第２図（ａ）に示すように、チップ６の表面に形
成された素子のＡｌ電極パッド上に、 ２０μｍ径のＡ
ｕ線を使用して、キャピラリーよりＡｕ線を送り出し、
１５０℃の超音波熱圧着によりＡｕボールのバンブを外
部接続電極２として形成する。First, as shown in FIG. 2(a), an A with a diameter of 20 μm is placed on the Al electrode pad of the element formed on the surface of the chip 6.
Using the U line, send out the Au line from the capillary,
Au ball bumps are formed as external connection electrodes 2 by ultrasonic thermocompression bonding at 150°C.
次に、第２図（ｂ）に示すように、このチップ１と表面
をミラー反転したパターンのチップ１゜のＡｕバンプを
それぞれに、ＴＡＢテープ３の両面に印刷した配線にｘ
＃Ｉによるアライメント方式を用いて位置合わせをおこ
なった後、ＰＩテープに銅（Ｃｕ）箔を貼ったＴＡＢテ
ープに４５０ ”Ｃで熱圧着方式によりインナーリード
ボンディングを行う。Next, as shown in FIG. 2(b), a 1° Au bump with a mirror-reversed pattern on the surface of this chip 1 is attached to the wiring printed on both sides of the TAB tape 3.
After positioning using #I alignment method, inner lead bonding is performed by thermocompression bonding at 450''C to TAB tape with copper (Cu) foil pasted on PI tape.
更に、第２図（Ｃ）に示すように、４２アロイにＣｕめ
っきを行ったリードフレーム４にＴＡＢテープ３を４０
０℃で熱圧着方式によりアウターリードボンディングを
行う。Furthermore, as shown in FIG. 2(C), a 40mm TAB tape 3 is attached to a lead frame 4 made of 42 alloy plated with Cu.
Outer lead bonding is performed using a thermocompression method at 0°C.
最後に、第２図（ｄ）に示すように、エポキシ系のモー
ルド樹脂を使用し、モールド成形機によりチップＩから
リードフレーム４までを封止成形してメモリＩＣを完成
する。Finally, as shown in FIG. 2(d), the memory IC is completed by sealing and molding the chip I to the lead frame 4 using an epoxy molding resin using a molding machine.
以上説明した様に９本発明によれば従来方式の５工程が
３工程に短縮される。また、チップを貼り付ける工程が
不要であり、ＴＡＢテープ１個では不安定のようである
が、樹脂でモールドすれば問題はない。As explained above, according to the present invention, the five steps of the conventional method are shortened to three steps. Additionally, there is no need for a process for attaching the chip, and although it seems unstable with just one TAB tape, there is no problem if it is molded with resin.
更に、チップの表面に傷がつくこともなく、 ＴＡＢテ
ープもわざわざ曲げて使う必要がなるなる他、チップの
裏側が外に向いているため、その後の工程における搬送
等の作業性も良くなる。Furthermore, the surface of the chip is not damaged, there is no need to bend the TAB tape, and the back side of the chip faces outward, which improves workability in subsequent processes such as transportation.
第１図は本発明の原理説明図。 第２図は本発明の一実施例の工程順模式断面図。 第３図は従来例の説明図 である。 図において。 ｌはチップ、 ２は外部接続電極。 ３はＴＡＢテープ、 ４はリードフレーム。 ５はモールド樹脂 冨 ２ 記 FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps. Figure 3 is an explanatory diagram of the conventional example. It is. In fig. l is the chip, 2 is the external connection electrode. 3 is TAB tape, 4 is lead frame. 5 is mold resin Tomi 2
Claims (1)
ップ（１）の素子形成面に形成された外部接続電極（２
）を介して、１個のＴＡＢテープ（３）の両面に接合さ
れていることを特徴とする半導体装置。 ２）素子形成されたチップ（１）の表面に外部接続電極
（２）を形成する工程と、 該外部接続電極（２）が形成された２個の該チップ（１
）をそれぞれ、該外部接続電極（２）を介してＴＡＢテ
ープ（３）の両面に接続する工程と、 該ＴＡＢテープ（３）をリードフレーム（４）にアウタ
ーリードボンディングする工程とを含むことを特徴とす
る半導体装置の製造方法。[Claims] 1) Each of the two chips (1) on which an element is formed has an external connection electrode (2) formed on the element formation surface of the chip (1).
) A semiconductor device characterized in that it is bonded to both sides of a single TAB tape (3) via a tape. 2) Forming an external connection electrode (2) on the surface of the chip (1) on which an element has been formed;
) to both sides of the TAB tape (3) via the external connection electrode (2), and outer lead bonding of the TAB tape (3) to the lead frame (4). A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2314618A JPH04184949A (en) | 1990-11-20 | 1990-11-20 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2314618A JPH04184949A (en) | 1990-11-20 | 1990-11-20 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04184949A true JPH04184949A (en) | 1992-07-01 |
Family
ID=18055475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2314618A Pending JPH04184949A (en) | 1990-11-20 | 1990-11-20 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04184949A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5471369A (en) * | 1993-07-09 | 1995-11-28 | Fujitsu Limited | Semiconductor device having a plurality of semiconductor chips |
| US5757080A (en) * | 1995-03-30 | 1998-05-26 | Sharp Kabushiki Kaisha | Resin-sealed semiconductor device |
| US5793108A (en) * | 1995-05-30 | 1998-08-11 | Sharp Kabushiki Kaisha | Semiconductor integrated circuit having a plurality of semiconductor chips |
-
1990
- 1990-11-20 JP JP2314618A patent/JPH04184949A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5471369A (en) * | 1993-07-09 | 1995-11-28 | Fujitsu Limited | Semiconductor device having a plurality of semiconductor chips |
| US5579208A (en) * | 1993-07-09 | 1996-11-26 | Fujitsu Limited | Semiconductor device having a plurality of semiconductor chips |
| US5724233A (en) * | 1993-07-09 | 1998-03-03 | Fujitsu Limited | Semiconductor device having first and second semiconductor chips with a gap therebetween, a die stage in the gap and associated lead frames disposed in a package, the lead frames providing electrical connections from the chips to an exterior of the packag |
| US5757080A (en) * | 1995-03-30 | 1998-05-26 | Sharp Kabushiki Kaisha | Resin-sealed semiconductor device |
| US5793108A (en) * | 1995-05-30 | 1998-08-11 | Sharp Kabushiki Kaisha | Semiconductor integrated circuit having a plurality of semiconductor chips |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3255646B2 (en) | Method for manufacturing resin-encapsulated semiconductor device | |
| US6878570B2 (en) | Thin stacked package and manufacturing method thereof | |
| JP3619773B2 (en) | Manufacturing method of semiconductor device | |
| JP4097403B2 (en) | Semiconductor device | |
| JP3461720B2 (en) | Resin-sealed semiconductor device | |
| JP3958522B2 (en) | Semiconductor device | |
| JP2005531137A (en) | Partially patterned leadframe and method for its manufacture and use in semiconductor packaging | |
| JP2001274316A (en) | Semiconductor device and its manufacturing method | |
| JPH0722567A (en) | Molding resin sealed type semiconductor device and its manufacture | |
| JPH04184949A (en) | Semiconductor device and manufacture thereof | |
| JP3443406B2 (en) | Resin-sealed semiconductor device | |
| JP3842241B2 (en) | Semiconductor device | |
| JP3954585B2 (en) | Semiconductor device | |
| JP3954586B2 (en) | Semiconductor device | |
| JP3756338B2 (en) | Manufacturing method of semiconductor device | |
| JP4162758B2 (en) | Manufacturing method of semiconductor device | |
| TW461060B (en) | Packaging method for die with central pad | |
| JP4750076B2 (en) | Manufacturing method of semiconductor device | |
| JPH08153826A (en) | Semiconductor integrated circuit device | |
| JP2011210936A (en) | Method of manufacturing semiconductor device, and semiconductor device | |
| JP4335203B2 (en) | Manufacturing method of semiconductor device | |
| JP2681145B2 (en) | Resin-sealed semiconductor device | |
| JPH08274234A (en) | Semiconductor device, its manufacture, and semiconductor packaging module | |
| KR940008329B1 (en) | Semiconductor package using inter connect lead and manufacturing method thereof | |
| JP2001068582A (en) | Semiconductor device and manufacture thereof |