461060 A7 B7 6617twf.doc/008 五、發明說明（I ) (請先閲讀背面之注意事項再填寫本頁) 本發明是有關於一種封裝方式，且特別是有關於一 種具有中央分佈銲墊（central pad )之晶粒的覆晶接合技 術。 第一階層封裝主要係將晶粒連接到承載器（carrier ) 上，大致有三種封裝型態，分別爲銲線（wire bond )、軟 片自動接合（Tape Automated Bonding, TAB )以及覆晶接合 技術。而晶片上搭載導線（Lead On Chip，簡稱LOC )型態 的封裝方式在電氣特性表現與晶粒尺寸都有較多的好處， 因此目前仍被業界廣泛的使用。一般採晶片上搭載導線 (LOC )型態封裝之晶粒，其大部分必需採用傳統銲線的方 法，由於銲線無法避免寄生電感與寄生電容的問題，所以 電器特性比不上以覆晶接合技術封裝之晶粒。若將具有中 央分佈銲墊之晶粒利用覆晶接合技術與承載器接合時，由 於晶粒上之銲墊分佈集中在晶粒的中央處，會使得組裝後 的信賴性（reliability )出現問題。 經濟部智慧財產局員工消費合作社印製 請參照第1A圖，其繪示爲習知具有中央分佈銲墊之 晶粒，以銲線方式將晶粒與承載器連接的示意圖。首先提 供一具有中央分佈銲墊1〇2之晶粒100，以及一搭載於晶 粒100上之承載器104 ’承載器1〇4上具有數個接點106。 習知以銲線方式將晶粒1〇〇與承載器104連接的方式，係 以晶粒100上的銲墊102爲第一銲點，而以承載器1〇4上 之接點106爲第二銲點，利用打線機先將金線的端點燒結 成小球，輔以超音波震動將小球壓銲在銲墊102上，接著 沿著設計好的路徑（如第1圖所繪不），將金線拉銲於承 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 461060 6617twf-doc/008 五、發明說明) 載器104之接點106上，之後再拉斷金線，即完成一條銲 線108的製作。如此不斷的重複即可完成晶粒1〇〇上的所 有銲線動作。由於銲線無法避免寄生電感與寄生電容的問 題，所以電器特性比不上以覆晶接合技術進行封裝之晶 粒。 接著請參照第1B圖，具有中央分佈銲墊102之晶粒 100，由於銲墊102集中分佈於晶粒100之中央，若進行 覆晶接合時，晶粒100的邊緣因爲缺乏支撐’使得在覆晶 接合時，晶粒100上的銲墊102與基板110上的接點112 部分，會承受到很大的應力。此外，在晶粒接合時的支撐 點集中分佈於晶粒100的中央，並非均勻分佈於晶粒100 上，所以若直接將具有中央分佈銲墊102之晶粒100進行 晶粒接合，將會影響元件的信賴性。 上述習知中晶片上搭載導線（LOC )型態之晶粒，其 大部分仍需採用傳統銲線的封裝方式’由於銲線無法避免 寄生電感與寄生電容的問題，所以電器特性比不上以覆晶 接合技術進行封裝之晶粒。 習知晶片上搭載導線（LOC )型態之晶粒，也可以採 用軟片自動接合再搭配以傳統銲線的封裝方式，之後再進 行銲線，由於銲線同樣無法避免寄生電感與寄生電容的.問 題，所以電器特性比不上以覆晶接合技術進行封裝之晶 粒。 且習知中具有中央分佈銲墊之晶粒，由於銲墊集中 分佈於晶粒之中央，若要進行覆晶接合時，晶粒的邊緣因 4 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） illlllllli - I I (請先閱讀背面之注意事項再填寫本頁) - -•rt 經濟部智慧財產局員工消費合作社印製 A7 B7 461060 6617twf-doc/008 五、發明說明（+ ) 爲缺乏支撐，容易於接合時，在晶粒中央承受到較大的應 力，且接合的支撐點不能均勻分佈於晶粒表面，影響其信 賴性。 因此，本發明提出一種具有中央分佈轉塾（central pad ) 晶粒的覆晶接合技術’以有效克服習知於中央分佈銲墊晶 粒中易產生銲線寄生電感、電容的缺點。 爲達上述之目的，本發明提出一種適用於具有中央 分佈銲墊晶粒的封裝方式，主要係於具有中央分佈銲墊晶 粒邊緣之適當位置形成適當數目的支撐墊（dummy pad )， 以作爲後序覆晶接合時平衡晶粒的支撐點。同時於承載器 或是印刷電路板(Printed Circuit Board,簡稱PCB )上，對 應於銲墊與支撐墊的位置形成接點。接著，於晶粒上之銲 墊、支撐墊上進行導體凸塊製作。最後再將晶粒翻覆，進 行晶粒與基板或是印刷電路板之間的接合步驟，以使晶粒 上之導體凸塊與基板或是印刷電路板上之接點接合。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例’並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： 第1Α圖繪示爲習知具有中央分佈銲墊之晶粒，以銲 線方式將晶粒與承載器連接的示意圖。 第1Β圖繪示爲習知具有中央分佈銲墊之晶粒，以覆 晶接合技術將晶粒與承載器連接後，應力集中於中央分佈 銲墊上的剖面示意圖。 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 丨 · I I ! I 訂!1丨丨1· V-,、 經濟部智慧財產局員工消費合作杜印製 經濟部智慧財產局員工消費合作社印製 461060 A7 6617twf.doc/008 __B7_五、發明說明（^ ) 第2圖繪示爲依照本發明第一實施例與第二實施例 中具有中央分佈銲墊與支撐墊之晶粒俯視圖。 第3圖至第5圖繪示爲依照本發明第一實施例具有 中央分佈銲墊之晶粒，以覆晶接合技術將晶粒與基板連接 的流程剖面示意圖。 第6圖至第8圖繪示爲依照本發明第二實施例具有 中央分佈銲墊之晶粒，以覆晶接合技術將晶粒與印刷電路 .板連接的流程剖面示意圖。 標號之簡單說明： 100、200 :晶粒 102、202 :銲墊 104 :承載器 106:承載器上之接點 108 :銲線 110:基板 112 :基板上之接點 204 :支撐墊 206 :球底金屬層 206a:阻障層 206b:銅金屬層 208 :保護層 210 :導體凸塊 212 :基板 214 :基板上之接點 6 (請先閱讀背面之注意事項再填寫本頁) —裝 訂----- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 461060 6617twf.doc/008 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（t) 216:印刷電路板 218 :印刷電路板上之接點 第一實施例 覆晶接合技術主要是於晶粒的銲墊上形成導體凸 塊’例如爲錫鉛凸塊，藉由這些導體凸塊與基板或是印刷 電路板接合’因此覆晶接合技術具有晶粒與基板之間短路 徑的優點。 首先，請參照第2圖’其繪示爲依照本發明第一實 施例具有中央分佈銲墊與支撐墊之晶粒俯視圖。首先提供 一具有數個中央分佈銲墊202與數個支撐墊204之晶粒 200 ’其中’中央分佈的銲墊202係分佈於晶粒200的中 央區域，而數個支撐墊204例如分佈於晶粒200的邊緣， 其材質例如與銲墊202相同，爲鋁金屬。由於晶粒200在 後續進行覆晶接合的過程中，會經過導體凸塊製作、晶粒 翻覆以及晶粒接合等步驟，因此支撐墊204分佈的位置與 其數目，以可分散集中於銲墊202上之應力爲原則。此外， 支撐墊204的大小與高度約與中央分佈之銲墊202相當， 使支撐墊204在覆晶接合時，可以分散集中於銲墊202上 之應力。 接著請參照第3圖至第5圖，其繪示爲依照本發明 第一實施例具有中央分佈銲墊之晶粒，以覆晶接合技術將 晶粒與基板連接的流程剖面示意圖。 請參照第3圖，提供一具有數個中央分佈銲墊202 與數個支撐墊204之晶粒200。其中，支撐墊204與銲墊 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱〉 --------II ,ίν·裝 - -------訂·！-------r'、 <請先閱讀背面之注§項再填寫本頁) A7 B7 461060 6617twf.doc/008 五、發明說明（〔） 202係於半導體之前段製程中同時完成。且支撐墊2〇4的 大小與高度約與中央分佈之銲墊202相等，使支撐墊2〇4 在覆晶接合時，可以分散原集中於中央分佈銲墊2〇2上之 應力。 接著於晶粒200上之銲墊202與支撐墊204上進行 導體凸塊210的製作。於晶粒200上形成一多層結構之球 底金屬層 206( Under Bump Metallurgy,.簡稱 UBM )，覆蓋 於晶粒200表面之銲墊202、支撐墊204及保護層208上。 此球底金屬層206例如爲一層作爲阻障層206a之鈦金屬 層以及一層銅金屬層206b之雙層結構。接著，再於銲墊202 與支撐墊204上方以外之區域上形成一層經圖案化之光阻 層（未繪示），以此圖案化之光阻層爲罩幕，於暴露出之 球底金屬層206上進行導體凸塊210的成長，導體凸塊210 的形成方法例如以蒸鍍、印刷或電鍍方式形成一錫鉛合金 材質之錫鉛凸塊。在形成導體凸塊210之後將光阻剝除， 並以導體凸塊210爲罩幕，將未受導體凸塊210覆蓋之球 底金屬層206移除至暴露出保護層208爲止。最後進行迴 銲使導體凸塊210因表面張力的緣故而呈現球形。 接著請參照第4圖，提供一基板212，基板212上具 有數個接點214。基板212上之接點214的位置對應於晶 粒200上銲墊2〇2與支撐墊204之位置。接著於導體凸塊 210塗上助銲劑，並由一晶粒接合機進行辨識對位，以將 該晶粒200放置在基板212上，使銲墊202與支撐墊204 能夠分別與基板212的接點214相接合。 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ! ! I 蜃 i ! β (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 B7 461060 6617twf.d〇c/008 五、發明說明（^) 請參照第5圖，經過晶粒接合機進行辨識對位之步· 驟之後，進行一迴銲的步驟，將銲墊202與支撐墊204藉 由導體凸塊210與基板212上之接點214接合。在晶粒接 合之後，再將具有晶粒200之基板212與一印刷電路板（未 繪示）接合，即完成具有中央分佈銲墊晶粒200的覆晶式 構裝,。 第二實施例 第6圖至第8圖繪示爲依照本發明第二實施例具有 中央分佈銲墊之晶粒，以覆晶接合技術將晶粒與印刷電路 板連接的流程剖面示意圖。 請參照第6圖，於晶粒200上之銲墊202與支撐墊204 上進行導體凸塊210的製作。於晶粒200上形成一多層結 構之球底金屬層 206( Under Bump Metallurgy, UBM )’ 覆 蓋於晶粒200表面之銲墊202、支撐墊204及保護層208 上。此球底金屬層206例如爲一層作爲阻障層206a之鈦 金屬層以及一層銅金屬層206b之雙層結構。接著，再於 銲墊202與支撐墊.204上方以外之區域上形成一層經圖案 化之光阻層（未繪示），以此圖案化之光阻層爲罩幕’於 暴露出之球底金屬層206上進行導體凸塊210的成長’導 體凸塊210的形成方法例如以蒸鍍、印刷或電鍍方式形成 一錫鉛合金材質之錫鉛凸塊。在形成導體凸塊210之後將 光阻剝除，並以導體凸塊210爲罩幕，將未受導體凸塊210 覆蓋之球底金屬層206移除至暴露出保護層208爲止。最 後進行迴銲使導體凸塊210因表面張力的緣故而呈現球 9 本紙張尺度適用中國國家標準(21〇 x 297公17 (請先閲讀背面之注意事項再填寫本頁) 裝----丨訂----------广V. 經濟部智慧財產局員工消費合作社印製 4 6106 0 6617twf.doc/008 B7 五、發明說明（X ) 形。 (請先閲讀背面之注意事項再填寫本頁) 接著請參照第7圖，提供一印刷電路板216，印刷電 路板216上具有數個接點218。印刷電路板216上之接點 218的位置對應於晶粒200上銲墊202與支撐墊204之位 置。接著於導體凸塊210塗上助銲劑’並由一晶粒接合機 進行辨識對位，以將該晶粒200精準的放置在印刷電路板 216上，使銲墊202與支撐墊204能夠準確對準於印刷電 路板216的接點218上。 請參照第8圖’經過晶粒接合檄進行辨識對位之步 驟之後，進行一迴銲的步驟，將銲墊202與支撐墊204藉 由導體凸塊210與印刷電路板216上之接點218接合’即 完成具有中央分佈銲墊晶粒200的覆晶式組裝。 藉由位於晶粒200邊緣之支撐墊204的支撐’可使 晶粒200在覆晶接合的過程中，晶粒200邊緣的支撐墊204 可以分散應力，而有效改善信賴性的問題。而支撐墊204 的支撐功能甚至可以省去於晶粒與基板或是印刷電路板之 間塡膠（Underfill )的製程。 綜上所述，本發明至少具有下列優點： 經濟部智慧財產局員工消費合作社印製 1. 本發明中具有中央分佈銲墊之晶粒，以覆晶接合技 術將晶粒構裝或是組裝於基板或是印刷電路板上，可避免 習知銲線技術無法避免之寄生電感、電容問題，大大的增 進了元件的信賴性。 2. 本發明於具有中央分佈銲墊之晶粒的邊緣適當位置 加入適當數目之支撐墊，而支撐墊的大小及高度約與中央 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） 461060 6617twf-doc/〇〇8 A7 B7 五、發明說明（q ) 分佈之銲墊相等，因此支撐墊在覆晶接合時，可以分散集 中於銲墊上之應力增進信賴性。使得具有中央分佈銲墊之 晶粒可以應用覆晶接合技術進行組裝或構裝。 3.本發明具有中央分佈銲墊之晶粒邊緣，於適當位置 加入適當數目之支撐墊，支撐墊的功能甚至可以省去於晶 粒與基板或是印刷電路板之間塡膠的製程。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作各種之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 -----— —is 裝.--I!丨訂！ ---广'.、 (請先閲讀背面之注意事項再填窝本頁} 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）461060 A7 B7 6617twf.doc / 008 V. Description of the Invention (I) (Please read the precautions on the back before filling this page) The present invention relates to a packaging method, and in particular to a method with a centrally distributed pad (central pad) chip bonding technology. The first-level package is mainly used to connect the die to a carrier. There are roughly three types of packages, namely wire bond, tape auto bonding (TAB), and flip-chip bonding technology. The lead-on-chip (LOC) type of packaging method has many advantages in electrical characteristics and die size, so it is still widely used in the industry. Generally, the chip mounted with a wire (LOC) type package on the chip must use the traditional bonding wire method. Because the bonding wire cannot avoid the problems of parasitic inductance and parasitic capacitance, the electrical characteristics are not comparable to flip-chip bonding. Dies for technology packaging. If the die with a centrally distributed pad is bonded to the carrier using flip-chip bonding technology, the distribution of the pads on the die is concentrated at the center of the die, which will cause problems in reliability after assembly. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to Figure 1A, which is a schematic diagram of a conventional die with a centrally distributed pad, and the die is connected to the carrier by wire bonding. First, a die 100 having a centrally distributed pad 102 and a carrier 104 ′ mounted on the die 100 are provided with a plurality of contacts 106. Conventionally, the method of connecting the die 100 to the carrier 104 by a wire bonding method is to use the pad 102 on the die 100 as the first solder joint, and the contact 106 on the carrier 104 as the first solder joint. For two solder joints, the end of the gold wire is sintered into a small ball by a wire drawing machine, and the small ball is pressure-welded to the pad 102 with ultrasonic vibration, and then along the designed path (as shown in Figure 1) ), The gold wire is drawn and welded to the paper size of 3 papers which are applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) A7 B7 461060 6617twf-doc / 008 V. Description of the invention) Contact 106 of the carrier 104 Then, after the gold wire is broken, the production of a bonding wire 108 is completed. This continuous repetition can complete all the bonding wire actions on the grain 100. Because the bonding wire cannot avoid the problems of parasitic inductance and parasitic capacitance, the electrical characteristics are inferior to those of crystal chips packaged with flip-chip bonding technology. Next, please refer to FIG. 1B, the die 100 with the centrally distributed pads 102. Because the pads 102 are concentratedly distributed in the center of the die 100, if the flip-chip bonding is performed, the edges of the die 100 are not supported because of the lack of support. During die bonding, the portion of the bonding pad 102 on the die 100 and the contact 112 on the substrate 110 is subjected to a large stress. In addition, the support points during the die bonding are concentrated in the center of the die 100 and are not evenly distributed on the die 100. Therefore, if the die 100 with the centrally distributed pad 102 is directly bonded to the die, it will affect the Component reliability. In the above-mentioned conventional chip with a wire (LOC) type, most of them still need to be packaged with traditional bonding wires. 'Because bonding wires cannot avoid the problems of parasitic inductance and parasitic capacitance, electrical characteristics are inferior to Chip-on-chip bonding technology. It is known that the die equipped with a wire (LOC) type on the chip can also be automatically bonded with a flexible film and then combined with a traditional bonding wire packaging method, and then bonding the wire, because the bonding wire can not avoid parasitic inductance and parasitic capacitance. The problem is that the electrical characteristics are not comparable to those of die packaged with flip-chip bonding technology. And the grains with centrally distributed pads are known in the art. Because the pads are concentrated in the center of the grains, the edge of the grains is 4 times the size of the paper applicable to the Chinese National Standard (CNS) A4 specification for flip-chip bonding. (21〇x 297 mm) illlllllli-II (Please read the notes on the back before filling out this page)--• rt Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 461060 6617twf-doc / 008 5. Description of the invention (+) Due to the lack of support, it is easy to bear large stress in the center of the grain when joining, and the support points of the joint cannot be evenly distributed on the surface of the grain, which affects its reliability. Therefore, the present invention proposes a flip-chip bonding technology 'with a centrally distributed pad crystal grain to effectively overcome the shortcomings of the conventionally-produced bonding wire parasitic inductance and capacitance in the centrally distributed pad crystal grains. In order to achieve the above-mentioned object, the present invention proposes a packaging method suitable for a die with a centrally distributed pad, which is mainly formed by forming an appropriate number of dummy pads at appropriate positions on the edges of the die with the centrally distributed pad, as a dummy pad. Support points for balancing grains during subsequent flip-chip bonding. At the same time, a contact is formed on the carrier or a printed circuit board (Printed Circuit Board (PCB)) corresponding to the position of the solder pad and the support pad. Next, conductor bumps are fabricated on the solder pads and support pads on the die. Finally, the die is overturned, and the bonding step between the die and the substrate or the printed circuit board is performed, so that the conductor bumps on the die are bonded with the contacts on the substrate or the printed circuit board. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A illustrates In order to familiarize the die with a centrally distributed pad, a schematic diagram of connecting the die to the carrier by a bonding wire. Figure 1B is a schematic cross-sectional view of a conventional die with a centrally distributed bonding pad. After the die and the carrier are connected by flip-chip bonding technology, the stress is concentrated on the centrally distributed bonding pad. 5 This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) 丨 · II! I order! 1 丨 丨 V- ,, economic Printed by the Intellectual Property Bureau of the Ministry of Intellectual Property, printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by 461060 A7 6617twf.doc / 008 __B7_ V. Description of the Invention (^) Top view of a die with a centrally distributed pad and support pad in the second embodiment. Figures 3 to 5 are schematic cross-sectional views showing the flow of a die having a centrally distributed bonding pad according to the first embodiment of the present invention, and the die is connected to the substrate by a flip-chip bonding technique. Figures 6 to 8 are schematic cross-sectional views of the process of connecting the die to the printed circuit board using the flip-chip bonding technology according to the second embodiment of the present invention. Brief description of the numbers: 100, 200: die 102, 202: pad 104: carrier 106: contact 108 on the carrier 108: bonding wire 110: substrate 112: contact on the substrate 204: support pad 206: ball Bottom metal layer 206a: Barrier layer 206b: Copper metal layer 208: Protective layer 210: Conductor bump 212: Substrate 214: Contact 6 on the substrate (Please read the precautions on the back before filling this page) --Binding-- --- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 461060 6617twf.doc / 008 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economy B7 V. Description of invention (t) 216: Printed circuit Board 218: Contacts on a printed circuit board. The first embodiment of the flip-chip bonding technology is to form conductor bumps on the die pads, such as tin-lead bumps. These conductor bumps are connected to the substrate or the printed circuit. 'Board bonding' therefore flip-chip bonding technology has the advantage of a short path between the die and the substrate. First, please refer to FIG. 2 ', which is a top view of a die having a centrally distributed pad and a support pad according to the first embodiment of the present invention. First, a die 200 having a plurality of centrally distributed pads 202 and a plurality of support pads 204 is provided. Among them, the centrally distributed pads 202 are distributed in the central region of the die 200, and the plurality of support pads 204 are, for example, distributed on the crystals. The material of the edge of the pellet 200 is, for example, the same as that of the bonding pad 202 and is aluminum metal. Since the die 200 is subsequently subjected to the flip-chip bonding process, it will go through the steps of conductor bump production, die flipping, and die bonding. Therefore, the positions and numbers of the support pads 204 are distributed to be concentrated on the pads 202. Stress as a principle. In addition, the size and height of the support pad 204 are approximately equal to those of the centrally distributed pads 202, so that the stresses on the pads 202 can be dispersed during the flip-chip bonding. Please refer to FIG. 3 to FIG. 5, which are schematic cross-sectional flow diagrams of the process of connecting the die to the substrate by the flip-chip bonding technology according to the die having a centrally distributed pad according to the first embodiment of the present invention. Referring to FIG. 3, a die 200 with a plurality of centrally distributed pads 202 and a plurality of support pads 204 is provided. Among them, the support pad 204 and the solder pad 7 The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) -------- II, ίν · installation-------- order ·! ------- r ', < Please read the note § on the back before filling this page) A7 B7 461060 6617twf.doc / 008 V. Description of the invention ([) 202 is in the previous stage of semiconductor manufacturing Completed at the same time. In addition, the size and height of the support pad 204 is approximately equal to that of the centrally distributed pad 202, so that the support pad 204 can disperse the stress originally concentrated on the centrally distributed pad 202 when the flip-chip bonding is performed. Then, the conductive bump 210 is fabricated on the bonding pad 202 and the supporting pad 204 on the die 200. A multi-layered ball-bottom metal layer 206 (UBM) is formed on the die 200, and is covered on the solder pad 202, the support pad 204, and the protective layer 208 on the surface of the die 200. The ball-bottom metal layer 206 is, for example, a two-layer structure of a titanium metal layer as a barrier layer 206a and a copper metal layer 206b. Next, a patterned photoresist layer (not shown) is formed on the areas other than above the bonding pad 202 and the support pad 204, and the patterned photoresist layer is used as a mask to expose the exposed ball-bottom metal. The conductor bump 210 is grown on the layer 206. The method for forming the conductor bump 210 is, for example, forming a tin-lead bump made of tin-lead alloy by evaporation, printing, or electroplating. After the conductive bump 210 is formed, the photoresist is peeled off, and the conductive bump 210 is used as a mask to remove the ball-bottom metal layer 206 not covered by the conductive bump 210 until the protective layer 208 is exposed. Finally, re-soldering is performed to make the conductor bump 210 appear spherical due to surface tension. Referring to FIG. 4, a substrate 212 is provided. The substrate 212 has a plurality of contacts 214. The positions of the contacts 214 on the substrate 212 correspond to the positions of the solder pads 202 and the support pads 204 on the wafer 200. Next, the solder bump 210 is coated with a flux, and is identified and aligned by a die bonding machine to place the die 200 on the substrate 212 so that the bonding pad 202 and the supporting pad 204 can be connected to the substrate 212 respectively. The points 214 are joined. 8 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)!! I 蜃 i! Β (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs B7 461060 6617twf.d〇c / 008 V. Description of the invention (^) Please refer to Figure 5 after the step of identifying and aligning the grain bonding machine, and then perform a step of re-soldering to connect the pad 202 to the support The pad 204 is bonded to the contact 214 on the substrate 212 through the conductor bump 210. After the die bonding, the substrate 212 with the die 200 is bonded to a printed circuit board (not shown) to complete the flip-chip structure with the centrally distributed pads die 200. Second Embodiment FIGS. 6 to 8 are cross-sectional schematic diagrams showing the flow of a die having a centrally distributed bonding pad according to a second embodiment of the present invention for connecting the die to a printed circuit board using a flip-chip bonding technique. Referring to FIG. 6, the conductor bump 210 is fabricated on the bonding pad 202 and the supporting pad 204 on the die 200. A multi-layered ball-bottom metal layer 206 (UnBump Metallurgy, UBM) 'is formed on the die 200 and covered on the pad 202, the support pad 204, and the protective layer 208 on the surface of the die 200. The ball-bottom metal layer 206 is, for example, a two-layer structure of a titanium metal layer serving as a barrier layer 206a and a copper metal layer 206b. Then, a patterned photoresist layer (not shown) is formed on the areas other than above the pad 202 and the support pad .204, and the patterned photoresist layer is used as a mask on the exposed ball bottom. The method of forming the conductive bump 210 on the metal layer 206 is to form a conductive bump 210 such as a tin-lead bump made of tin-lead alloy by evaporation, printing, or plating. After the conductive bump 210 is formed, the photoresist is peeled off, and the conductive bump 210 is used as a mask to remove the ball-bottom metal layer 206 not covered by the conductive bump 210 until the protective layer 208 is exposed. Finally, re-soldering is performed to make the conductor bump 210 appear as a ball 9 due to surface tension. This paper size applies to Chinese national standards (21 × x297 mm 17 (please read the precautions on the back before filling this page).丨 Order ---------- Canton V. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6106 0 6617twf.doc / 008 B7 V. Invention Description (X) (Please read the note on the back first Please fill in this page again) Then refer to Figure 7 to provide a printed circuit board 216, which has several contacts 218. The position of the contacts 218 on the printed circuit board 216 corresponds to the die 200 soldering The positions of the pad 202 and the support pad 204. Next, the solder bumps 210 are coated with a flux 'and identified and aligned by a die bonding machine, so that the die 200 is accurately placed on the printed circuit board 216 for soldering. The pad 202 and the support pad 204 can be accurately aligned with the contacts 218 of the printed circuit board 216. Please refer to FIG. 8 after the step of identifying and positioning through the die bonding, and then performing a re-soldering step to place the pad 202 and support pad 204 through conductor bump 210 and contact 2 on printed circuit board 216 18 junctions' completes the flip-chip assembly with the centrally distributed pads die 200. With the support of the support pad 204 located at the edge of the die 200, the die 200 can be bonded to the edges of the die 200 during the flip-chip bonding process. The support pad 204 can disperse stress and effectively improve the problem of reliability. The support function of the support pad 204 can even omit the process of underfill between the die and the substrate or the printed circuit board. As mentioned above, the present invention has at least the following advantages: 1. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 1. The die with a centrally distributed pad in the present invention is structured or assembled on a substrate by flip-chip bonding technology. The printed circuit board can avoid the problems of parasitic inductance and capacitance that cannot be avoided by the conventional bonding wire technology, which greatly improves the reliability of the component. 2. The present invention adds an appropriate number of suitable positions on the edge of the die with a centrally distributed bonding pad. The size and height of the support pad are about the same as the central paper size. The Chinese national standard (CNS) A4 specification (210 X 297) is applicable. 461060 6617twf-doc / 〇〇8 A7 B7 V. Description of the invention (q) The distributed pads are equal, so the support pads can disperse the stress concentrated on the pads to improve the reliability during flip-chip bonding, so that the die with a centrally distributed pad can be applied with flip-chip bonding technology. Assembly or construction. 3. The present invention has a die edge with a centrally distributed pad, and an appropriate number of support pads are added at appropriate positions. The function of the support pad can even be omitted between the die and the substrate or the printed circuit board. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. -----— —is equipment .-- I! 丨 Order! --- Guang '., (Please read the notes on the back before filling in this page} Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)