JP2003100988A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a reliable multi-chip package with simple package configuration at low cost. SOLUTION: A semiconductor device 1 is so constituted that QFN semiconductor devices 1a and 1b are stacked. The semiconductor devices 1a and 1b are so formed that outer leads 5a and dams 6 for connection are exposed in areas extending from the mounting face to the surface (face opposite the mounting face) of the package 9 thereof. The dams 6 for connection of the lower semiconductor device 1a and the outer leads 13a of the upper semiconductor device 1b are connected with each other through conductive adhesive 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to two or more QFNs (Quad).
Flat Non-leaded package)
The present invention relates to a technique effectively applied to a multi-chip package in which semiconductor devices are stacked.

[0002]

2. Description of the Related Art A so-called multi-chip package is widely known as a technique for improving the packaging density of semiconductor devices. As one of the multi-chip packages, for example, TSOP (Thin Small Outli)
There is a multi-stage stacking type semiconductor device in which two or more semiconductor devices such as a ne page) are stacked.

In this case, the packages of the semiconductor device are mounted in multiple stages, and the respective joint portions of the outer leads that overlap each other are electrically connected by solder or the like.

Incidentally, as an example in which a semiconductor device of this kind has been described in detail, May 31, 1993, Nikkei B.
Published by Company P, Susumu Kayama, Kunihiko Naruse (Author), "Practice Course VL"
SI packaging technology (bottom) "P180, P181
There is a TCP (Tape Carri) in this document.
er package) in a multi-stage stacking type semiconductor device.

[0005]

However, the inventor of the present invention has found that the above-mentioned high-density technology using the multi-chip package has the following problems.

That is, since the outer leads of the semiconductor devices mounted in multiple stages are overlapped to make electrical connection, the positional accuracy of the outer leads is very important, making it difficult to stack in multiple stages and complicating the package structure. Therefore, there is a problem that the cost of the semiconductor device is significantly increased.

An object of the present invention is to provide a semiconductor device capable of forming a highly reliable multi-chip package at a low cost with a simple package structure and a manufacturing method thereof.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, in the semiconductor device of the present invention, the external electrodes for inputting / outputting external signals are formed on the same plane as the end surface of the package, and the external electrodes are formed from the mounting surface of the package to the surface opposite to the mounting surface. Is.

Further, the semiconductor device of the present invention is formed by stacking a first semiconductor device and a second semiconductor device on an upper stage of the first semiconductor device, and is provided in the first and second semiconductor devices. External electrodes for inputting and outputting the generated external signal are formed on the same plane as the end surface of the package from the mounting surface of the package to the surface opposite to the mounting surface, and the external electrode formed on the opposite surface of the first semiconductor device. An external electrode formed on the mounting surface of the second semiconductor device is polymerized and connected, and is laminated.

Further, the semiconductor device of the present invention is formed by stacking the first semiconductor device and the second semiconductor device on the upper stage of the first semiconductor device, and is provided in the first and second semiconductor devices. External electrodes for inputting and outputting external signals are formed on the same plane as the end surface of the package from the mounting surface of the package to the surface opposite to the mounting surface, and the external electrode formed on the opposite surface of the first semiconductor device and The external electrodes formed on the mounting surface of the second semiconductor device are superposed and connected to each other, and the external electrodes formed on the mounting surface of the first semiconductor device in which the second semiconductor device is stacked on the upper stage are mounted on the mounting substrate. It is mounted by being connected to the electrodes formed on.

A method of manufacturing a semiconductor device according to the present invention is
A step of preparing a lead frame having a plurality of device regions and having a connecting dam connected to the upper surface of the outer lead;
A step of preparing a semiconductor chip to be mounted in the device area of the lead frame; a step of adhesively fixing the semiconductor chip to the device area of the lead frame; a surface electrode of the semiconductor chip and the inner lead of the lead frame corresponding thereto With a connecting member, a plurality of device regions in the lead frame are collectively covered with a molding resin, the semiconductor chip is resin-sealed and a collective sealing portion is formed, and the device region is formed along the dicing line. And a step of dividing the lead frame and the collective sealing portion into individual pieces and forming individual packages in which outer leads and connecting dams are exposed from the mounting surface to the surface opposite to the mounting surface.

Further, the method of manufacturing a semiconductor device of the present invention comprises a step of preparing a lead frame having a plurality of device regions and having a connecting dam connected to the upper surface of the outer lead, and mounting the lead frame in the device region of the lead frame. A semiconductor chip to be prepared, a step of adhesively fixing the semiconductor chip to a device region of the lead frame, and a step of connecting a surface electrode of the semiconductor chip and an inner lead of the lead frame corresponding thereto by a connecting member. A step of collectively covering a plurality of device regions in the lead frame with a molding resin, resin-sealing the semiconductor chips and forming a collective encapsulation part, and the lead frame and the collective encapsulation for each device area along the dicing line. The stopper is divided into individual pieces, and the outer surface is mounted from the mounting surface to the surface opposite to the mounting surface. Forming individual packages with exposed terminals and connecting dams, forming a first semiconductor device and a second semiconductor device stacked on top of the first semiconductor device, and forming the package And a step of connecting the external electrode formed on the opposite surface of the formed first semiconductor device and the external electrode formed on the mounting surface of the second semiconductor device.

Further, in the method of manufacturing a semiconductor device of the present invention, the connecting dam has the same shape as the external electrode, and for example, has a width of about 0.3 mm and a length of about 0.5 to.
It has a rectangular shape of about 1.0 mm.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view of a lead frame used in the semiconductor device of FIG. 1, and FIGS. 3 to 8 are semiconductor devices of FIG. 9 is an explanatory view of wire bonding in a semiconductor device provided in a lower stage of the semiconductor device in FIG. 1, and FIG. 10 is a description of wire bonding in a semiconductor device stacked in an upper stage of the semiconductor device in FIG. FIG. 11 and FIG. 11 are flowcharts illustrating manufacturing steps in the semiconductor device of FIG.

In the present embodiment, the semiconductor device 1 is
It consists of BGA which is one of the surface mount type packages. As shown in FIG. 1, this semiconductor device 1 has a DRAM (Dy
natural Random Access Memor
The semiconductor device (first semiconductor device) 1a including a semiconductor memory such as y) is laminated in the lower stage, and the semiconductor device (second semiconductor device) 1b also including a semiconductor memory such as a DRAM is laminated in the upper stage. There is. These semiconductor devices 1a and 1b are composed of QFN which is one of non-lead surface mount packages.

The semiconductor device 1a is formed by the so-called collective molding (MAP) method, and the semiconductor chip 2 is located in the central portion. A bonding pad (surface electrode) 3 which is an electrode is provided at the center of the semiconductor chip 2.
Are arranged.

A plurality of inner leads 5 are located near the bonding pads 3 of the semiconductor chip 2, and the inner leads 5 extend to form outer leads (external electrodes) 5a which serve as external connection lines. .

A connection dam (external electrode) 6 is connected to the surface of these outer leads 5a via a conductive adhesive 7 such as solder or silver paste. This connecting dam 6 has the same shape as the outer lead 5a,
For example, a width of about 0.3 mm and a length of about 0.5 to 1.0
It is a rectangle of about mm and is made of the same metal material as the lead frame LF (FIG. 2) such as iron or copper.

The tip of the inner lead 5 is located below the semiconductor chip 2 and has a LOC structure. The semiconductor chip 2 is connected to the inner leads 5 via the adhesive material 4.

The tip of the inner lead 5 and the semiconductor chip 2
The bonding pads 3 are electrically connected to each other by bonding wires (connection members) 8 made of gold wire or the like.

Further, the semiconductor chip 2, the inner leads 5,
Further, the bonding wire 8 is sealed with a thermosetting sealing resin to form a rectangular package 9. The package 9 is formed by the collective molding method described above.

On the four sides of the package 9, a plurality of outer leads 5a are formed so as to be exposed from the mounting surface to the side surface of the package 9. Similarly, the connecting dam 6 is formed so as to be exposed from the side surface of the package 9 to the surface (the surface opposite to the mounting surface).

Further, the upper semiconductor device 1b is also formed by the collective molding method.
The structure is similar to that of the semiconductor device 1a, and a bonding pad (surface electrode) 11 is arranged at the center of the semiconductor chip 10, and an inner lead is provided below the semiconductor chip 10 with an adhesive 12 interposed therebetween. 13 has a LOC structure in which the tip is located.

A plurality of inner leads 13 are located near the bonding pad 11, and the inner leads 13 extend to form outer leads (external electrodes) 13a. A connecting dam (external electrode) 14 is connected to the surface of the outer lead 13 a via a conductive adhesive material 15. The tip of the inner lead 13 and the bonding pad 11 are bonded to each other by a bonding wire (connection member) 1
6 are electrically connected to each other.

Further, the semiconductor chip 10 and the inner leads 1
3 and the bonding wire 16 are sealed with a sealing resin to form a rectangular package 17.

On the four sides of the package 17, a plurality of outer leads 13a are formed so as to be exposed from the mounting surface to the side surface of the package 17, and the connecting dam is provided from the side surface to the surface (opposite to the mounting surface) of the package 17. 14
Are formed to be exposed.

The semiconductor device 1a has a printed wiring board 18 made of BT (bismaleimide resin) or the like.
Mounted on the main surface of the printed wiring board 18, the electrodes formed on the printed wiring board 18 and the outer leads 13a of the semiconductor device 1a are polymerized and connected to each other via a conductive adhesive material 19 such as solder. On the back surface (mounting surface) of the printed wiring board 18, connection electrodes and wiring patterns arranged in an array are formed, and these connection electrodes include:
Solder bumps 20 made of spherical solder are respectively formed.

The outer leads 13a of the semiconductor device 1b are connected to the connection dams 6 exposed from the surface of the package 9 of the semiconductor device 1a via the conductive adhesive material 21, and the semiconductor device 1b is connected to the semiconductor device 1b. It is laminated on the upper stage of 1a.

Next, the semiconductor device 1 according to the present embodiment
1 and 2 for explaining the manufacturing process of the lead frame, FIGS. 3 to 8 for explaining the manufacturing process, FIGS. 9 and 10 for explaining wire bonding, and FIG. 11 for explaining the flowchart. To do.

Although the case of manufacturing the semiconductor device 1a is described here, the manufacturing process of the semiconductor device 1b is the same as that of the semiconductor device 1a.

First, the lead frame LF shown in FIG. 2 and the semiconductor chip 2 mounted on the lead frame LF.
Are prepared (step S101). The lead frame LF is collectively molded by resin molding so as to collectively cover the plurality of device areas DA defined by the dicing lines DL1 and DL2.

The dicing line DL1 is an area for separating the device area DA portion which becomes a pair, and the dicing line DL2 is for the lead frame LF and the device area DA.
This is an area that separates from the part.

Further, as shown in FIG. 3, a connecting dam 6 is previously connected to the surface of the outer lead 5a of the lead frame LF via a conductive adhesive material 7. Then, the adhesive 4 is applied to the inner leads 5 of the lead frame LF, and the semiconductor chip 2 is mounted and fixed by adhesion (step S102).

Thereafter, as shown in FIG. 4, the bonding pad 3 of the semiconductor chip 2 and the inner lead 5 are bonded by the bonding wire 8 and electrically connected (step S103).

After this wire bonding, the semiconductor chip 2, the bonding wires 8 and the inner leads 5 are resin-sealed by performing a collective molding using a mold for transfer molding. As the mold resin, for example, an epoxy thermosetting resin or the like is used.

After that, the molding resin is hardened, and FIG.
As shown in FIG. 5, a collective mold part (collective sealing part) MB is formed (step S104).

Then, as shown in FIG. 6, the dicing lines DL1 and DL2 in the collective molding portion MB are divided into individual device areas DA by dicing using a blade which is a cutting blade for dicing (individualization (individualization). Step S105).

By this dicing, the semiconductor device 1a is formed as shown in FIGS. Then, the semiconductor device 1a is subjected to a predetermined memory test (step S106).

The semiconductor device 1b is also manufactured in the same manner. The manufacturing process in this semiconductor device 1b is the same as the process of steps S101 to S106, except that the connection destination of the data input / output pin DQ in the wire bonding process is different.

In the wire bonding process, as shown in FIG.
As shown in FIG. 10, the power supply voltage VCC and the reference potential VS
The semiconductor device 1a, 1b has the same connection destination (same pin) with respect to a common pin such as S or a control signal, but the semiconductor device 1a, 1b will be bonded to different connection destinations.

Thereafter, the semiconductor devices 1a and 1b thus formed and the printed wiring board 18 on which the solder bumps 20 are formed are prepared (step S10).
7). The solder bumps 20 are formed on the printed wiring board 18 by, for example, a printing method or a transfer method.

Then, the outer lead 5 of the semiconductor device 1a
Conductive adhesives 19 and 21 are applied to the respective surfaces of a and the connection dam 6 (step S108), the semiconductor device 1a is mounted on the printed wiring board 18, and then the semiconductor device 1b is placed on the upper stage of the semiconductor device 1a. Are loaded (step S109).

The printed wiring boards 18 on which the semiconductor devices 1a and 1b are mounted are electrically connected by reflow (step S110), and the semiconductor device 1 is completed (step S111).

Here, a case will be described in which the semiconductor device 1 is manufactured by using a lead frame having an ordinary metal ribbon structure instead of the MAP method.

Since the semiconductor device 1a and the semiconductor device 1b have the same manufacturing process, the semiconductor device 1a is the same.
The manufacturing process in will be described.

First, the lead frame and the semiconductor chip 2 to be mounted on the lead frame are prepared. This lead frame is formed, for example, by etching or pressing a metal plate made of iron or copper and patterning it.

An inner lead 5 and an outer lead 5a which serves as an external electrode portion are formed on the lead frame.
It is composed of a metal ribbon structure in which several patterns are connected.

A connecting dam 6 is attached to the outer lead 5a.
They are connected via a conductive adhesive 7 such as solder or silver paste. The adhesive 4 is applied to the inner leads 5 of the lead frame, and the semiconductor chip 2 is mounted and fixed by adhesion.

After that, the bonding pad 3 of the semiconductor chip 2 and the inner lead 5 are bonded to each other by the bonding wire 8 and electrically connected. After this wire bonding, the outer lead 5a of the lead frame and the connecting dam 6 are sandwiched in the thickness direction of the lead frame by using a molding die, and resin is injected into the cavity for molding, and the semiconductor chip 2, the bonding wire 8 and the inner leads 5 are resin-sealed to form a package 9.

Thereafter, the outer lead 5a and the connecting dam 6 are cut, the outer lead 5a and the connecting dam 6 exposed along the side surface from the front surface to the back surface of the package 9 are formed, and a predetermined memory test of the semiconductor device 1a is performed. Done.

Then, the formed semiconductor devices 1a, 1
b and the printed wiring board 18 on which the solder bumps 20 are formed are prepared. After the conductive adhesives 19 and 21 are applied to the surfaces of the outer leads 5a and the connection dams 6 of the semiconductor device 1a and the semiconductor device 1a is mounted on the printed wiring board 18, the semiconductor device is placed on the upper stage of the semiconductor device 1a. Load 1b. Semiconductor devices 1a and 1b
The printed wiring boards 18 on which are mounted are electrically connected by reflow, and the semiconductor device 1 (FIG. 1) is completed.

In the completed semiconductor device 1, the solder bumps 20 formed on the printed wiring board 18 are polymerized with the lands that will be the connection electrodes formed on the mounting wiring board of the electronic device or the like, and are reflowed to be electrically respectively. Connected.

Therefore, according to the present embodiment, the QF
Since a multi-chip package can be realized only by stacking N semiconductor devices 1a and 1b, a lead frame or the like having a special outer lead shape can be eliminated, and the semiconductor devices 1a and 1b can be superposed. Can be easy.

Further, since the lead frame LF used for a normal QFN can be used, the semiconductor devices 1a and 1b can be manufactured in the existing manufacturing process, and the cost of the semiconductor device 1 can be reduced. .

Further, since the semiconductor devices 1a and 1b can be tested individually, the yield of the semiconductor device 1 can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-mentioned embodiment, the semiconductor device having the BGA structure in which the solder bumps are formed on the printed wiring board is described, but the electronic system is directly mounted without using the printed wiring board having the solder bumps. The semiconductor device 1 may be mounted on a wiring board (mounting board) P or the like.

In this case, as shown in FIG. 12, the mounting surface of the outer lead 5a in the lower semiconductor device 1a is connected to the electrode of the mounting wiring board via the solder H or the like.

Further, although the semiconductor devices to be stacked have the LOC structure in the above-mentioned embodiment, the semiconductor devices are stacked, but as shown in FIGS. 13 and 14, they are stacked by flip-chip connection. Alternatively, a semiconductor device may be formed.

The semiconductor device of FIG. 13 (first semiconductor device)
In 1a ₁ , the bonding pads of the semiconductor chip 2 are formed in the central portion of the semiconductor chip 2, and bumps (connection members) 22 such as solder are formed on these bonding pads, and the bumps 22 are connected to the inner leads 5 Press to connect.

Further, in the semiconductor device (first semiconductor device) 1a ₂ of FIG. 14, the bonding pads of the semiconductor chip 2 are formed in the vicinity of two opposite sides of the semiconductor chip 2 and these bonding pads are formed. Bumps 22 such as solder are formed, and the bumps 22 are pressed against the inner leads 5 for connection.

Further, according to the above-mentioned embodiment, two semiconductor devices are laminated, but for example, the semiconductor device ₁₁ has three (or more) semiconductor devices as shown in FIG. it may be stacked semiconductor device _{1 1 a~1 1} c.

[0066] In this case, may be laminated by mixed the semiconductor device 1 ₁ b of the semiconductor device ₁ 1 a, 1 1 c and LOC structure of the flip-chip connection.

[0067]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) Since a multi-chip package can be realized only by stacking first and second semiconductor devices having the same shape, it is easy to stack the first and second semiconductor devices. You can

(2) Further, a lead frame having a special outer lead shape is not required, and the first and second semiconductor devices can be manufactured in the existing manufacturing process.
The manufacturing cost of the semiconductor device can be reduced.

(3) Due to the above (1) and (2), cost reduction can be realized while greatly improving the reliability of the semiconductor device of the multi-chip package.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view of a lead frame used in the semiconductor device of FIG.

FIG. 3 is an explanatory diagram of a manufacturing process in the semiconductor device of FIG.

FIG. 4 is an explanatory diagram of the manufacturing process of the semiconductor device, following FIG. 3;

FIG. 5 is an explanatory diagram of the manufacturing process of the semiconductor device, following FIG. 4;

FIG. 6 is an explanatory diagram of the manufacturing process of the semiconductor device, following FIG. 5;

FIG. 7 is an explanatory diagram of the manufacturing process of the semiconductor device, following FIG. 6;

FIG. 8 is an explanatory diagram of the manufacturing process of the semiconductor device, following FIG. 7;

9 is an explanatory diagram of wire bonding in the semiconductor device provided in the lower stage of the semiconductor device in FIG.

FIG. 10 is an explanatory diagram of wire bonding in a semiconductor device stacked on the upper stage of the semiconductor device in FIG.

11 is a flow chart illustrating a manufacturing process in the semiconductor device of FIG.

FIG. 12 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

FIG. 13 is a sectional view showing an example of a semiconductor device used for stacking according to another embodiment of the present invention.

FIG. 14 is a cross-sectional view showing another example of a semiconductor device used for stacking according to another embodiment of the present invention.

FIG. 15 is a sectional view showing an example of a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

1 semiconductor device 1 _first semiconductor device 1a semiconductor device (first semiconductor device) 1a _1, 1a ₂ semiconductor device (first semiconductor device) 1b semiconductor device (the second semiconductor device) ₁ 1 a to 1 ₁ c semiconductor device 2 Semiconductor Chip 3 Bonding Pad (Surface Electrode) 4 Adhesive 5 Inner Lead 5a Outer Lead (External Electrode) 6 Connection Dam (External Electrode) 7 Conductive Adhesive 8 Bonding Wire (Connecting Member) 9 Package 10 Semiconductor Chip 11 Bonding Pad (Surface electrode) 12 Adhesive material 13 Inner lead 13a Outer lead (external electrode) 14 Connection dam (external electrode) 15 Conductive adhesive material 16 Bonding wire (connection member) 17 Package 18 Printed wiring board 19 Conductive adhesive material 20 Solder bump 21 conductive adhesive 22 bump (connecting member) LF lead frame Arm DL1, DL2 dicing line DA device area P mounting wiring board (mounting board)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 25/18 (72) Inventor Sei Horiuchi 5-22-1, Kamisuihonmachi, Kodaira-shi, Tokyo Stock company (72) Inventor of Hitachi Ultra L.S.I.Systems Toshihiro Tsuboi 5-22-1 Kamisuihonmachi, Kodaira-shi, Tokyo Hitachi Ultra L.S.I.Systems (72) Inventor Dr. Tamai 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Group (72) Inventor Yutaka Kagaya 64 Nagano, Tenno, Tenno-cho, Minamiakita-gun, Akita Prefecture F-term (Reference) ) 4M109 AA01 BA01 CA21 DA02 5F067 AA02 AB04 BC14 BE10 CB02 CB05 CC02 CC07 DA05 EA01 EA04

Claims (5)

[Claims] 1. A semiconductor device in which an external electrode for inputting / outputting an external signal is formed on the same plane as an end surface of a package, wherein the external electrode is formed from a mounting surface of the package to a surface opposite to the mounting surface. A semiconductor device characterized by the above. 2. A semiconductor device formed by stacking a first semiconductor device and a second semiconductor device on an upper stage of the first semiconductor device, the semiconductor device being provided in the first and second semiconductor devices. External electrodes for inputting and outputting an external signal are formed on the same plane as the end surface of the package from the mounting surface of the package to the surface opposite to the mounting surface, and the external electrode formed on the opposite surface of the first semiconductor device. A semiconductor device, characterized in that the external electrode formed on the mounting surface of the second semiconductor device is polymerized and connected to be laminated. 3. A semiconductor device formed by stacking a first semiconductor device and a second semiconductor device on an upper stage of the first semiconductor device, wherein the semiconductor device is provided in the first and second semiconductor devices. External electrodes for inputting and outputting external signals are formed on the same plane as the end surface of the package from the mounting surface of the package to the surface opposite to the mounting surface, and the external electrode formed on the opposite surface of the first semiconductor device and An external electrode formed on the mounting surface of the first semiconductor device in which the second semiconductor device is stacked and connected to the external electrode formed on the mounting surface of the second semiconductor device by superposition and connection. A semiconductor device, wherein the semiconductor device is mounted by being connected to an electrode formed on a mounting substrate. 4. A step of preparing a lead frame having a plurality of device regions, in which a connecting dam is connected to an upper surface of an outer lead, and a step of preparing a semiconductor chip mounted in the device region of the lead frame, A step of adhering and fixing the semiconductor chip to a device region of the lead frame; a step of connecting a surface electrode of the semiconductor chip and an inner lead of the lead frame corresponding thereto by a connecting member; A step of collectively covering a device region with a mold resin, resin-sealing the semiconductor chips and forming a collective sealing portion, the lead frame and the collective sealing portion along the dicing line for each device region. Is divided into individual pieces, and from the mounting surface to the surface opposite to the mounting surface, Utarido, and a method of manufacturing a semiconductor device characterized by a step of forming individual packages the connecting dam is exposed. 5. A step of preparing a lead frame having a plurality of device regions, in which a connecting dam is connected to the upper surface of the outer lead, and a step of preparing a semiconductor chip mounted in the device region of the lead frame, A step of adhering and fixing the semiconductor chip to a device region of the lead frame; a step of connecting a surface electrode of the semiconductor chip and an inner lead of the lead frame corresponding thereto by a connecting member; A step of collectively covering a device region with a mold resin, resin-sealing the semiconductor chips and forming a collective sealing portion, the lead frame and the collective sealing portion along the dicing line for each device region. Is divided into individual pieces, and from the mounting surface to the surface opposite to the mounting surface, Forming individual packages in which the water leads and the connection dam are exposed, and forming the first semiconductor device and a second semiconductor device stacked on the upper stage of the first semiconductor device; And a step of connecting an external electrode formed on the opposite surface of the first semiconductor device on which the above is formed and an external electrode formed on the mounting surface of the second semiconductor device.