JPH04184278A - Ic tester - Google Patents

Abstract

PURPOSE:To exactly measure the timing of an output signal of IC by generating a pulse for timing measurement in which output timing increases and decreases at specified intervals and taking logical multiply with the output signal of the pulse and IC to be measured. CONSTITUTION:In a signal shift circuit 15 a width-narrow pulse signal C is moved by specified time (cut value) dy. A register 16 stores the cut value dy (value for increasing or decreasing the rise time of a signal C at specified intervals). A register 18 stores the initial value of the rise time of the signal C. A computing element 17 adds or subtracts the value dy of the register 16 to or from the initial value of the register 18 and its result is stored 18 again. The value of the register 18 is output into a control means 11 and a test signal generation means 12. The generation means 12 successively generates the signal C corresponding to the value of the register 18 increasing (decreasing) the value dy alone, the control means 11 latches the value of the register 18 at the time when the output level of an AND circuit 14 becomes an H level 1, and the value is made the rise (fall) time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC testing device for testing the electrical characteristics of an IC (integrated circuit), and particularly to an IC testing device for accurately measuring the timing of an IC under test. Regarding IC test equipment that can be used.

[Conventional technology]

In order to ship an IC with guaranteed performance and quality as a final product, 11! ■C1 in each process of manufacturing department and inspection department!
! It is necessary to remove all or part of the product and inspect its electrical characteristics. An IC testing device is a device that tests such electrical characteristics.

The IC test equipment applies predetermined test pattern data to the IC under test, reads the resulting output data of the IC under test, and checks the output of the IC under test to determine whether there are any problems with the basic operation and functions of the IC under test. Analyzing defect information from data and inspecting electrical characteristics.

In particular, when testing an IC under test that includes a logic circuit or the like, the timing of the rise and fall of a signal output from the IC under test relative to an input signal is important. Therefore, conventionally, the timing of whether the IC under test rises within the set-up time (allowable time until the signal rises) stipulated in the test specifications has been measured.

A timing measurement method performed by a conventional IC testing device will be explained using FIG. 5.

The tester' section 1 mainly includes a control means 11 and a test signal generation means 1.
Consists of 2. The IC under test is actually measured in the tester section 1.
2, drivers, comparators, etc. are omitted in this specification, and their waveforms (signals A, B, C) are shown in the signal waveform 13. will be shown and explained.

The IC under test 2 has a built-in logic circuit 21, receives the signal A of the signal waveform 13 generated by the test signal generating means 12, and outputs the signal B.

The tester section 1 and the IC under test 2 are connected by a signal line consisting of a plurality of (m) coaxial cables, etc. corresponding to the total number of input/output terminals of the IC under test C2, and various signals are transmitted. It looks like this.

Although only one IC 2 to be measured is shown in the figure, a plurality of ICs 2 to be measured are actually connected to the tester section 1. For example, one IC2 under test has 28 input/output terminals.
If 0 cables are connected, a total of 280 cables are connected.

The control means 11 controls, operates, and manages the entire IC test equipment 4, and has a microprocessor configuration. Therefore, although not shown, it is configured to include a ROM that stores system programs, a RAM that stores various data, and the like.

The control means 11 performs various kinds of control over the test signal generation means 12 and various data processes according to the AND output from the AND circuit 14.

The test signal generating means 12 outputs predetermined test pattern data to a driver, a comparator, etc.

Signal A of signal waveform 13 is applied to IC2 under test by the driver.
Signal B is a signal created by IC 2 under test based on signal A, and is a signal output from the comparator. The signal C is a very narrow pulse that goes to a high level "'1" at a set-up time Y specified in the test specifications.

Therefore, when measuring the timing of the rise of signal B, the test signal generating means 12 generates the signal C, and the AND circuit 14 detects whether the signal B and the signal C are both at the high level 111 IT. Ta.

Therefore, by outputting the high level 411 IT from the AND circuit 14, it can be determined that the signal B has risen within the setup time.

[Problem to be solved by the invention]

In conventional IC test equipment, signal A of signal waveform 13,
Assuming that the relationship between B and C is as shown in FIG. 6, the determination of timing measurement will be as follows.

That is, in the case of signals B1 and B3, both are at high level "'1" when signal C is at high level "'1".
The AND circuit 14 outputs a high level II I IT. Therefore, in the control means 11, the signals B1 and B3 rise within the set-up time Y, and it is determined that the timing is good. In addition, in the case of signal B2, signal C is at high level “
Since it is a low level (lOIT) when it is 1'', a low level itOz+ is output from the AND circuit 14. Therefore, the signal B2 does not rise within the set-up time Y, and it is determined that the timing is defective.

There is no problem when determining signals such as signals B1 to B3, but a problem occurs when determining signals such as signal B4. it is,
Since the signal B4 is at a low level "0" when the signal C is at a high level 1'1", the AND circuit 14 outputs a low level "0".
" is output, and the signal B4 is determined to be a timing failure. However, the signal B4 is actually at a high level "1" before the signal C becomes a high level 411 #+, so there is a timing failure. Rather, it is a normal signal that rose during the setup time. However, conventional determination methods treat such cases as timing failures.

In addition, if you want to measure the time from the falling point of signal A to the actual rise of signal B, or if you want to measure the delay time of another signal from the rising point of signal B, you can simply It is impossible to judge only whether the power has started up within the set-up time.

The present invention has been made in view of the above points.

An object of the present invention is to provide an IC testing device that can accurately detect the timing of an output signal output based on an input signal of an IC under test.

[Means to solve the problem]

A first IC testing apparatus of the present invention includes a test signal generating means for applying a test signal to an IC under test, and a control means for measuring the timing of a signal output from the IC under test by applying the test signal. In the IC test equipment, a timing measurement pulse whose output timing increases or decreases at predetermined intervals is generated in addition to the test signal, and this timing measurement pulse and the output signal of the IC under test are ANDed. The timing of the output signal of the IC under test is measured based on the change in the logical product.

The IC test equipment of the second embodiment includes a test signal generating means for applying a test signal to the IC under test, and a control means for measuring the timing of a signal output from the IC under test by applying the test signal. In the IC test apparatus having
A measuring signal generating means for generating a measuring signal that maintains a high level or a low level until the rising or falling point of the output signal of the output signal, and a pulse width measuring means for measuring the pulse width of this measuring signal, This is to measure the timing of the output signal of the measurement IC.

[Effect]

In the first aspect of the present invention, the timing measurement pulse is output separately from the test signal, and its output timing increases or decreases at predetermined intervals, so that the timing measurement pulse and the output signal of the IC under test are By continuing to perform the logical product with the logical product, the state of the logical product output changes at a certain point.

Therefore, the timing of the output signal of the IC under test can be measured based on how much the output timing of the timing measurement pulse increases or decreases when the AND output changes. Further, timing detection accuracy can be improved by reducing the interval, which is the rate of increase/decrease in the timing measurement pulse. Note that in order to generate such timing measurement pulses, separate hardware may be provided, or they may be generated using software by a control means.

By applying the test signal, the IC under test outputs output signals at various timings. The detection accuracy of such an output signal is determined by the rate of increase or decrease of the timing measurement pulse. Therefore, even if the output signals actually occur at different timings, they may be processed as signals that occur at the same timing because the increase/decrease ratio is large. Therefore, in the second aspect of the present invention, the measurement signal generating means maintains a high level or low level from the rising or falling time of the test signal to the rising or falling time of the output signal of the IC under test. now occurs. This measurement signal is a high-level or low-level pulsed signal, so simply measuring the pulse width of this measurement signal with a pulse width measurement means will
The actual timing of the output signal can be measured,
The detection accuracy of timing measurement can be greatly improved.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the general structure of an IC testing device according to an embodiment of the present invention. In FIG. 1, the same components as in FIG. 5 are denoted by the same reference numerals, so their explanation will be omitted.

The present embodiment differs from the conventional one in that it is provided with a signal shift circuit 15 that shifts the narrow pulse signal C by a predetermined time (kitch value) dy.

The signal shift circuit 15 includes registers 16 . It is composed of a register 18 and an arithmetic unit 17.

The register 16 stores the increment value dy from the control means 11. This increment value dy is a value for increasing or decreasing the rise time of the signal C at predetermined intervals.
1 can be set arbitrarily.

It is possible to set up to the minimum resolution of the tester itself.

Register 18 stores the initial value of the rise time of signal C. As the initial value, a value smaller than the setup time specified in the test specification may be stored.
Since a case like the signal B4 in the figure is also possible, a value that is almost the same as that at the falling edge of the signal A may be stored. register 1
The initial value is stored in the control means 11 before timing measurement.
carried out by.

The arithmetic unit 17 adds or subtracts the roughness value dy of the register 16 to the initial value of the register 18, and stores the result in the register 18 again. Therefore, the register 18 increases or decreases by an increment of 1fidy every test cycle.

The value of the register 18 is output to the control means 11 and the test signal generation means 12. Therefore, the test signal generating means 12 sequentially generates the signal C corresponding to the value of the register 18 which increases by the increment value dy, and the control means 11 registers the signal C at the time when the output of the AND circuit 14 becomes high level "1". 18 is taken in, and this value is set as the rise time of signal B.

When measuring the fall time of signal B, register 18
Set the initial value of register 18 to a sufficiently large value.
It is sufficient to reduce the value of by the increment value dy, and use the value of the register 18 at the time when the output of the AND circuit 14 becomes a high level "1" as the fall time of the signal B.

The embodiment shown in FIG. 1 can be constructed by simply adding an arithmetic unit 17 and registers 16 and 18 to the current IC test equipment, and the signal B
The detection accuracy of the rise or fall of can be freely changed.

It goes without saying that the same functions as the arithmetic unit 17 and the registers 16 and 18 may be realized by the software of the control means 11.

However, whether the signal C in which the position of the high level "'1'" increases or decreases by the increment value dy is generated by hardware as shown in FIG. 1 or by the software of the control means 11, the increment value By decreasing dy, the detection accuracy improves, but the amount of movement of the rise time of signal C becomes slower, and timing measurement takes a lot of time. Conversely, if the cut value dy is increased, timing measurement is shorter, but the detection accuracy is lower.

Therefore, the time from the falling edge of signal A to the rising edge of signal B was directly detected using an IC testing device. This embodiment will be described below with reference to FIGS. 2, 3, and 4.

FIG. 2 is a diagram showing a schematic configuration of an IC testing device according to another embodiment of the present invention, in which the time from the falling point of signal A to the rising point of signal B is directly detected. . In FIG. 2, the same components as in FIG. 5 are given the same reference numerals, so the explanation of -P: will be omitted.

First, in this embodiment, the signal C1 generated by the test signal generating means 12 is different from the signal C in FIG. 1, and is a signal that shows a high level "1" during one test cycle.

The D/A converters 22 and 23 convert digital data (for example, 1/2 level values of the signals A and H) from the control means 11 for determining the rising and falling points of the signals A and B into analog signals. is supplied to comparators 24 and 25. This digital data causes the comparator 24
and 25 respective thresholds are determined.

The comparator 24 determines the falling point t of the signal A of the test signal generating means 12 based on the threshold value from the D/A converter 22.
Detect a. The comparator 25 detects the rising time tb of the signal B output from the logic circuit 21 of the IC 2 under test based on the threshold value from the D/A converter 23.

In this embodiment, the falling time ta of the signal A and the rising time tb of the signal B are detected. However, in reality, the IC under test
When measuring, the rising edge and falling edge depend on the logic circuit of the IC to be measured, so this embodiment has a configuration in which rising edge/falling edge can be selected so that detection can be performed in either case.

That is, the outputs of the comparators 24 and 25 are outputted directly and via the inverter circuits 26 and 27, so that the selection circuit 28 can arbitrarily select them. In the case of this embodiment, since the falling time ta is detected for the signal A, the selection circuit 28 selects the output of the inverter circuit 26, and the rising time tb is detected for the signal B, so the selection circuit 28 selects the output of the inverter circuit 26. 25 is selected.

The flip-flop 29 connects the comparator 24 (
Alternatively, the output of the inverter circuit 26) is input, and the output of the comparator 25 (or the inverter circuit 27) is input to the R terminal. Therefore, a high level "11n" is output from the Q terminal at the same time as the falling time ta of the signal A, and a high level "II 1 '1" is output from the Q terminal at the same time as the rising time tb of the signal B.
becomes Laure Dairu 110 P+, and flip-flop 2
An output signal with a pulse width Tw is output from the Q terminal of 9.

In the operation of IC test equipment, such tests are performed using test patterns for logic tests, but timing measurements only use part of the test patterns.
Therefore, the part where timing measurement is to be performed (one step among thousands to tens of thousands of steps) is set in the test pattern as signal C1, and timing measurement is performed when AND gate 30 is opened by signal C1. Make it.

Therefore, the output signal of the flip-flop 29 is output from the AND gate 3o to the pulse width measuring means 31 when the signal c1 is at a high level "1".

The configuration of the pulse width measuring means 31 is shown in FIG.

The pulse generator 32 outputs a pulse signal E with an arbitrary pulse interval Tp. The AND gate 33 inputs the pulse signal E and the output signal R, and outputs the AND output of the two to the counter 34. Counter 34 counts the output of AND gate 33. In other words, the counter 34 counts while the output signal is at a high level "'1" (F of the pulse width Tw of the output signal).
17), the pulse signal E passing through the AND gate 33 is counted. Therefore, in the case of FIG. 4, the counter 34 outputs 6 pulses N1 to N6 during the pulse width Tw of the output signal.
Since pulse signals E are counted, the pulse interval Tp
The pulse width Tw is about 6 times longer than the pulse width Tw.

In this case, the pulse interval Tp is proportional to the measurement accuracy, so in order to reduce the measurement error, the pulse interval Tp must be made small. However, there is a limit to how small the pulse interval can be made. Therefore, in this embodiment, an analog circuit is used to measure the time a between the rising edge ta of the output signal and the pulse N1, and the time C between the pulse N6 and the falling edge tb of the output signal. The value obtained by multiplying the total time indicated by the count value of 34 by the pulse interval TP (
a+b+c) Let Tp be the pulse width 'rw. Here, the time value output from the counter 34 is assumed to be a value (n-1) smaller by 1 than the number n of pulse signals E generated during the pulse width Tw of the output signal.

This analog circuit includes a sawtooth wave generation circuit 35, sample and hold circuits (S/H) 36 and 37, and an A/D converter 38.
．． 39 and data converters 40 and 41.

The sawtooth wave generation circuit 35 detects the rising edge of the output signal (STA
RT) generates a sawtooth wave F, and generates a pulse signal E.
(STR8) is reset, and the generation of the sawtooth wave F is repeated. Then, the sawtooth wave generation circuit 35
stops generating the sawtooth wave F in response to the falling edge (STOP) of the output signal. Therefore, pulse N of pulse signal E
A sawtooth wave Fir of the same level is generated between 1 and N6, but a sawtooth wave F of a different level is generated between pulses NO and N1 and between pulses N6 and N7.

The sample hold circuit 36 detects the moment (S) when the high level ri1u (pulse Nl) is output from the AND gate 33
TR8) holds the level Va of the sawtooth wave F. The sample and hold circuit 37 detects the falling point of the output signal (S
TOP) to hold the level VC of the sawtooth wave F. A/
D converters 38 and 39 receive analog signals (levels Va and Vb) held in sample and hold circuits 36 and 37.
Convert to digital signal. Data converters 40 and 41
outputs the digital signals of the A/D converters 38 and 39 to the control means 11 as time data a and C.

The control means 11 calculates the output signal by multiplying the total value (a + b + c)' of the time data b from the counter and the time data a and C from the data converters 40 and 41 by the pulse interval Tp. The pulse width TW can be determined.

As described above, according to the present embodiment shown in FIG. 2, it is only necessary to perform timing measurement once at any given time, and the measurement time can be significantly shortened.

In addition, in the above-mentioned embodiment, a case was explained in which the time from the falling time ta of signal A to the rising time tb of signal B was measured, but the time from the rising or falling time of signal A to the rising or falling time of signal B It goes without saying that any time period up to that point may be measured.

〔Effect of the invention〕

According to the present invention, it is possible to accurately detect the timing of an output signal output based on an input signal of an IC under test.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an IC testing device that is an embodiment of the present invention, and FIG. 2 is a block diagram showing a schematic configuration of an IC testing device that is another embodiment of the present invention. 3 is a diagram showing the detailed configuration of the pulse width measuring means in FIG. 2, FIG. 4 is a timing chart diagram for explaining the operation of FIG. 2, and FIG. 5 is a diagram showing the schematic configuration of a conventional IC testing device. Figure shown. FIG. 6 is a timing chart showing the state of timing measurement in conventional IC test mounting. 1... Tester part, 2... IC installation difficulty, 11...
Control means, 12... Test signal generation means, 14... AND circuit, 15... Signal shift circuit, 16.18...
Register, 17... Arithmetic unit, 21... Logic circuit, 2
2.23...D/A converter, 24.25...Comparator, 26.27...Inverter, 28...Selection circuit, 29...Flip-flop, 30.33...
AND gate, 31...Pulse width measuring means, 32...
・Pulse generator.

Claims (5)

[Claims] (1) In an IC testing apparatus, the IC test apparatus includes a test signal generating means for applying a test signal to an IC under test, and a control means for measuring the timing of a signal output from the IC under test by application of the test signal, wherein the test signal is Separately, a timing measurement pulse whose output timing increases or decreases at predetermined intervals is generated, and the timing measurement pulse and the output signal of the IC under test are ANDed, and based on the change in the AND output, An IC testing device that measures the timing of an output signal of the IC under test. (2) The control means causes the test signal generation means to generate the timing measurement signal, and instructs to increase or decrease the output timing and detects changes in the AND output using software. 1. The IC test device according to 1. (3) A first register that stores a timing value indicating the output timing of the timing measurement pulse, a second register that stores a kinematic value that indicates the rate of increase/decrease, and a register that stores the kinematic value in the timing value. Add or subtract,
a timing shift circuit comprising an arithmetic unit that stores the value again in the first register; The IC testing device according to claim 1, wherein the IC testing device generates a pulse for timing measurement. (4) In an IC test apparatus, the IC test apparatus includes a test signal generating means for applying a test signal to an IC under test, and a control means for measuring the timing of a signal output from the IC under test by application of the test signal, wherein the test signal is The measurement target I from the rising or falling point of
A measuring signal generating means for generating a measuring signal that maintains a high level or a low level by the rising or falling point of the output signal of C, and a pulse width measuring means for measuring the pulse width of this measuring signal. An IC testing device characterized by measuring the timing of an output signal of an IC under test. (5) The measurement signal generating means includes a first comparator that detects the rising or falling point of the test signal, and a second comparator that detects the rising or falling point of the output signal of the IC under test. , a signal selection circuit that directly or inverts the outputs of the first and second comparators, the output of the first comparator selected by the signal selection circuit is connected to the S terminal, and the output of the second comparator is connected to the S terminal. A flip-flop inputs the measurement signal to the R terminal and outputs the measurement signal from the Q terminal, and the pulse width measurement means includes pulse generation means for generating pulse signals at predetermined intervals; a counter that counts how many of the pulse signals are generated during the period, a time from the rising or falling point of the measurement signal until the first pulse signal is generated within the pulse width, and the pulse width. and a time measuring means for detecting the time from the generation of the last pulse signal to the rising or falling point of the measurement signal in an analog manner using a sawtooth wave; 5. The IC testing apparatus according to claim 4, wherein the timing of the output signal of the IC under test is measured based on the value of the counter and the value of the time measuring means.