JPH041837A - Memory access circuit - Google Patents

Abstract

PURPOSE:To attain the switch of memory accesses with use of a common bus selection circuit despite the use of plural memory boards and to reduce the hardware scale by connecting a bus selection circuit to a memory board via a common bus. CONSTITUTION:A bus selection circuit 74 is provided at a position except a memory board 72 and connected to the memory board 72 via a common bus 75. Then the circuit 74 performs the switch between a processor of a processor board 71 and an external device 73 when an access is given to the board 72. Thus the circuit 74 can deal with the increase of the number of boards 72. Then it is possible to prevent the increase of the hardware circuits related to the circuit 74 that is caused by the increase of the boards 72.

Description

[Detailed Description of the Invention] [Summary] Regarding memory access circuits in data processing devices such as emulators, the present invention reduces hardware by making it possible to switch memory access using a common bus selection circuit even when multiple memory boards are used. The aim is to make it possible for users to create and use their own memory boards without having to worry about the bus selection circuit. In a data processing device equipped with an external device mounted with Configured to connect to the board via a shared bus.

[Industrial Application Field] The present invention relates to a memory access circuit in a data processing device such as an emulator.

[Prior Art] FIG. 5 shows the external configuration of an emulator, which is a program development support device, as a data processing device. In FIG. 5, 51 is the emulator main body, 52 is a host personal computer for controlling the emulator main body, and the emulator main body 51 and the personal computer 52 are connected by a flat cable 53. A personal computer bus is guided to the emulator main body 51.

The emulator main body 51 includes several printed boards 512 housed within a shelf 511. These printed boards 5
12 includes a DSP board equipped with a DSP (digital signal processing processor) and DSP peripheral circuits, and multiple external memory boards equipped with external memory and memory peripheral circuits.The connection between this DSP board and the external memory board is This is performed by a host computer bus and a DSP bus connected to the backboard of the shelf 511.

FIG. 6 shows a conventional connection configuration between this DSP board and an external memory board. In FIG. 6, 3 is a host personal computer bus connected to a host personal computer 52, and 4 is a DSP board 5 for memory access.
5 is a DSP board, and 6■ to 6■ are three external memory boards. DSP board 5 and external memory board 6
■～6■ are both host computer bus and DSP board 5
is connected to □External memory board 6■
~6■ is also a DS from the host personal computer 52
Memory access is also possible from the P board 5.

An example of the configuration of the external memory boards 61-62 is shown in FIG. In FIG. 7, 61 is a random access memory, 62 and 63 are selectors, 64 is an inverter, and 65 and 66 are bidirectional buffer circuits.

41 is an address bus in the DSP bus 4, on which a DSP address signal DA is loaded. 42 is a data bus in the DSP bus 4, on which the DSP data number DD is loaded. 43 is a DSP write enable signal line in the DSP bus 4, on which a DSP write enable signal (DSP read/write signal) DWE is carried. 31 is an address bus in the personal computer bus 3, on which a personal computer address signal PA is loaded. 32 is a data bus in the personal computer bus 3, on which a personal computer data signal PD is loaded.

33 is a personal computer write enable signal line in the personal computer bus 3, on which a personal computer write enable signal (personal computer read/write signal) PWE is carried.

The selection signal SEL is connected to the DSP bus 4 and the host computer bus 3.
This is a signal that selects the memory 61 from the DSP board 5 when it is "0", and enables access from the host personal computer 52 to the memory 61 when it is "1".DSP write enable Signal DWE and PC write enable signal PWE are “
The memory 61 can be switched to the write mode when the value is O'', and to the read mode when the value is ``1''.

A DSP address signal DA and a personal computer address signal PA are manually input to the selector 62, and the selector 62 selects one of the address signals DA and PA in response to a selection signal SEL from the backboard and selects one of the address signals DA and PA to select the one from the memory 61. Enter the address in .

The selector 63 also has a DSP write enable signal DW.
E and a personal computer write enable signal PWE are input, and the selector 63 receives this write enable signal DW.
One of E and PWH is selected according to the selection signal SEL and inputted to the write enable terminal WE of the memory 61.

The bidirectional buffer circuit 65 is a bidirectional buffer for the DSP data signal DD, and when the selection signal SEL is °0'' and D
When SP write enable signal DWE is “0″’, DS
The DSP data number DD on the P data bus 42 is transferred to the memory 6.
1, the selection signal SEL is °O'' and the DSP
The data read from the memory 61 when the write enable signal DWE is '1''' is placed on the DSP data bus 42 as the DSP data number DD.

Similarly, the bidirectional buffer circuit 66 receives the personal computer data signal P.
It is a bidirectional buffer for D, and the selection signal SEL is °゛1
``'' and the personal computer write enable signal PWE is °'0'', the personal computer data signal PD on the personal computer data bus 32 is written to the memory 61, and the 1 selection signal SEL is 1'' and the personal computer write enable signal PWE is °'1. The data read from the memory 61 at the time of ``'' is placed on the personal computer data bus 32 as the personal computer data signal PD.

To explain the operation of this external memory board, when emulating and accessing external memory overnight, the DSP board 5 uses the DSP bus 4 to connect external memory boards 6 to 6.
On the other hand, the host personal computer 52 uses the host personal computer bus 3 to access external memory boards 6--6.

When accessing the memory 61 from the DSP board 5, the selection signal SEL is set to O'' to enable the bidirectional buffer circuit 65. This allows the memory 61 and D
The SP boards 5 are connected via the DSP bus 4, allowing access between them. Then, when writing to the memory 61, the DSP write enable signal DWE is set to "O"', and when reading is performed, it is set to "1"'.

Next, from the host personal computer 52 to the memory 6
When accessing 1, set the selection signal SEL to "1"'
to enable the bidirectional buffer circuit 66. As a result, the memory 61 and the host personal computer 5
2 are connected via a host personal computer bus 3, allowing access between the two. When writing to the memory 61, the personal computer write enable signal PWE is set to "0", and when reading from it, it is set to "1".

[Problems to be Solved by the Invention] In the conventional device described above, switching between the DSP board 5 and the host personal computer 52 to access the memory mounted on the external memory board is performed by the external memory boards 6 - Selector 62.6 placed within 6■
This is done by a bus selection circuit composed of 3 and bidirectional buffer circuits 65 and 66.

As a result, even when two or more external memory boards are used, it is necessary to prepare a bus selection circuit for each external memory board, resulting in an increase in the number of components.

Furthermore, if an emulator user attempts to use a memory board other than the external memory board provided by the manufacturer, if the bus selection circuit described above is not built into this memory board, the host personal computer and DSP board will memory access cannot be switched, and the device cannot operate normally. As a result, when a user makes his own memory board, it is necessary to consider the bus selection circuit, which increases the burden of design on the user.

The present invention has been made in view of such technical problems, and its purpose is to enable switching of memory access using a common bus selection circuit even when a plurality of memory boards are used. The purpose of this invention is to reduce the scale, and to reduce the burden on the user by eliminating the need to be aware of the bus selection circuit when the user makes and uses a memory board by himself/herself.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

A memory access circuit according to the present invention is used in a data processing device including a processor board 71 on which a processor is mounted, a memory board 72 on which a memory is mounted, and an external device 73 on which a processor is mounted.
A bus selection circuit 74 for selecting either a signal from the processor of the memory board 73 or a signal from the external device 73 is provided at a location other than the memory board 72.
2 via a shared bus 75.

Further, the memory access circuit according to the present invention includes a first selector 741 in which the above-described bus selection circuit 74 selects an address signal from the processor of the processor board 71 and an address signal from the external device 73 according to a selection signal; A second selector 742 that selects a write enable signal from the processor of the processor board 71 and a write enable signal from the external device 73 according to a selection signal, and a connection between the data terminal of the processor of the processor board 71 and the external memory board 72 between the data bus from the external device 73 and the memory board 72. A second bidirectional buffer circuit 7 that controls the connection of the buffer circuit according to a selection signal and also controls the direction of signal transmission during writing/reading using a write enable signal from an external device 73.
It consists of 44.

Further, in the memory access circuit according to the present invention, the above-described bus selection circuit 74 is provided on the processor board 71.

[Operation] Switching between accessing the memory board 72 from either the processor of the processor board 71 or the external device 73 is performed by the bus selection circuit 74 provided at a location other than the memory board.

Therefore, even if the number of memory boards 72 increases, the aforementioned bus selection circuit 74 can commonly handle the increase, and it is possible to prevent an increase in the number of hardware circuits related to the bus selection circuit due to the addition of memory boards.

The bus selection circuit can be configured by first and second selectors 741 and 742 and first and second bidirectional buffer circuits 743 and 744, and when accessing the memory board 72 from the processor of the processor board 71 , the first and second selectors 741 and 74 are selected by the selection signal.
2 and the first bidirectional buffer circuit 743 select the processor side of the processor board 71 and connect it to the memory board 72 via the shared bus 75. When accessing the memory board 72 from the external device 73, the first and second selectors 741 and 742 and the second bidirectional buffer circuit 744 select the bus from the external device 73 according to the selection signal. , are connected to the memory board 72 via a common bus 75.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings. This embodiment is a case where the present invention is applied to an emulator, and the external structure of this emulator is the same as that shown in FIG. 5 described in the above-mentioned prior art.

FIG. 2 shows a schematic configuration of the memory access circuit of the embodiment. In Figure 2, ■ is a DSP equipped with a DSP.
Boards 2 - 2 - are external memory boards loaded with memory, 3 is a personal computer bus from the host personal computer 52 , and 4 is a DSP bus that is a common bus between the DSP board 1 and the host personal computer 52 . Here, the DSP board 1 is connected to both the host personal computer bus 3 and the DSP bus 4. On the other hand, external memory board 2■~
2) is connected only to the DSP bus 4 and not to the personal computer bus 3, unlike the conventional one.

A more detailed configuration example of the DSP board 1 of this embodiment is shown in the third section.
As shown in the figure. In FIG. 3, 11 is a DSP circuit;
2 and 13 are selectors, 14 and 15 are bidirectional buffer circuits, and 16 is an inverter. 31 is an address bus in the PC bus 3 from the backboard, 32 is a data bus in the PC bus 3, and 33 is a PC write enable signal line in the PC bus 3, and each has a PC address signal PA and a PC data signal. PD and personal computer write enable signal PWE are loaded.

Selector 12 has personal computer address signals PA and DS.
The DSP address signal DA from the P circuit 11 is input, and the selector 12 receives the selection signal SE from the backboard.
One of them is selected according to L and output to the address bus 41 in the DSP bus 4.

Further, the selector 13 receives the DSP write enable signal DWE from the DSP circuit 11 and the PC write enable signal PWE from the host personal computer 52, and selects one of them according to the selection signal SEL. D in DSP bus 4
It is output to the SP write enable signal line 43.

The bidirectional buffer circuits 14 and 15 are configured so that when one is enabled, the other is disabled by the selection signal SEL. The bidirectional buffer circuit 14 is a DSP
It is placed between the terminal for DSP data D from the circuit 11 and the data bus 42 in the DSP bus 4, and receives the selection signal S.
Enable/disable is controlled by EL,
Further, the direction of signal transmission is controlled by a DSP write enable signal DWE from the DSP circuit 11.

Similarly, the bidirectional buffer circuit 15 includes a data bus 32 in the host personal computer bus 3 and a data bus 4 in the DSP bus 4.
2, enabling/disabling is controlled by the selection signal SEL via the inverter 16, and the direction of signal transmission is controlled by the personal computer write enable signal PWE from the host personal computer 52. It has become.

The DSPS-board 1 medium collector 12.13 and the bidirectional buffer circuit 14.15 constitute a bus selection circuit.

FIG. 4 shows a detailed example of the configuration of the external memory boards 2--2 of the embodiment. In FIG. 4, 21 is a random access memory, and 22 is a bidirectional buffer circuit. The address terminal ADR3 of the memory 21 is connected to the address bus 41 in the DSP bus 4 from the backboard, and the data terminal DATA is connected to the DSP bus 41 through the bidirectional buffer circuit 22.
It is connected to a data bus 42 in the bus 4, and the write enable terminal WE is connected to a DSP write enable signal line 43 in the DSP bus 4. Bidirectional buffer circuit 22
The signal transmission direction is switched by a DSP write enable signal DWE from a DSP write enable signal line 43.

The operation of the embodiment device will be explained below.

First, a case will be described in which the DSP circuit 11 of the DSP board 1 accesses the memory 21 of the external memory boards 2--2. In this case, the selection signal SEL is set to O''' by the host personal computer 52.
Make it.

As a result, on the DSP board l, the selector 12 selects the DSP address signal DA from the DSP circuit 11 and outputs it to the DSP address bus 41 of the backboard, and the selector 13 selects the DSP write enable signal DWE from the DSP circuit 11. It is selected and output to the DSP write enable signal line 43 of the backboard. Also, the bidirectional buffer circuit 14 is enabled, the bidirectional buffer circuit 15 is disabled, and the DSP data DD terminal terminal of the DSP circuit 11 is connected to the DSP data bus 42 of the board. It is separated from 42.

When performing write access from the DSP circuit 11 to the external memory boards 2■ to 2■, the DSP circuit 11
Set the SP write enable signal DWE to "0"'. As a result, the bidirectional buffer circuit 14 is switched to transmit the DSP data D from the DSP circuit 11 to the DSP data bus 42 side.

On the other hand, on the external memory board 2■~2■ side, the DS
The bidirectional buffer circuit 22 is switched to transmit a signal toward the memory 21 by the P write enable signal DWE, and the memory 21 is switched to the write mode.

As a result, the DSP data D output from the DSP circuit 11 of the DSP board 1 is written into the memories 21 of the external memory boards 2--2.

When reading and accessing the external memory boards 2 - 2 from the DSP circuit 11, the DSP write enable signal DWE of the DSP circuit 11 is set to '1'.This causes the bidirectional buffer circuit 14 to move in the direction of the DSP circuit 11. while the external memory board 2
On the (1) to (2) side, the bidirectional buffer circuit 22 is switched to transmit signals in the direction of the DSP data bus 42, and the memory 21 is switched to the read mode.

Therefore, data read from the memory 21 is transmitted to the DSP circuit 1 via the bidirectional buffer circuit 22, the backboard DSP data bus 42, and the bidirectional buffer circuit 14.
1 is man-powered.

Next, when memory access is to be made from the host personal computer 52 to the external memory boards 2-2-2, the selection signal SEL is set to "1"'. This allows selector 1
2 selects the personal computer address signal PA and outputs it to the DSP data bus 41, the selector 13 selects the personal computer write enable signal PWE and outputs it to the DSP write enable signal line 43, and the bidirectional buffer circuit 15 is enabled. The personal computer data bus 32 and the external memory boards 2-2 are connected via the DSP data bus 42 of the backboard.

Switching between the write mode and the read mode is performed by the personal computer write enable signal PWE, but since the operation is the same as that of the DSP circuit 11 described above, detailed explanation will be omitted.

Various modifications are possible in implementing the invention. For example, in the above embodiment, the present invention is applied to an emulator, but the present invention is not limited to this. It is possible to apply.

Further, in the above embodiment, the case where the bus selection circuit is provided on the DSP board has been described, but the present invention is not limited to this. (For example, the bus selection circuit may be provided on the backboard, or A board may also be provided.

However, from the viewpoint of reducing the number of buses dedicated to the DSP, it is preferable to provide it on the DSP board.

[Effects of the Invention] As explained above, according to the present invention, even when a plurality of memory boards are used, memory access can be switched using a common bus selection circuit. There is no need to provide a selection circuit, so the hardware scale of the device can be reduced. Furthermore, it becomes possible for the user to create and use a memory board by himself without being aware of the bus selection circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a block diagram showing a memory access circuit as an embodiment of the present invention. FIG. 3 is a diagram showing a configuration example of a DSP board in the memory access circuit of the embodiment. 4 is a block diagram showing an example of the configuration of an external memory board in the memory access circuit of the embodiment, FIG. 5 is a diagram showing the external configuration of an emulator as a data processing device, and FIG. 6 is a conventional memory access circuit. A block diagram showing the circuit,
FIG. 7 is a diagram showing an example of the configuration of a conventional external memory board. In the figure, ■, 5...DSP board 2■~2■, 6■~6■...External memory board 3...PC bus 4...DSP bus 11...DSP circuit 12.13.62 .63...Selector 14.15.6
5.66... Bidirectional buffer circuit 16.64... Inverter 21.61... Random access memory 31... Personal computer address bus 32 ・ 33 ・ 4 l ・ 42 ・ 43 ・ 5 l ・ 52 ・ 53・ ・PC data bus・PC write enable signal line・DSP address bus・DSP data bus・DSP write enable signal line・Emulator body・Host personal computer・Flat cable: PC path Part 1 of the present invention 1 circuit 1 2 Figure Emi 1L - “Nu no Fut!i!/iχ Figure 5 3゛Computer Pass Conventional 1st Figure 6 Route

Claims (1)

[Claims] 1. A data processing device comprising a processor board (71) on which a processor is mounted, a memory board (72) on which a memory is mounted, and an external device (73) on which a processor is mounted, comprising: A bus selection circuit (74) for selecting either a signal from the processor of the board (71) or a signal from the external device (73) is provided at a location other than the memory board, and the bus selection circuit (74) selects one of the signal from the processor of the board (71) and the signal from the external device (73). A memory access circuit configured to be connected to a memory board (72) via a shared bus (75). 2. The bus selection circuit (74) includes a first selector (741) that selects an address signal from the processor of the processor board (71) and an address signal from the external device (73) according to a selection signal. , a second selector (742) that selects a write enable signal from the processor of the processor board (71) and a write enable signal from the external device (73) according to the selection signal; and the processor board (71). a first bidirectional buffer that controls the connection between the data terminal of the processor and the memory board (72) according to the selection signal, and controls the direction of signal transmission during writing/reading using the write enable signal of the processor; The connection between the circuit (743), the data bus from the external device (73), and the memory board (72) is controlled according to the selection signal, and the write enable signal of the external device is used to control the connection during writing/reading. 3. The memory access circuit according to claim 2, further comprising a second bidirectional buffer circuit (744) for controlling the direction of signal transmission. 3. The bus selection circuit (74) is connected to the processor board (74).
3. The memory access circuit according to claim 1, wherein the memory access circuit is provided in 1).