JP3700065B2 - Interface cables in computer systems - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides a computer system, particularly a small personal computer system, in which when a plurality of peripheral devices are commonly connected to a single input / output port, the selection of the peripheral devices can be easily switched. It relates to an interface cable in the system.
[0002]
[Prior art]
In a small computer system including a personal computer, there are cases where a plurality of peripheral devices are connected to a single input / output port and a specific one is selected and used. As such an interface, for example, an IDE interface is used. It has been known.
[0003]
This device uses a 40-pin connector and can connect two peripheral devices to a single input / output port. Each peripheral device is set in a master-slave relationship with each other. That is, each peripheral device has a built-in setting switch. By setting one as a master and the other as a slave, each peripheral device can be individually accessed from the computer body side. If only one peripheral device is connected, it must be set as the master. When the power is turned on, each peripheral device performs a self-diagnosis in response to the reset signal. At this time, the master confirms the existence of the slave and transmits the result to the computer main body via the master. Because it is.
[0004]
[Problems to be solved by the invention]
In such a conventional technique, the peripheral device that starts from the computer main body side when the power is turned on is fixed on the master side. Therefore, if this is changed to the slave side, it is necessary to reset the setting switch in the peripheral device. There is an unavoidable problem that the setting operation is extremely troublesome. At this time, if both peripheral devices are mistakenly set as a master or a slave, an input / output data collision occurs, which may cause a fatal data destruction accident.
[0005]
Therefore, in view of the problems of the prior art, an object of the present invention is to set all peripheral devices uniformly as a master by interposing a simple control circuit between the connectors of the interface cable. Another object of the present invention is to provide an interface cable in a computer system that does not require a troublesome setting operation and also has no risk of data destruction due to an incorrect setting.
[0006]
[Means for Solving the Problems]
In order to achieve this object, the configuration of the present invention includes a main body side connector connected to the computer main body, a device side connector connected to each of a plurality of peripheral devices, a main body side connector, and a device side connector The control circuit is mounted on a board that can be inserted into a slot for loading a peripheral device of a personal computer together with a connector on the main body side, detects and stores a selection command from the computer main body, and selects the control circuit. The gist is to transmit a chip select signal from the computer main body to the peripheral device selected by the instruction, and to transmit an interrupt request signal from the selected peripheral device to the computer main body.
[0007]
The control circuit includes a selection signal generation circuit, and the selection signal generation circuit controls the selection circuit that selects the transmission destination of the chip select signal and the input destination of the interrupt request signal according to the contents of the stored selection instruction. The selection signal generation circuit can be provided with a manual selection switch for correcting the content of the selection command.
[0008]
The control circuit also includes a data bus control circuit, and the data bus control circuit can control the contents of specific bits of the data bus in accordance with the contents of the stored selection instruction.
[0009]
[Action]
In such a configuration, the control circuit detects and stores a selection command from the computer body, transmits a chip select signal to the selected peripheral device, and receives an interrupt request signal from the selected peripheral device. By transmitting, an arbitrary peripheral device can be substantially connected to the computer main body and can be selected to be controllable from the computer main body side. That is, each peripheral device can be operated by selecting an arbitrary one from the computer main body side even if the built-in setting switch is uniformly set on the master side.
[0010]
When the control circuit includes a selection signal generation circuit, the selection signal generation circuit selects a predetermined peripheral device by selecting the transmission destination of the chip select signal and the input destination of the interrupt request signal via the selection circuit. Can be activated.
[0011]
If a manual selection switch is attached to the selection signal generation circuit, the operation content of the selection signal generation circuit can be switched by operating the selection switch. It is possible to modify and arbitrarily change the peripheral device actually selected by the selection command.
[0012]
When the data bus control circuit is provided in the control circuit, the data bus control circuit can control the contents of the specific bit of the data bus. Therefore, for example, the specific bit of the data bus is transmitted to the peripheral device like the IDE interface. Even when sharing the selection operation, it can be handled without any problem.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
The interface cable in the computer system includes a control circuit 20 interposed between a connector 11 on the main body side and connectors 12 and 12 on the equipment side (FIG. 1).
[0015]
The connector 11 on the main body side corresponds to a single input / output port Ca in the computer main body C. The device-side connectors 12 and 12 respectively correspond to one of the two peripheral devices D1 and D2 that are commonly connected to the input / output port Ca. However, the peripheral devices D1 and D2 may be arbitrary information input / output devices including, for example, a hard disk device, a CDROM device, and the like.
[0016]
The selection command signal S1 from the computer main body C is input to the detection circuit 21 of the control circuit 20 through the connector 11 on the main body side. The output of the detection circuit 21 is connected to the storage circuit 22, and the output of the storage circuit 22 is connected to the selection signal creation circuit 23. The selection signal creation circuit 23 is provided with a selection switch SW. The selection signal S2 from the selection signal generation circuit 23 is input to the selection circuit 24.
[0017]
A chip select signal S3 from the computer main body C is input to the selection circuit 24 via the connector 11 on the main body side. The outputs of the selection circuit 24 are individually input to the peripheral devices D1 and D2 through the connectors 12 and 12 on the device side as chip select signals S31 and S32.
[0018]
On the other hand, interrupt request signals S41 and S42 from the peripheral devices D1 and D2 are input to the selection circuit 24 via the connectors 12 and 12 on the device side. The output of the selection circuit 24 is input to the computer main body C via the main body side connector 11 as the interrupt request signal S4. Note that other common control signals, data signals, etc. (hereinafter simply referred to as control signals) S5 are bidirectionally transmitted between the computer main body C and the peripheral devices D1 and D2 via the connectors 11, 12, and 12. It is supposed to be transmitted.
[0019]
Now, when the selection command signal S1 is output from the computer main body C to select one of the peripheral devices D1 and D2, the detection circuit 21 of the control circuit 20 detects the selection command included in the selection command signal S1. The storage circuit 22 can store the contents of the detected selection command. In other words, the storage circuit 22 can store different peripheral devices Di (i = 1, 2) selected by the selection command.
[0020]
Therefore, the selection signal creation circuit 23 creates the selection signal S2 in accordance with the contents of the selection command stored in the storage circuit 22. However, the selection signal generation circuit 23 at this time generates a selection signal S2 that directly designates the peripheral device Di stored in the storage circuit 22 when the selection switch SW is turned on. When SW is not turned on, a selection signal S2 for designating a peripheral device Dj (j = 2, 1) opposite to the peripheral device Di stored in the storage circuit 22 is generated. That is, the selection signal generation circuit 23 can make necessary corrections to the contents of the selection command from the computer main body C in accordance with the input state of the selection switch SW. Note that the selection switch SW is manually operated appropriately by an operator.
[0021]
The selection circuit 24 uses the chip select signal S3 from the computer main body C as the chip select signal S3i (or S3j) for the selected peripheral device Di (or Dj) according to the selection signal S2 from the selection signal generation circuit 23. The interrupt request signal S4i (or S4j) from the selected peripheral device Di (or Dj) is transmitted to the computer main body C as the interrupt request signal S4. That is, the selection circuit 24 can select the transmission destination of the chip select signal S3 and the input destination of the interrupt request signals S41 and S42 according to the selection signal S2.
[0022]
For example, when the selection signal S2 designates the peripheral device D1, the selection circuit 24 transmits the chip select signal S3 from the computer main body C to the peripheral device D1 as the chip select signal S31, and the interrupt request signal from the peripheral device D1. S41 is transmitted to the computer main body C as an interrupt request signal S4. When the selection signal S2 designates the peripheral device D2, the selection circuit 24 transmits the chip select signal S3 from the computer main body C to the peripheral device D2 as the chip select signal S32, and the interrupt request signal from the peripheral device D2. S42 is transmitted to the computer main body C as an interrupt request signal S4.
[0023]
That is, when the computer main body C selects one of the peripheral devices D1 and D2 by outputting the selection command signal S1, the storage circuit 22 stores the peripheral device Di selected by the selection command signal S1, and selects the selection signal generation circuit. 23 can substantially connect the selected peripheral device Di or the opposite peripheral device Dj to the computer main body C via the selection circuit 24 in accordance with the input state of the selection switch SW. Therefore, thereafter, the computer main body C can freely access a predetermined peripheral device Di (or Dj). The control signal S5 is bi-directionally transmitted between both the peripheral devices D1 and D2 and the computer main body C, and if necessary, the peripheral device Di (on the side actually selected by the selection circuit 24). Alternatively, it can be used by the computer main body C or as information from the peripheral device Di (or Dj).
[0024]
Note that the selection switch SW is not always necessary. By omitting the selection switch SW, the selection signal generation circuit 23 always allows the peripheral device Di stored in the storage circuit 22 to be actually accessible as it is. Can do.
[0025]
A specific example when the present invention is applied to an IDE interface is shown in FIG.
[0026]
In the figure, the detection circuit 21 of the control circuit 20 is configured by cascading two AND gates. Address signals DA0, DA1, DA2 and chip select signals CS0, CS1 are input to the preceding AND gate, and a write strobe signal DIOW is input to the subsequent AND gate. The small white circles at each gate indicate that the signal level has a low level. Therefore, the detection circuit 21 can output the device head register access signal DHRW and the device head register write signal DHW for the peripheral devices D1 and D2 as outputs of the AND gates. This is because, in the IDE interface, the combination of the address signals DA0, DA1, DA2, and the chip select signals CS0, CS1 being low, high, high, low, high indicates an access to the device head register.
[0027]
That is, the detection circuit 21 in FIG. 2 can detect a selection command from the computer main body C and output the device head register write signal DHW.
[0028]
The storage circuit 22 includes a flip-flop that inputs the device head register write signal DHW from the detection circuit 21 to the clock terminal CK. The data terminal 4 of the data bus is connected to the data terminal D of the flip-flop, and the reset signal RESET is input to the clear terminal CLR. Therefore, the storage circuit 22 can store the 4-bit DD4 of the data bus at the rising edge of the device head register write signal DHW and output it as the device selection signal DSEL to the output terminal Q of the flip-flop.
[0029]
The device selection signal DSEL is at a low level when the peripheral device D1 is selected, and is set at a high level when the peripheral device D2 is selected. This is because, in the IDE interface, the 4-bit DD4 of the data bus corresponding to the write operation of the device head register means master selection at the low level and slave selection at the high level. However, it is assumed that the device selection signal DSEL is initialized to a low level by the reset signal RESET at the same time as the power is turned on.
[0030]
That is, when the selection circuit 21 detects a selection command from the computer main body C by the detection circuit 21, the storage circuit 22 can store the content and output it as a device selection signal DSEL.
[0031]
The selection signal generation circuit 23 includes two sets of exclusive OR gates that input the device selection signal DSEL and the ON state signal SWS of the selection switch SW via a pull-up resistor. As an output of the OR gate, a first selection signal DR1 for instructing selection of the peripheral device D1 and a second selection signal DR2 for instructing selection of the peripheral device D2 can be generated. However, the first selection signal DR1 is selected when the selection switch SW is turned on and the device selection signal DSEL selects the peripheral device D1, or when the selection switch SW is not turned on and the device selection signal DSEL is set to the peripheral device. This is effective when D2 is selected. The second selection signal DR2 is selected when the selection switch SW is turned on and the device selection signal DSEL selects the peripheral device D2, or when the selection switch SW is not turned on and the device selection signal DSEL is turned on. This is effective when D1 is selected.
[0032]
That is, the selection signal generation circuit 23 can output the first selection signal DR1 and the second selection signal DR2 in accordance with the device selection signal DSEL from the storage circuit 22.
[0033]
Which of the first selection signal DR1 and the second selection signal DR2 is valid through the four sets of AND gates, each of which receives the first selection signal DR1 and the second selection signal DR2, respectively, in the selection circuit 24 Thus, the transmission destination of the chip select signals CS0 and CS1 can be selected as one of the peripheral devices D1 and D2. In addition, the selection circuit 24 combines the two AND gates and the OR gates to determine the input destination of the interrupt request signal INTRQ depending on which of the first selection signal DR1 and the second selection signal DR2 is valid. One of the devices D1 and D2 can be selected. A pull-down resistor is inserted in the signal line of the interrupt request signal INTRQ from each of the peripheral devices D1 and D2 in order to prevent the signal level when not in use from becoming unstable.
[0034]
In the control circuit 20 of FIG. 2, a data bus control circuit 25 is added to the signal line of the 4-bit DD4 of the data bus.
[0035]
The data bus control circuit 25 includes two amplifiers in the opposite direction, one transmitting signals from the computer main body C side to the peripheral devices D1 and D2, and the other transmitting from the peripheral devices D1 and D2 side. To the computer main body C side. The operation of the former amplifier is controlled through an AND gate that inputs the write strobe signal DIOW and the device head register write signal DHW from the detection circuit 21, and writing to peripheral devices D1 and D2 other than the device head register is performed. It is designed to operate in response to a load instruction. A pull-down resistor is inserted at the output terminal of the former amplifier to prevent the signal level when it is not in operation from becoming unstable. On the other hand, the operation of the latter amplifier is controlled by the read strobe signal DIOR, and operates in response to all read commands.
[0036]
However, although the input side of the former amplifier is directly connected to the computer main body C, the input side of the latter amplifier is connected to two sets that are opened / closed by a device head register access signal DHRW from the detection circuit 21 via an OR gate. The AND gates are juxtaposed, and the 4-bit DD4 of the data bus from the peripheral devices D1 and D2 is input to one AND gate, and the device selection signal DSEL from the storage circuit 22 is input to the other AND gate. Have been entered.
[0037]
That is, the data bus control circuit 25 operates the former amplifier in response to a write command to the peripheral devices D1 and D2 other than the device head register, thereby transferring the 4-bit DD4 of the data bus from the computer main body C side to the peripheral device. It can be transmitted to the D1 and D2 sides. The data bus control circuit 25 activates the latter amplifier in response to the read command. When the read command designates the device head register, the device selection signal DSEL from the storage circuit 22 is sent to the computer main body C side. When the read command does not specify the device head register, the 4-bit DD4 of the data bus from the peripheral devices D1 and D2 can be transmitted to the computer main body C as it is.
[0038]
In this way, the data bus control circuit 25 is added to the signal line of the 4-bit DD4 of the data bus in this way because the IDE interface uses the 4-bit DD4 of the data bus as a general data bus, This is because they are also used in common to select one of the peripheral devices D1 and D2 set as one of the slaves. Therefore, in the case of an interface in which a specific bit of the data bus is not used for such a special purpose, it is not necessary to provide the data bus control circuit 25.
[0039]
Comparing FIG. 1 and FIG. 2, the components with the same reference numerals correspond to each other, and the latter address signals DA0, DA1, DA2, chip select signals CS0, CS1, and write strobe signal DIOW are collectively shown in the former. This corresponds to the selection command signal S1. The latter first selection signal DR1 and second selection signal DR2 correspond to the former selection signal S2 at once. Further, the chip select signals CS0 and CS1 from the computer main body C in the latter are transmitted as the chip select signals CS0, CS1, CS0 and CS1 to the peripheral devices D1 and D2 via the selection circuit 24. This corresponds to the former chip select signals S3, S31, and S32. Further, the interrupt request signals INTRQ and INTRQ from the peripheral devices D1 and D2 in the latter are transmitted as the interrupt request signal INTRQ to the computer main body C via the selection circuit 24, and these are the interrupt requests in the former. This corresponds to the request signals S41, S42 and S4.
[0040]
In FIG. 2, an anonymous control signal including bits other than the 4-bit DD4 of the data bus is transmitted bidirectionally between the computer main body C and the peripheral devices D1 and D2. Corresponds to the control signal S5 in FIG.
[0041]
In the above description, the number of peripheral devices D1 and D2 may be n (where n ≧ 2). At this time, in order to specify and store the selected peripheral device Di (i = 1, 2,... N), the storage circuit 22 may be a memory of 2 bits or more. It is assumed that the selection signal S2 is generated according to the peripheral device Di that has been transmitted. The selection circuit 24 transmits the chip select signal S3 from the computer main body C to the selected peripheral device Di, and transmits the interrupt request signal S4i from the selected peripheral device Di to the computer main body C. Good.
[0042]
Such an interface cable is equipped with a connector 11 on the main body side, one of the equipment-side connectors 12 and 12 and a control circuit 20 on one board PB (FIG. 3). The other of 12 can be constituted by being pulled out from the substrate PB via a multi-core flat cable FC. In general, since a notebook personal computer can be loaded with only one peripheral device D1, the interface cable having such a configuration loads the peripheral device D1 into the personal computer and loads the other peripheral device D2. It can be conveniently used when adding externally. However, the board PB at this time is formed so as to be insertable into a slot for loading the peripheral device D1 provided in the personal computer and fixed to the front surface of the peripheral device D1, and the flat cable FC extends along the peripheral device D1. The connector 12 is formed to a length that can be pulled out to the outside.
[0043]
【The invention's effect】
As described above, according to the present invention, a control circuit is interposed between a connector on the main body side and a connector on the device side, and a selection command from the computer main body side is detected and stored in the control circuit. Since there is no need to set the master and slave in advance via the setting switch, it can be freely selected from the computer body side, so there is no need for troublesome setting operations. There is an excellent effect that there is no fear of any.
[Brief description of the drawings]
[Fig. 1] Overall block diagram [Fig. 2] Detailed block diagram [Fig. 3] Schematic diagram of overall configuration [Explanation of symbols]
C: Computer main body D1, D2: Peripheral device SW: Selection switch S3, S31, S32, CS0, CS1 ... Chip select signals S4, S41, S42, INTRQ ... Interrupt request signals 11, 12 ... Connector 20 ... Control circuit 23 ... Selection signal generation circuit 24 ... selection circuit 25 ... data bus control circuit

Claims (4)

It comprises a main body of the connector for connecting to the computer, and the device-side connector to be connected to each of the plurality of peripheral devices, the main body of the connector, and a control circuit which is interposed between the device-side connector, the The control circuit is mounted on a board that can be inserted into a slot for loading a peripheral device of a personal computer together with the connector on the main body side, detects and stores a selection command from the computer main body , and for the peripheral device selected by the selection command An interface cable in a computer system for transmitting a chip select signal from a computer main body and transmitting an interrupt request signal from a selected peripheral device to the computer main body. The control circuit includes a selection signal generation circuit, and the selection signal generation circuit controls a selection circuit that selects a transmission destination of a chip select signal and an input destination of an interrupt request signal in accordance with the contents of the stored selection instruction. The interface cable in a computer system according to claim 1. 3. The interface cable in a computer system according to claim 2, wherein the selection signal generation circuit is provided with a manual selection switch for correcting the content of the selection command . 4. The control circuit includes a data bus control circuit, and the data bus control circuit controls the contents of a specific bit of the data bus according to the contents of a stored selection instruction. An interface cable in the computer system according to any one of the above.

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