JPH09114562A - Interface cable in computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformly set all the peripheral equipments to a master by detect- storing a selection instruction from a computer main body, transmitting a chip select signal from the computer main body to a selected peripheral equipment and transmitting an interruption request signal from the peripheral equipment to the computer main body. SOLUTION: In accordance with the contents of the selection instruction stored by a storing circuit 22, a selection signal preparing circuit 23 prepares a selection signal S2. When the selection signal S2 specifies a peripheral equipment D1, e.g. a selection circuit 24 transmits the chip select signal S3 from the computer main body C to the peripheral equipment D1 as a chip select signal S31 and transmits the interruption request signal S41 from the peripheral equipment to the computer main body C as an interruption request signal S4. In addition when the selection signal S2 specifies a peripheral equipment D2, a selection circuit 24 transmits the chip select signal S3 from the computer main body C to the peripheral equipment D2 as a signal S32 and to the computer C as the interruption signal S4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, particularly a small personal computer system, which facilitates selection of peripheral devices when a plurality of peripheral devices are commonly connected to a single input / output port. The present invention relates to an interface cable in a computer system capable of switching control.

[0002]

2. Description of the Related Art In a small computer system including a personal computer, a plurality of peripheral devices may be connected to a single input / output port and a specific one may be selected and used. , For example IDE interfaces are known.

This device uses a 40-pin connector and can connect two peripheral devices to a single input / output port. Each peripheral device is set in a master / slave relationship with each other. ing. That is, each peripheral device has a built-in setting switch, and by setting one as a master and the other as a slave, each peripheral device can be individually accessed from the computer main body side. If only one peripheral device is connected, this must be set as the master. When the power is turned on, each peripheral device executes self-diagnosis in response to the reset signal, and the diagnosis result at this time is transmitted to the computer main body side through the master after confirming the existence of the slave. Because it is.

[0004]

In the prior art, since the peripheral device which is started from the computer main body when the power is turned on is fixed to the master side, if it is changed to the slave side, the peripheral device is changed. It is necessary to reset the setting switch inside, and the problem that the setting operation is extremely troublesome is inevitable. Also, at this time, if both peripheral devices are mistakenly set as master or slave,
Input and output data may collide, resulting in a fatal data destruction accident.

Therefore, in view of the problems of the prior art, an object of the present invention is to uniformly set all peripheral devices as masters by interposing a simple control circuit between the connectors of the interface cable. Therefore, it is an object of the present invention to provide an interface cable in a computer system that not only does not require a troublesome setting operation but also has no risk of a data destruction accident due to an erroneous setting.

[0006]

SUMMARY OF THE INVENTION To achieve the above object, the structure of the present invention comprises a main body side connector connected to a computer main body, a device side connector connected to each of a plurality of peripheral devices, and an inter-connector connector. The control circuit detects and stores a selection command from the computer main body, transmits a chip select signal from the computer main body to the selected peripheral device, and transmits the chip select signal from the selected peripheral device. The main point is to transmit the interrupt request signal to the computer main body.

The control circuit includes a selection signal generation circuit, and the selection signal generation circuit selects the transmission destination of the chip selection signal and the input destination of the interrupt request signal according to the contents of the stored selection command. Can be controlled, and a manual selection switch can be attached to the selection signal generating circuit.

Further, the control circuit includes a data bus control circuit, and the data bus control circuit can control the content of a specific bit of the data bus according to the content of the stored selection instruction.

[0009]

According to the structure of the invention, the control circuit is
By detecting and storing a selection command from the computer main unit, transmitting a chip select signal to the selected peripheral device, and transmitting an interrupt request signal from the selected peripheral device It can be connected to the computer main body and can be selected to be controllable from the computer main body side. That is, even if the built-in setting switch is uniformly set to the master side, each peripheral device can be operated by selecting any one from the computer main body side.

When the control circuit includes a selection signal generating circuit, the selection signal generating circuit selects a transmission destination of the chip select signal and an input destination of the interrupt request signal via the selection circuit, thereby providing a predetermined peripheral device. Can be selected and activated.

If a manual selection switch is attached to the selection signal generating circuit, the operation contents of the selection signal generating circuit can be switched by operating the selection switch. Therefore, the selection switch is a selection command from the computer main body side. It is possible to modify the contents of and to arbitrarily change the peripheral device actually selected by the selection command.

When the data bus control circuit is provided in the control circuit, the data bus control circuit can control the content of the specific bit of the data bus. Therefore, for example, an IDE interface, the specific bit of the data bus is controlled. Even when it is shared with the peripheral device selection operation, it can be handled without any trouble.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

The interface cable in the computer system has a control circuit 20 interposed between the connector 11 on the main body side and the connectors 12, 12 on the device side (FIG. 1).

The connector 11 on the main body side corresponds to a single input / output port Ca in the main body C of the computer. Further, the connectors 12 on the device side are respectively connected to two peripheral devices D1 and D2 commonly connected to the input / output port Ca.
It corresponds to one of. However, peripheral devices D1 and D2
May be any information input / output device including, for example, a hard disk device, a CDROM device, or the like.

A selection command signal S from the computer main body C
1 is input to the detection circuit 21 of the control circuit 20 via the connector 11 on the main body side. The output of the detection circuit 21 is
It is connected to the memory circuit 22, and the output of the memory circuit 22 is connected to the selection signal creating circuit 23. A selection switch SW is attached to the selection signal creation circuit 23. Also,
The selection signal S2 from the selection signal creation circuit 23 is input to the selection circuit 24.

The chip select signal S3 from the computer main body C is sent to the selection circuit 2 via the connector 11 on the main body side.
4 has been entered. The output of the selection circuit 24 is output as chip select signals S31 and S32 to the connector 12 on the device side.
It is individually input to the peripheral devices D1 and D2 via 12.

On the other hand, the interrupt request signals S41 and S42 from the peripheral devices D1 and D2 are input to the selection circuit 24 through the connectors 12 on the device side. In addition, the selection circuit 24
Is output as an interrupt request signal S4 to the computer main body C via the connector 11 on the main body side. In addition, between the computer main body C and the peripheral devices D1 and D2,
Other common control signals, data signals, etc. (hereinafter simply referred to as control signals) S5 are collectively and bidirectionally transmitted via the connectors 11, 12, 12.

Now, when the selection command signal S1 is output from the computer main body C to select one of the peripheral devices D1 and D2, the detection circuit 21 of the control circuit 20 causes the selection command included in the selection command signal S1. Is detected and the memory circuit 22
Can store the content of the detected selection instruction. In other words, the storage circuit 22 can store another peripheral device Di (i = 1, 2) selected by the selection command.

Therefore, the selection signal creating circuit 23 creates the selection signal S2 in accordance with the content of the selection command stored in the storage circuit 22. However, the selection signal generating circuit 23 at this time is, for example, the peripheral device D stored in the storage circuit 22 when the selection switch SW is turned on.
A selection signal S2 for directly designating i is generated, but when the selection switch SW is not turned on, the memory circuit 22
Peripheral device Dj (j
It is assumed that a selection signal S2 designating = 2, 1) is generated. That is, the selection signal creation circuit 23 can make necessary corrections to the content of the selection command from the computer main body C according to the closing state of the selection switch SW.
The selection switch SW is manually operated by an operator as appropriate.

According to the selection signal S2 from the selection signal generating circuit 23, the selection circuit 24 sends the chip selection signal S3 from the computer C to the selected peripheral device Di (or Dj) as the chip selection signal S3i (or S
3j) and select peripheral device Di (or D)
The interrupt request signal S4i (or S4j) from j) is transmitted to the computer main body C as the interrupt request signal S4. That is, the selection circuit 24 can select the transmission destination of the chip selection signal S3 and the input destination of the interrupt request signals S41 and S42 according to the selection signal S2.

For example, when the selection signal S2 designates the peripheral device D1, the selection circuit 24 changes the chip select signal S3 from the computer main body C to the chip select signal S31.
As an interrupt request signal S4 from the peripheral device D1 to the computer C as an interrupt request signal S4. When the selection signal S2 designates the peripheral device D2, the selection circuit 24 changes the chip select signal S3 from the computer main body C to the chip select signal S32.
As an interrupt request signal S4 from the peripheral device D2 to the computer C as an interrupt request signal S4.

That is, when the computer main unit C selects one of the peripheral devices D1 and D2 by outputting the selection command signal S1, the memory circuit 22 causes the memory circuit 22 to select the selection command signal S1.
The peripheral device Di selected by is stored, and the selection signal creating circuit 23 determines whether or not the selection switch SW is turned on.
Through the selection circuit 24, the selected peripheral device Di or the peripheral device Dj opposite thereto can be connected to the computer main body C substantially. Therefore, thereafter, the computer main body C can freely access the predetermined peripheral device Di (or Dj). Note that the control signal S5 is bidirectionally transmitted between both the peripheral devices D1 and D2 and the computer main body C, and if necessary, the peripheral device Di actually selected by the selection circuit 24.
(Or Dj) or as information from its peripheral Di (or Dj).

The selection switch SW is not always necessary, and by omitting it, the selection signal creating circuit 23 can always access the peripheral device Di stored in the storage circuit 22 as it is. Can be

A concrete example of the case where the present invention is applied to an IDE interface is shown in FIG.

In the figure, the detection circuit 2 of the control circuit 20
1 is configured by connecting two AND gates in cascade.
Address signals DA0, DA are provided to the AND gate in the preceding stage.
1, DA2, chip select signals CS0, CS1 are input, and the write strobe signal DIOW is input to the AND gate in the subsequent stage. The white small circles in each gate indicate that the low level of the signal level is significant. Therefore, the detection circuit 21 can output the device head register access signal DHRW and the device head register write signal DHW to the peripheral devices D1 and D2 as the outputs of the AND gates.
In the IDE interface, the address signal DA0,
This is because a combination of DA1, DA2 and chip select signals CS0, CS1 of low, high, high, low, high indicates access to the device head register.

That is, the detection circuit 21 shown in FIG. 2 can detect the selection command from the computer main body C and output the device head register write signal DHW.

The memory circuit 22 receives the device head register write signal DHW from the detection circuit 21 at the clock terminal C.
It is composed of a flip-flop input to K. The 4-bit DD4 of the data bus is connected to the data terminal D of the flip-flop, and the clear terminal CLR is
The reset signal RESET is input. Therefore, the memory circuit 22 outputs the device head register write signal DH.
At the rising edge of W, 4-bit DD4 of the data bus can be stored and output to the output terminal Q of the flip-flop as the device selection signal DSEL.

The device selection signal DSEL is set to a low level when the peripheral device D1 is selected, and is set to a high level when the peripheral device D2 is selected.
4-bit DD4 of the data bus corresponding to the write operation of the device head register in the IDE interface
Is a master selection at a low level and a slave selection at a high level. However, in the memory circuit 22, the device selection signal DSEL is initialized to a low level by the reset signal RESET at the same time when the power is turned on.

That is, the memory circuit 22 is the detection circuit 21.
When the selection command from the computer main body C is detected by the, the contents are stored and the device selection signal DSEL
Can be output as

The selection signal generating circuit 23 receives the device selection signal DSEL and the selection switch S via the pull-up resistor.
The selection signal creation circuit 23, which is composed of two sets of exclusive OR gates for inputting the input state signal SWS of W, has a first selection signal DR1 for instructing the selection of the peripheral device D1 as an output of each exclusive OR gate, and a peripheral device. It is possible to generate the second selection signal DR2 instructing the selection of D2. However,
The first selection signal DR1 is selected when the selection switch SW is turned on and the device selection signal DSEL selects the peripheral device D1, or when the selection switch SW is not turned on and the device selection signal DSEL changes the peripheral device D2. Effective when selecting. The second selection signal DR2 has the selection switch SW turned on and the device selection signal D2.
When the SEL selects the peripheral device D2, or when the selection switch SW is not turned on, the device selection signal DS
This is effective when EL selects the peripheral device D1.

That is, the selection signal creating circuit 23 is responsive to the device selection signal DSEL from the memory circuit 22 to generate the first signal.
The selection signal DR1 and the second selection signal DR2 can be output.

The selection circuit 24 receives a first selection signal DR1 and a second selection signal DR2, and two sets each of which receives a first selection signal DR1 and a second selection signal DR2.
Chip select signal C depending on which one is effective
The transmission destinations of S0 and CS1 can be selected as one of the peripheral devices D1 and D2. In addition, the selection circuit 24 combines the two sets of AND gates and OR gates to determine the peripheral of the input destination of the interrupt request signal INTRQ depending on which of the first selection signal DR1 and the second selection signal DR2 is valid. It is possible to select one of the devices D1 and D2. The interrupt request signal I from each peripheral device D1 and D2
A pull-down resistor is inserted in the signal line of the NTRQ in order to prevent the signal level when not in use from becoming indefinite.

The control circuit 20 of FIG.
The data bus control circuit 25 is added to the signal line of the bit DD4.

The data bus control circuit 25 includes two amplifiers in the reverse direction, one for transmitting signals from the computer main body C side to the peripheral devices D1 and D2, and the other for the other peripheral device D1. , D2 side can transmit signals to the computer main body C side. The operation of the former amplifier is controlled through an AND gate for inputting the write strobe signal DIOW and the device head register write signal DHW from the detection circuit 21, and the peripheral device D1,
It operates in response to a write command for a device other than the device head register of D2. A pull-down resistor is inserted at the output terminal of the former amplifier to prevent the signal level when it is not operating from becoming indefinite. on the other hand,
The operation of the latter amplifier is controlled by the read strobe signal DIOR so that it operates in response to all read commands.

However, although the input side of the former amplifier is directly connected to the computer main body C, the input side of the latter amplifier is opened / closed by a device head register access signal DHRW from the detection circuit 21 via an OR gate. 2 sets of AND gates are arranged side by side. One AND gate receives the 4-bit DD4 of the data bus from the peripheral devices D1 and D2, and the other AND gate selects the device from the memory circuit 22. The signal DSEL is input.

In other words, the data bus control circuit 25 activates the former amplifier in response to a write command to the peripheral devices D1 and D2 other than the device head registers, so that the 4-bit DD4 of the data bus is transferred to the computer main body C side. Can be transmitted to the peripheral devices D1 and D2. The data bus control circuit 25 operates the latter amplifier in response to the read command, but when the read command specifies the device head register, the device selection signal DSEL from the memory circuit 22 is sent to the computer main body C side. When the read command does not specify the device head register, the 4-bit DD4 of the data bus from the peripheral devices D1 and D2 can be directly transmitted to the computer main body C side.

In this way, the data bus control circuit 25 is added to the signal line of the 4-bit DD4 of the data bus in addition to the fact that the IDE interface uses the 4-bit DD4 of the data bus as a general data bus. Peripheral device D1 set as master, master, or slave
, D2 are also used in common to select one of them. Therefore, in the case of an interface in which a specific bit of the data bus is not used for such a special purpose, it is not necessary to provide the data bus control circuit 25.

Comparing FIG. 1 and FIG. 2, the components having the same reference numerals correspond to each other, and the latter address signal DA.
0, DA1, DA2, chip select signals CS0, CS
1. The write strobe signal DIOW collectively corresponds to the former selection command signal S1. The latter first selection signal DR1 and second selection signal DR2 collectively correspond to the former selection signal S2. Furthermore, in the latter case, chip select signals CS0, C from the computer main body C
S1 is a chip select signal CS0, CS1, CS0, CS for the peripheral devices D1, D2 via the selection circuit 24.
1, which correspond to the chip select signals S3, S31, and S32 in the former case. Also, the interrupt request signals INTRQ and INTRQ from the peripheral devices D1 and D2 in the latter are transmitted as the interrupt request signal INTRQ to the computer main body C through the selection circuit 24, and these are the interrupts in the former case. It corresponds to the request signals S41, S42, S4.

In FIG. 2, the computer main body C
Anonymous control signals including bits other than the 4-bit DD4 of the data bus are bidirectionally transmitted between the peripheral devices D1 and D2 and the peripheral devices D1 and D2.
It corresponds to.

In the above description, the peripheral devices D1 and D2
May be n (where n ≧ 2). At this time,
The memory circuit 22 stores the selected peripheral device Di (i = 1, 2
.. n) is specified and stored, a memory of 2 bits or more may be used, and the selection signal creating circuit 23 is assumed to generate the selection signal S2 in accordance with the selected peripheral device Di. Further, the selection circuit 24 sends a chip select signal S from the computer main body C to the selected peripheral device Di.
3 and the interrupt request signal S4i from the selected peripheral device Di may be transmitted to the computer main body C.

Such an interface cable is equipped with a connector 11 on the main body side, one of the connectors 12 and 12 on the device side, and a control circuit 20 on one board PB (FIG. 3). The other of the connectors 12 and 12 can be configured by being pulled out from the substrate PB via a multi-core flat cable FC. Generally, since only one peripheral device D1 can be loaded inside the notebook personal computer, the interface cable having such a configuration loads the peripheral device D1 into the personal computer and loads the other peripheral device D2. It can be conveniently used when adding it externally. However, the board PB at this time is formed so that it can be inserted into the loading slot of the peripheral device D1 provided in the personal computer, and is fixed to the front surface of the peripheral device D1.
Shall have a length such that the connector 12 can be pulled out to the outside along the peripheral device D1.

[0043]

As described above, according to the present invention, the control circuit is interposed between the connector on the main body side and the connector on the device side, and the control circuit detects and stores the selection command from the computer main body side. Depending on each peripheral,
There is no need to set the master or slave in advance via the setting switch, and you can freely select from the computer side, so there is no need for troublesome setting operations, and there is a risk of data destruction accidents due to incorrect settings. There is an excellent effect that there is no.

[Brief description of the drawings]

Fig. 1 Overall block system diagram

[Fig. 2] Detailed block system diagram

[Fig. 3] Overall configuration schematic diagram

[Explanation of symbols]

C ... Computer main body D1, D2 ... Peripheral device SW ... Selection switch S3, S31, S32, CS0, CS1 ... Chip select signal S4, S41, S42, INTRQ ... Interrupt request signal 11, 12 ... Connector 20 ... Control circuit 23 ... Selection signal generation circuit 24 ... Selection circuit 25 ... Data bus control circuit

Claims (4)

[Claims] 1. A main body side connector connected to a computer main body, a device side connector connected to each of a plurality of peripheral devices, and a control circuit interposed between the connectors, the control circuit comprising a computer. It is characterized by detecting and storing a selection command from the main body, transmitting a chip select signal from the computer main body to the selected peripheral equipment, and transmitting an interrupt request signal from the selected peripheral equipment to the computer main body. Interface cable in a computer system that works. 2. The control circuit includes a selection signal creating circuit, and the selection signal creating circuit selects a transmission destination of a chip select signal and an input destination of an interrupt request signal according to the contents of a stored selection command. The interface cable in a computer system according to claim 1, wherein the interface cable controls a selection circuit. 3. The interface cable in a computer system according to claim 2, wherein the selection signal generating circuit is provided with a manual selection switch. 4. The control circuit includes a data bus control circuit, and the data bus control circuit controls the content of a specific bit of the data bus in accordance with the content of the stored selection command. An interface cable in a computer system according to any one of claims 1 to 3.