JPH0143328B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output circuit, and more particularly to the configuration of a transfer data input/output circuit provided on a data transfer path between transmitting and receiving devices.

The input/output circuit is used, for example, to determine the direction of data transfer, the timing of data exchange, etc. when a microcomputer and its external memory transfer data to each other. Generally, it is also called an input/output port in the information processing field.

Conventional input/output circuits use a read control signal (hereinafter referred to as a read signal) and a write control signal (hereinafter referred to as a write signal) to instruct the direction of data transfer. These control signals are generated by a master processor that takes initiative in data transfer. Therefore, the input/output circuits connected to the master processor and the sub (slave) processors (for example, memory, key input devices, external peripheral devices such as printers, etc.) to which data transfer is instructed by commands from the master processor, etc. ) had a different circuit structure due to its nature. That is, the input/output circuit on the master processor side, as shown in FIG. It has an input/output section 1 that inputs and outputs data to and from a bus 4 connected to a subprocessor. On the other hand, the input/output circuit on the sub-processor side, as shown in FIG. An input/output unit 5 that performs switching between outputting data to the bus 8 connected to the master processor or inputting data on the bus 8 to the bus 7.
It has In this way, the input/output circuit connected to the master side (Figure 1) has only output terminals for read and write signals, while the input/output circuit connected to the sub side (Figure 2) has read and write signal output terminals. A master and a sub were distinguished by having only a signal input terminal. however,
As mentioned above, conventional input/output circuits have different mechanisms for master and sub circuits, and therefore have the disadvantage of lack of flexibility when changing the system. In particular, recently, multiprocessor systems using multiple master processors have been used, but the input/output circuits connected to each master processor are independently led, as shown in Figure 1. and generates a write signal. Therefore, within the plurality of master processors, a processor was required to supervise them. This is due to the inconvenience that each master processor cannot be controlled by other master processors, that is, its input/output circuit cannot be used as a sub input/output circuit. For this reason, the operator cannot freely decide the master processor according to the program, but is restricted to having to program within a given system system. Furthermore, a one-chip processor including an input/output circuit has the disadvantage that it can only be used as a master processor and does not allow control from other processors.

An object of the present invention is to provide a versatile input/output circuit that can be applied both as a master and as a sub.

The present invention is an input/output circuit used in a microcomputer, and includes a data latch circuit provided between a data input/output terminal of the microcomputer and an internal bus, and a data latch circuit provided between a data input/output terminal of the microcomputer and an internal bus, and a data input/output circuit that receives data input from the outside through the data input/output terminal. a first means for latching the latched data to the data latch circuit; a second means for transferring the latched data to the internal bus; a third means for latching the data on the internal bus to the data latch circuit; A fourth means for transferring data to the data input/output terminal, a write signal for instructing to transfer data on the internal bus to the outside, and a write signal for instructing to transfer external data input from the data input/output terminal to the internal bus. A read/write generation circuit that generates a read signal and a read signal inside the microcomputer, a read/write input/output terminal that outputs the generated read signal and write signal to the outside, and inputs a read signal and a write signal from the outside; A circuit that generates a mode signal that specifies whether the computer operates in master mode or slave mode, and a read signal that is output from the read/write input/output terminal when the mode signal specifies master mode. On the other hand, when the mode signal specifies the slave mode, the first and second means are activated in response to a write signal input from the read/write input/output terminal, and the data is input from the data input/output terminal. a fifth means for transferring external data to the internal bus via a data latch circuit; When the signal specifies the slave mode, the third and fourth means are activated in response to the read signal input from the read/write input/output terminal, and the data on the internal bus is transferred through the data latch circuit. and a sixth means for transferring data to an input/output terminal.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a circuit configuration block diagram showing an embodiment of the input/output circuit according to the present invention. The input/output circuit of this embodiment is provided between buses 12 and 13, and includes a path for data transfer between both buses 12 and 13, a data input section, and a data output section. unit 9, and a control unit 10 that controls the transfer direction of data transferred by the data transfer unit 9.
and an instruction section 11, which will be described later. The control unit 10 includes means for generating read signals and write signals, and means for externally inputting read signals and write signals having the same function. Here, the external means another processor having a read/write signal generating means, or an input/output circuit connected to the processor, and includes the read/write signal generating means provided in the control unit 10 in FIG. It means something that one has. Further, the instruction section 11 has a mode specifying means for determining whether to use the read/write signals generated from the control section 10 shown in FIG. 3 or the read/write signals inputted from the outside. Note that when a data transmitting/receiving device such as a program execution device such as a microprocessor or an arithmetic processing device is connected to the bus 12 as a master processor A, the master processor A transmits and receives data. Target devices (for example, memory, other processors, or peripheral devices such as keyboards and printers) are connected to the bus 13 side.

By configuring the input/output circuit in this way, when the processor A connected to the bus 12 is used as a master, the instruction section 11 sends read and write signals to the control section 10 and outputs them to the target device. Just give instructions. As a result, read and write signals within the control unit 10 are generated externally as an output mode. Furthermore, if a read signal is generated at this time, data will be input from the target device, so the data transfer unit 9 uses a data path that can input data from the bus 13 and transfer it to the bus 12. . On the other hand, if a write signal is generated, data will be output to the target device, so a data path is used in which the own data transfer section 9 can output the data on the bus 12 to the bus 13. This path selection and control is performed by a control signal C from the control section 10.

Furthermore, in the above connection state, processor A is
That is, if it is desired to use it as being controlled by another processor, the instruction section 11 may instruct the control section 10 to accept read/write signals input from the outside. As a result, the control unit 10
is prepared to respond not to a read/write signal generated from its own read/write signal generating means but to a read/write signal input from the outside. Note that the data transfer unit 9 may be controlled by the control unit 10 using the same control method as when the data transfer unit 9 is the master. Note that the read signal from the outside is handled by the control unit 1.
The target device may be connected in such a manner that the write signal is input from the write signal output terminal of the controller 10, and the write signal from the outside is input from the read signal output terminal of the control unit 10.
Also, it is clear that even if the device is connected to the target device in this way, it is no different from the connection when the device itself is used as a master.

In this way, according to this embodiment, the third
Only one input/output circuit shown in the figure can be used for both purposes. Therefore, in addition to being versatile in terms of system configuration, the degree of freedom in design is also significantly improved. In particular, it will be understood that when the input/output circuit of FIG. 3 is integrated on the same chip as processor A, the above effect becomes even greater. Although the instruction section 11 may be configured to specify the mode by program operation, the control section 10 is provided with a switching gate for selecting between an internally generated read/write signal and an externally input read/write signal. In this case, the mode may be designated by operating a switch.

A more detailed explanation of the input/output circuit of this embodiment will be given below, with a preferred example of the circuit shown in FIG.

FIG. 4 is a diagram depicting the block diagram of FIG. 3 in detail, and the part enclosed by the dotted line in FIG.
It is 4. _P0 has 14 input/output terminals connected to corresponding bit lines of bus 13. 15 is a data latch, 16 and 17 are three-state buffers, 1
8, 19 are N-channel IGFET transfer gates, 20 is OR gate, 21, 22, 23
is an inverter, 24, 25 are NOR gates, 26,
27 and 28 are three-state buffers, 29 is a flip-flop for mode switching, 30 is a read/write signal timing generation circuit, /,
WR/ stands for read/write and write/, respectively.
The read signal input/output terminal is a chip select terminal. The three-state buffers 26, 27, and 28 are activated by setting the mode switching flip-flop to "1" by a program. Therefore, this state is a mode in which the read signal is output from the generating circuit 30 to the / terminal and the write signal is output to the / terminal. That is, the processor A shown in FIG. 3 is operating as a master processor. At this time,
Since the input/output circuit must be set to an operating state, the CS signal becomes "0". Furthermore, when the write signal “0” is output from the / terminal,
The NOR gate 24 becomes "1" and the three-state buffer 16 is activated. Therefore, the Q output of the data latch 15 is read out to the _P0 terminal through the buffer 16 and connected to the external data bus (1 in FIG.
3). As a result, the peripheral device that received the write signal is set to the write state, so the output from P ₀ is written there. on the other hand,
When the read signal RD "0" is output from the / terminal, the NOR gate 25 becomes "1" and the data clutch 15 enters the write state because "1" is input to the read gate G via the OR gate 20. In this state, transfer gate 18 becomes conductive and transfer gate 19 becomes non-conductive.
Therefore, data read from the peripheral device onto the external data bus (13 in FIG. 3) is transferred from the _P0 terminal through the transfer gate 18 to the latch 1.
5 and is written to the data latch 15 at the trailing edge of the read signal "0". That is, in this mode, processor A connected to data bus 12 (FIG. 3) can control other peripheral devices as a master.

On the other hand, when the contents of the mode switching flip-flop 29 are programmed to "0", the three-state buffers 26, 27, and 28 are all placed in a floating state. In this state, all output signals from the generation circuit 30 are prohibited, and/or
Both RD/terminals operate as input terminals. Therefore, when a read signal is sent from the processor connected to the bus 13 side and is input to the / terminal, it becomes "1" through the NOR gate 24.
A signal is input. As a result, the three-state buffer 16 is activated and the data stored in the data latch 15 is output to the _P0 terminal. This data is transferred via the external data bus 13 to another intended microprocessor. on the other hand,
When a write signal is input from the RD/ terminal,
NOR gate 25 becomes "1", 20 becomes "1",
22 becomes “1”, 23 becomes “0”, and gate 1
8 is conductive, and gate 19 is cut off. Therefore,
Data is written into the data latch 15 from the P ₀ terminal through the transfer gate 18 .

In this way, the flip-flop 2 for mode switching
Depending on the state of 9, in other words/and
By setting the input/output state of the RD/terminal, this input/output circuit can be used for control or non-control. This leads to the effect that there is no need to change the circuit design whether it is used as a master or a sub. In particular, if this input/output circuit is incorporated into a single-chip microcomputer, it can be used as a microprocessor or as a subprocessor. Program control becomes very easy.

The signal terminals shown in FIG. 4 are terminals for inputting and outputting signals instructing the opening and closing operations of the NOR gates 24 and 25 for determining the operating state of the data transfer section (block 14). That is,
If this signal is “1”, the NOR gates 24, 2
5 are closed, and even if a read/write signal is input from the outside or inside, the data transfer section 14 is in a non-operating state, and the buses 13 and 12 in FIG. 3 are electrically disconnected. becomes. Therefore, this signal (a signal that controls whether or not to give a read/write instruction to the transfer unit) is useful when three or more target devices that input/output read/write signals are connected to the bus 13. be. For example, if five processors P ₁ to _{P 5} are interconnected by a common bus, and data transfer is performed only between P ₁ and P ₅ , the other processors P ₂ , P ₃ ,
P ₄ must be separated from the bus. In such a case, it is sufficient to give a CS signal of "1" to P ₂ , P ₃ and P ₄ and a CS signal of "0" to P ₁ and P ₅ . Above, an example has been described in which each circuit is activated with "0", but of course it may be activated with "1".

FIG. 5 shows a system block diagram to which an embodiment of the present invention is applied. 31 and 32 are one-chip microcomputers each having an input/output circuit according to the present invention, and the respective / terminals and / terminals are connected respectively, and all bits (PORT) of the data conversion section are connected in parallel with each other. are doing. Each of the resistors r connected to the power supply voltage _Vcc functions as a pull-up resistor during floating. 31 and 32
can be arbitrarily switched to the control side or the controlled side by a program, external key input, or switch operation. It can be known from the status signal S which side is the control side or the non-control side. Therefore, it is set so that both do not become the control side at the same time. If you do it like this
Data can be transferred between CPUs at once at high speed, and there is no need to transfer data serially in synchronization with a serial clock as in the past, and there is no need to have a serial-to-parallel conversion circuit or a parallel conversion circuit. Therefore, the chip size becomes smaller and costs can be reduced. Furthermore, when the data in the built-in RAM of one microcomputer becomes full, the data that cannot be stored can be stored in the other microcomputer and read out later, increasing the degree of freedom in processing operations. greatly expanded. Of course, it is also possible to use three or more microcomputers of the present invention and perform various processes while changing the master-slave relationship with each other.

Furthermore, the input/output circuit of the present invention may be formed on the same chip, or only the data transfer section may be formed on one chip.
It is possible to integrate the control section within the processor as appropriate depending on the design.

[Brief explanation of drawings]

1 and 2 are block diagrams of conventional input/output circuits, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a preferred specific example of the embodiment of FIG. 3. The circuit diagram shown in FIG. 5 is a system configuration diagram of a multiprocessor using the present invention. 1, 5, 9...data transfer section, 2, 6, 10...
...Control unit, 3, 7, 12...Internal data bus,
4, 8, 13...external data bus, 11...instruction section, 29...flip-flop for mode switching, 1
6, 17, 26, 27, 28... Three-state buffer, 24, 25... NOR gate, 20...
...OR gate, 21, 22, 23... Inverter, 15... Data latch, 18, 19... N-channel IGFET, 30... Timing generation circuit,
31, 32...1 chip microcomputer.

Claims (1)

[Claims] 1 An input/output circuit used in a microcomputer, which includes a data latch circuit provided between a data input/output terminal of the microcomputer and an internal bus, and a data latch circuit provided between a data input/output terminal of the microcomputer and an internal bus, and a data input/output circuit that inputs data from the outside through the data input/output terminal. a first means for latching the latched data to the data latch circuit; a second means for transferring the latched data to the internal bus; a third means for latching the data on the internal bus to the data latch circuit; a fourth means for transferring the data to the data input/output terminal, a write signal instructing to transfer the data on the internal bus to the outside, and a fourth means for transferring the external data input from the data input/output terminal to the internal bus. a read/write generation circuit that generates a read signal instructing the microcomputer to perform the above operations; and a read/write input/output circuit that outputs the read signal and write signal to the outside and inputs the read signal and write signal from the outside. a circuit that generates a mode signal that specifies whether the microcomputer operates in master mode or slave mode; and when the mode signal specifies master mode, the read/write input/output terminal; said first and second means in response to a read signal outputted from said read/write input/output terminal, and in response to a write signal inputted from said read/write input/output terminal when said mode signal specifies slave mode. a fifth means for activating the external data input from the data input/output terminal to transfer the external data input from the data input/output terminal to the internal bus via the data latch circuit; In response to a write signal outputted from the input/output terminal, on the other hand, when the mode signal specifies slave mode, in response to a read signal inputted from the read/write input/output terminal, the third and fourth and sixth means for activating the means for transferring data on the internal bus to the data input/output terminal via the data latch circuit.