KR890008696A - Port Expansion Circuit for Input / Output Interfaces for Peripherals - Google Patents

Abstract

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Description

Port Expansion Circuit for Input / Output Interfaces for Peripherals

Since this is an open matter, no full text was included.

1 is a circuit diagram of the present invention,

2 is a detailed circuit diagram of the channel expansion circuit portion of FIG.

3 is a flowchart showing a circuit operation procedure of the present invention.

Claims (1)

In an interface circuit for controlling peripheral devices of a computer, a data readout signal RD, an input / output request signal IORQ with a peripheral device, a data write signal WR, and data are connected to a data bus and an address bus to execute a data processing and control function program. a decoding circuit for input to the central processor 10 for controlling the whole system, addresses a ₀ -A ₁₅ of the 3-bit address a ₁₃ -A ₁₅ and the control signal MREQ outputs a signal MREQ for controlling data transfer on the bus RAM 12, which is chip-enabled by the output logic signal of (11), is allocated a channel area according to the number of printers, and is controlled to read and write data by the data write signal WR described above, and the three bits. The chip is enabled by the output logic circuit of the decoding circuit 13 for inputting the addresses A ₁₃ -A ₁₅ and the control signals WR and MREQ described above. Output of ROM 14 storing program as control means, decoding circuit 15 for inputting addresses A ₂ -A ₇ to output a 3-bit enable enable signal, and the following signal control circuit 23. A state register 16 is chip-enabled by input / output of the state register 16 which searches for the BUSY signal which designates the operation state of a printer which is a control signal, and the load signal STB which controls the data transmission of a printer, and the input and output of the said decoding circuit 15. A channel selection register 17 for inputting the output of the data 16 and the data D ₀ -D ₁ of the data bus in common to output the channel selection signals SEL _0- SEL ₂ , and RD, IORQ and WR which are the control signals described above. The data input and output are decoded by the output logic signal of the decoding circuit 18 for inputting the chip, and the chip is enabled by the input / output of the decoding circuit 15, and also compared with the input ports PA ₀ -PA ₇ of the computer output data. Output to output the set data And the output port PB ₀ -PB ₇ and a control signal STB, and a parallel port and a control PC ₀ -PC ₇ to control the BUSY signal input-output circuit 19 and, butter (20) for inputting the output data of the computer A comparator 22 for comparing the outputs of the output ports PB ₀ -PB ₇ , a signal adjusting circuit 23 for inputting the output of the comparator 22 and the STB and BUSY signals to output a logic signal according to the input signal, and A channel selection display circuit 25 which decodes the channel selection signals SEL _{0 to} SEL ₂ of the channel selection register 17 into an 8-bit signal so that the LED corresponding to the selected channel is turned on; A channel expansion circuit for providing STB and INTI signals by selecting a corresponding channel by inputting a channel selection signal, and transmitting data through a selected channel by inputting an operation status signal BUSY signal and an error signal of the printer through the selected channel (25). ), Including Port expansion circuit of the input-output interface for the peripheral device, characterized in a. ※ Note: The disclosure is based on the initial application.