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Fujitsu Ltd
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Fujitsu Ltd
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Publication date
Application filed by Fujitsu LtdfiledCriticalFujitsu Ltd
Priority to JP58049277ApriorityCriticalpatent/JPS59174016A/ja
Publication of JPS59174016ApublicationCriticalpatent/JPS59174016A/ja
Publication of JPH0418330B2publicationCriticalpatent/JPH0418330B2/ja
Asynchronous clock switching between first and second clocks by extending phase of current clock and switching after a predetermined time and appropriated transitions
Asic bus interface having a master state machine and a plurality of synchronizing state machines for controlling subsystems operating at different clock frequencies