JPH04182852A - Dma control processing system - Google Patents

Abstract

PURPOSE:To speed up DMA transfer by sending out a transfer end preparation signal for data transfer right before final data transfer. CONSTITUTION:It can be known previously with a signal PRESTOP that a signal TSTOP1 is sent out in synchronism with next data transfer. A signal TSTOP2 can, therefore, precede the signal TSTOP1. When the signal TSTOP2 to be timed with the trailing edge of a final signal DACK2 is sent out irrelevantly to the signal TSTOP1, the signal can lead the signal TSTOP1, so its transmission period can be made to overlap with the transmission period of a signal DREQ1 and the time is therefore shortened to speed up the DMA transfer.

Description

[Detailed Description of the Invention] [Summary] The present invention aims to provide a DMA control processing method that enables high-speed data transfer.

Regarding a DMA control processing method when DMA interfaces are different.

A data processing device comprising a data processing device employing a first DMA interface and an extension section employing at least a second DMA interface.

DMA control means for sending a predetermined signal for the first DMA interface; conversion means for converting the signal for the first DMA ink face into a signal for the second DMA interface; and the DMA
The control means sends a transfer end preparation signal corresponding to the data transfer immediately before sending the transfer end signal corresponding to the last data transfer, and the converting means receives the transfer end preparation signal and sends out the transfer end preparation signal. The configuration is such that a signal corresponding to the transfer end signal is sent out at a predetermined timing prior to sending out the body symbol.

[Industrial Application Field] The present invention relates to a DMA control processing method, and more specifically,
DMA@? when DMA interfaces are different?
This relates to an ill processing method.

DMA (Direct Me+go) is one of the data transfer methods between main memory and input/output devices.
ryAccess) method. According to the DMA method,
Data transfer can be done without processor intervention.

It can reduce the burden on the processor.

[Conventional technology]

Even when data is transferred using the DMA method.

As well as normal processor-involved data transfers.

Control for synchronization such as handshake is required.

This DMA system m system system MA ink face) is 1st order, for example, 2nd order.

Now, assume that data is transferred by DMA from the input/output device to the main memory. In this case, the input/output device sends a data request signal DREQ to the DMA controller (DMAC). On the contrary.

DMAC is a data acknowledge signal DA to the input/output device.
Upon receiving the CK, the input/output device sends data onto the 5 data bus. Further, the DMAC sends a transfer end signal TSTOP to the input/output device approximately in synchronization with the last signal DACK.

The above DMA interface (first interface) sends out the signals DREQ, DACK, and TSTOP at predetermined timings. Note that the signal DACK is
In this case, it is a response to the signal DREQ and is also a signal instructing data transfer.

Furthermore, as is well known, DMA transfer is performed in multiple steps between the memory and the input/output device.

[Problem to be solved by the invention]

Assume that a certain data processing device employs (supports) the first interface described above.

A DM different from the first interface for this device.
It is conceivable to expand the system by connecting an input/output device that employs the A interface (second interface). The second ink face.

For example, there is an ink face in which the signal DACK is used only as a response to the signal DREQ, and a signal instructing data transfer is sent separately.

In this case, in order to perform DMA transfer between the device and the expansion input/output device, it is necessary to convert the first interface to the second interface.

However, a problem arises in that the data transfer cannot be made faster in order to ensure the timing of transmitting the transfer end signal TSTOP in the second interface after this conversion.

That is, in the first interface, the transfer end signal TS
It is not known which signal DACK the TOP is sent with. On the other hand, in the second interface, the transfer end signal TSTOP must be sent at a predetermined timing with respect to other signals. For this reason.

For each signal DACK, that is, for each data transfer, time must be secured for sending the transfer end signal TSTOP. Therefore, it is not possible to increase the speed of data transfer.

The present invention provides DMAs1 that enable high-speed data transfer.
11m processing method.

[Means to solve the problem]

FIG. 1 is a diagram illustrating the principle of the present invention and shows a data processing apparatus according to the present invention.

In Figure 1, 11 is the CPU, 2 is the memory, and 3 is the DMA.
C, 4 (4-1, 1-2) are input/output devices.

5 is a conversion adapter, 6 and 7 are input/output devices, 10 is a data processing device before expansion, and 20 is an expansion part.

The data processing device 1O is a data processing device before the expansion section 20 is expanded or added, and the data processing device 10
1 method (DMA interface) if(1) is adopted.

Therefore, the DMAC5 which is a DMA control means.

A predetermined signal for the DMA interface 1f(1) is sent to the input/output device 4 and the conversion adapter 5 at a predetermined timing. The entry/exit interior W4 is ink face 1f (
1) will be adopted.

The extension portion 20 is for the data processing bag 210.

This is a part that will be added later to expand its functionality.
At least the second DMA control method (DMA interface) if(2) is adopted.

For this purpose, a conversion adapter 5 is used as a conversion means.

A signal for interface 1f(1) is converted into a signal for interface 1f(2).

The input/output devices 6 and 7 each have an interface i f
(1) and if (2) are adopted.

[For production]

When performing DMA transfer, the DMAC 5 sends out a signal for the interface 1f(1). At this time.

DAMC3 sends a transfer end preparation signal P in addition to the transfer end signal.
Send RESTOP. The former is sent in response to the last data transfer, and the latter is sent in response to the data transfer immediately before sending the transfer end signal.

The conversion adapter 5 is an input/output device 6 connected to itself.
When performing MA transfer, the signal for the interface if[) is converted into a signal for the interface i r (2) and sent to the input/output device 6. At this time, upon receiving the transfer end preparation signal PRESTOP, the conversion adapter 5 generates a signal (TSTOP(2)) corresponding to the transfer end signal (expressed as TST OP (1)) at a predetermined timing prior to sending the transfer end signal. ) is sent. That is,
The signal T S T OP (2) is sent out in response to the last data transfer.

It is sent out at an earlier timing than the signal T S T OP (1). This is made possible by foretelling the end of transfer of all data in the primary data transfer using the transfer end preparation signal PRESTOP.

As described above, the end of the transfer is announced in advance, so there is no need to secure the timing for sending one transfer end signal T S T OP (2) for each data transfer.

Therefore, it is possible to speed up data transfer each time.
I) MA transfer can be sped up.

〔Example〕

FIG. 1 will be further explained.

The data processing device 10 employs DMA transfer as one of its input/output control methods. Therefore, data transfer between the memo IJ 2 and the input/output devices 4-1 and 4-2 is as follows.
It is executed by the DMAC 5 without the intervention of the CPU (central processing unit) 1. That is.

DMA transfer data is directly exchanged between the memory 2 and the input/output device.

Here, memory 2 is the main memory used by cput. The DMAC 5 may be something like a CHC (channel controller) or an SPU (system processing unit); the input/output devices 4-1 and 4-2 are DA
This includes those that operate at relatively high speeds, such as SDs, and those that operate at relatively low speeds, such as printing devices.

The data processing device 10 has an interface i f (1)
Adopt. Therefore, as described above, DMAC5 is.

Sends signal Sig(1) for interface 1f(1). Moreover, the input/output devices 4-1 and 4-2.

Prior to this, a predetermined signal is sent out.

FIG. 2 shows this interface 1f(1).

Signal Sig(1) configuring interface if[1]
is the signal DREQ(1), consisting of the signals DREQ(1), DACK(1) and TSTOP(1).
is a data request signal, which is a signal requesting DMA transfer of data. Signal DREQ(1) corresponds one-to-one with each input/output device 4-1 and 4-2, and requests transfer at its low level. That is, each input/output device 4-1 and 4-2 sends its own signal DREQ(1) to the DMAC.
5 to request DMA transfer. Signal DACK (
1) is a data acknowledge signal.

This is a response signal indicating that the signal DREQ(1) has been received, and is a signal instructing data transfer.

The signal D ACK (1) also corresponds one-to-one to each input/output device 4-1 and 4-2, and indicates a response at its high level. 1
) is sent to the input/output device 4-1 or 4-2 that sent it.

The signal T S T OP (1) is a transfer end signal, and is a signal indicating that it is the last data transfer. Signal T S T OP (1) is the last signal of signal DACK (1).

That is, the data is sent from the DMAC 5 to the input/output device 4-1 or 4-2 approximately in synchronization with the last data transfer.

on the data bus according to signal DACK(1).

Data is sent out at the timing shown (substantially in synchronization with signal DACK(1)). Note that the timing is slightly different between the case of transfer (load) from the memory 2 to the input/output device 4-1 or 4-2 and the case of the reverse (store).

On the other hand, in the extended portion 20, in addition to the interface 1f(1), at least an interface i f (2) different from this is employed. That is.

The extended portion 20 includes an input/output device 7 that uses interface 1f(1) and an input/output device 6 that uses interface 1f(2).

FIG. 3 shows this ink face i f (2).

Signal S i constituting ink face i r (2)
g (2) is the signal DREQ (2), DACK (2),
The signal DREQ(2) consists of TSTART(2) and TSTOP(2).

This is a similar signal corresponding to signal DREQ(1). Signal DACK(2) corresponds to signal DACK(1), but is not a data transfer instruction signal but signal DREQ(2).
This is the response signal for Signal T S T A RT
(2) is a signal that serves as a data transfer instruction for signal DACK(1). Signal T S T A RT (2
) instructs each input/output device (6) to transfer data at a high level. Therefore, the data is signal D ACK (2
)not.

It is transferred substantially in synchronization with the signal TSTART(2). The signal TSTOP (2) corresponds to the signal T S T OP (1), but its transmission timing is different from this. That is.

The signal T S T OP (2) is the signal D ACK
(2) Sampled at the trailing edge. Therefore, the signal T
S T OP (2) is.

It is sent at an earlier timing than the last signal of signal TSTART(2), that is, the last data transfer.

On the data bus there is a signal T S T A RT (2)
Accordingly, data is sent out at the illustrated timing that is approximately synchronized with this. Note that the difference between loading and storing is the same as in FIG. 2 described above.

In this interface 1f(2), the signal DREQ
(2) is sent by the input/output device 6; other signals are.

Originally, D supports ink face i f (2)
This is sent by the MAC.

The settings of the expansion part 20 are such that the input/output devices 6 and 7 to be added are connected to the DM on the side to be expanded via the (conversion) adapter 5.
This is done by connecting to AC5. Since there is an input/output device 6 that adopts interface 1f(2),
A conversion adapter 5 having a conversion function is used as the adapter.

The conversion adapter 5 converts the interface i f (1) into the interface i f (2). in particular,
The conversion adapter 5 sends and receives signals to and from the input/output device 6 according to the interface 1f(2).

On the other hand, interface 1f (1) with DMAC5
Each signal is sent and received according to the following. The transmission and reception of this signal is
It is started using the signal DREQ (2) of the interface i f (2) as a trigger.

In this conversion, the transfer end preparation signal PRESTOP is used. If there is no signal PRESTOP, the ink face i f (2) side will move D at high speed as shown in FIG.
It becomes impossible to perform MA transfer (details will be explained later)
, and 9 As a result, the interface 1f(1) side cannot perform DMA transfer at high speed as shown in FIG. That is, DMA transfer will be delayed due to conversion.

Conversion adapter 5 connects D between memory 2 and input/output device 7.
When performing MA transfer, the signal for the interface i f (1) sent by the DMAC 5 is supplied as is to the input/output device 7. Also, the signal D sent out by the input/output device 7
Send REQ(1) as is to DMAC5. That is, in this case, the conversion adapter 5 is.

Pass each signal through without converting it. On the contrary,
When performing DMA transfer between the memory 2 and the input/output device 6, the conversion adapter 5 converts the signal for the interface 1f (1) and inputs the signal for the interface i f (2). It is supplied to the output device 6.

Further, the signal DREQ(2) sent from the input/output interior W6 is converted and sent to the DMAC 5 as a signal DREQ(1).

The above processing is possible because the signals DREQ (1) and (2) correspond to each input/output device 6 and 7 on a one-to-one basis.

In preparation for such expansion, the DMAC 5 sends out a transfer end preparation signal PRESTOP at a predetermined timing. This signal PRESTOP 1 does not require any special time to send, and is sent out approximately in synchronization with the signal DACK(1), so there is no delay in DMA transfer due to this sending.

This signal PRESTOP is the interface 1f(1)
Input/output devices 4-1 and 4-
2 is not supplied. On the other hand, the conversion adapter 5 is supplied regardless of the presence or absence of the input/output device 6. As a result, expansion is not limited by differences in interfaces.

FIG. 4 is a diagram showing ink face conversion.

That is, for example, when data is loaded from the memory 2 to the input/output device 6 by DMA transfer.

Interface 1f (1) using signal PRESTOP
This shows the conversion from interface 1f (21) to interface 1f (21).

For comparison, FIG. 5 shows the conversion in the absence of the signal PRESTOP.

In FIG. 4, input/output device 6 sends signal DREQ(2) to conversion adapter 5. In FIG.

In response, the conversion adapter 5 sends the signal DACK(2) of the interface i f (2) to the input/output device 6.
) and TSTART(2). That is, the conversion adapter 5 functions like a DMAC that supports the interface i f (2). Note that this interface i f (2) is, as a result, similar to the one shown in FIG. On the other hand, the conversion adapter 5 sends the signal DREQ(2) formed from the signal DREQ(2) to the DMAC5.
1) is sent.

In response to this, the DMAC 5 sends a signal DACK(1) of the ink face 1f(1) to the conversion adapter 5. Note that this interface i f (1) is
The result is similar to that shown in FIG.

As described above, data is sent from the memory 2 onto the data bus by memory control in synchronization with the signal DACK (1), and is loaded into the input/output device 6 via the conversion adapter 5 in synchronization with the signal TSTART (2). .

DMAC5 synchronizes with the data transfer immediately before the last data transfer or the corresponding signal DACK(+).

A signal PRESTOP is sent to the conversion adapter 5.

In the last data transfer cycle, the conversion adapter 5
has received the signal PRESTOP.

without waiting for the signal T S T OP (1) from DMAC5.

A signal TSTOP(2) is sent to the input/output device 6. This transmission converts the signal T S T OP (2) into the signal D
This is done in such a way as to match the sampling timing at the trailing edge of ACK(2). This timing can be known in advance. As a result, the signal T S T OP (
2) is sent out t earlier than the corresponding signal T S T OP (1).

Thereafter, the DMAC 5 sends the signal T S T OP (1) to the conversion adapter 5 . This signal T S T OP
(1) is.

Although it is not necessary for the entry/exit interior W6, it is necessary for the input/output device 7.

Here, for comparison, the fifth
The diagram will be explained.

Looking at the last data transfer cycle, the signal TSTOP
(2) is formed from the signal T S T OP (1), so it always lags behind it and cannot precede it.

Further, the signal T S T OP (2) is the signal DACK
Since it is sampled at the trailing edge of (2), the signal DACK(2) must be sent out up to this point. Since the transmission period of signal DREQ(1) cannot be shortened, signal D
The sending period of REQ(2) becomes long. That is.

At the interface i f (2), tl in FIG.
t4 in FIG. 5 is longer than that shown in FIG. This is equivalent to t in FIG. 5 being longer than t2 in FIG. 4 at the interface i f (1). in this way,
In FIG. 5, the time for each data transfer increases, ie, for each data transfer.

Signal T S T OP (2) It is not possible to increase the speed because it is necessary to secure the timing of sending.

On the other hand, in FIG. 4, the signal PRESTOP causes 1
It can be known in advance that the signal TST○P (1) will be sent out in synchronization with the next data transfer.

Therefore, the signal T S T OP (2) is the signal T S
It is possible to precede T OP (1). Therefore, in order to match the trailing edge of the last signal DACK(2), the signal TST○P(2) is sent out regardless of the signal TSTOP(1) (as a result, it precedes by t).

According to the above.

The timing of sending the signal TSTOP (2) is the signal PRES.
It is only necessary to secure it when transferring data after receiving the TOP.

Furthermore, since this transmission can precede the signal T S T OP (1), it can overlap with the transmission period of the signal DREQ (1). Therefore, L+ and t4 can be shortened, and DM
A transfer speed can be increased.

Note that this speed-up is particularly important for the speed increase from the memory 2 to the input/output device 6.
This is effective when loading data to a file.

〔Effect of the invention〕

As explained above, according to the present invention, in the DMA control process, by sending a transfer end preparation signal in the data transfer immediately before the last data transfer, different DM
DMA transfer can be performed at high speed even with input/output devices that employ the A interface, and there is no need to consider restrictions due to differences in DMA interfaces when expanding the system.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention. FIG. 2 is a diagram showing the interface 1f(1). FIG. 3 is a diagram showing the ink face t f (2). FIG. 4 is a diagram showing ink face conversion. FIG. 5 is a diagram showing conversion when there is no signal PRESTC)P. 1 is CPU, 2 is memory, 3 is DMAC, 4 (4-1,
4-2) is an input/output device, 5 is a conversion adapter, 6 and 7 are input/output devices, 10 is a data processing device before expansion, and 20 is an expansion part. Patent applicant Pfn Co., Ltd.

Claims (2)

[Claims] (1) A data processing device comprising a data processing device (10) that employs a first DMA interface and an extension section (20) that employs at least a second DMA interface, the data processing device comprising: DMA control means (3) for sending out a predetermined signal for the interface; and conversion means (5) for converting the signal for the first DMA interface into a signal for the second DMA interface. The DMA control means (3) sends out a transfer end preparation signal in response to the data transfer immediately before sending out the transfer end signal corresponding to the last data transfer, and the converting means (5) A DMA control processing method characterized in that upon receiving the transfer end preparation signal, a signal corresponding to the transfer end signal is sent out at a predetermined timing prior to sending out the transfer end signal. (2) The extended portion (20) is connected to the first and second D
first and second input/output devices (7, 6) employing an MA interface, the conversion means (5) transmitting the DMA control means (3) ) is supplied as is for the first DMA interface, and the second DMA interface converted by the converting means (5) is supplied to the second input/output device (6). 2. The DMA control processing system according to claim 1, wherein a signal for a DMA interface is supplied.