JPH04170036A - Manufacture of anisotropic conductive film - Google Patents
Manufacture of anisotropic conductive filmInfo
- Publication number
- JPH04170036A JPH04170036A JP29755590A JP29755590A JPH04170036A JP H04170036 A JPH04170036 A JP H04170036A JP 29755590 A JP29755590 A JP 29755590A JP 29755590 A JP29755590 A JP 29755590A JP H04170036 A JPH04170036 A JP H04170036A
- Authority
- JP
- Japan
- Prior art keywords
- base material
- electrodeposition
- electrode
- forming
- insulating base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000004070 electrodeposition Methods 0.000 claims abstract description 49
- 239000000463 material Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 abstract description 9
- 238000005868 electrolysis reaction Methods 0.000 abstract description 4
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 238000010586 diagram Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- KERTUBUCQCSNJU-UHFFFAOYSA-L nickel(2+);disulfamate Chemical compound [Ni+2].NS([O-])(=O)=O.NS([O-])(=O)=O KERTUBUCQCSNJU-UHFFFAOYSA-L 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Non-Insulated Conductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、異方性導電膜の製造方法に係り、特にＬＳＩ
チップ等を回路基板等に信頼性良く実装することができ
る異方性導電膜の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an anisotropic conductive film, particularly for LSI
The present invention relates to a method of manufacturing an anisotropic conductive film that allows chips and the like to be reliably mounted on circuit boards and the like.
〔従来の技術］
近時、ＬＳＩ等を配線基板に実装する実装技術分野にお
いては、異方性導電膜がＬＳＩチップ等の実装に使用さ
れており、この異方性導電膜においては、接続ピッチの
微細化と接続の信頼性が一高度に要求されている。[Prior Art] Recently, in the field of mounting technology for mounting LSI chips and the like on wiring boards, anisotropic conductive films have been used for mounting LSI chips and the like. A high degree of miniaturization and connection reliability are required.
従来この種の異方性導電膜とその製造方法については、
特開昭６３−４０２１８号公報に報告されている。ここ
での異方性導電膜は、微細孔が厚さ方向に穿設されてい
る絶縁性基材の微細孔中に金属物質を充填させるととも
に、金属物質は絶縁性基材の両面にバンプ状の突出物を
形成し構成したものである。Regarding this type of anisotropic conductive film and its manufacturing method,
It is reported in Japanese Patent Application Laid-Open No. 63-40218. The anisotropic conductive film here is made by filling the micropores of an insulating base material in the thickness direction with a metal substance, and the metal substance is formed in the form of bumps on both sides of the insulating base material. It is constructed by forming a protrusion.
その異方性導電膜の製造方法は具体的には、絶縁性基材
の厚さ方向に微細孔を穿設し、金属種層を絶縁性基材の
少なくとも片面上及び絶縁性基材中の微細孔の孔壁に形
成し、絶縁性基材上に形成された金属種層を除去した後
、微細孔壁にのみ金属種層が付着されている絶縁性基材
を無電解メツキ浴中に浸すことにより金属種層を成長さ
せ微細孔を充填し、絶縁性基材表面にバンプ状の突出物
を形成するというものである。Specifically, the method for producing the anisotropic conductive film involves forming micropores in the thickness direction of an insulating base material, and applying a metal seed layer on at least one side of the insulating base material and inside the insulating base material. After removing the metal seed layer formed on the pore walls of the micropores and removing the metal seed layer formed on the insulating substrate, the insulating substrate with the metal seed layer attached only to the micropore walls is placed in an electroless plating bath. By dipping, a metal seed layer is grown to fill the micropores and form bump-like protrusions on the surface of the insulating base material.
また、その他の製造方法には、絶縁性基材の厚さ方向に
微細孔を穿設し、金属種層を絶縁性基材の少なくとも片
面上及び絶縁性基材中の微細孔の孔壁に形成し、絶縁性
基材上に形成された金属種層を除去し、微細孔壁にのみ
金属種層が付着されている絶縁性基材を無電解メツキ浴
中に浸すことにより金属種層牽成長させた後、金属種層
が所定厚さに到達後、絶縁性基材をハンダ浴中に浸すこ
とにより、微細孔内を充填し、絶縁性基材表面にバンプ
状の突出物を形成するというものがある。Other manufacturing methods include forming micropores in the thickness direction of an insulating base material, and applying a metal seed layer on at least one side of the insulating base material and on the wall of the micropores in the insulating base material. The metal seed layer formed on the insulating substrate is removed, and the insulating substrate with the metal seed layer adhered only to the micropore walls is immersed in an electroless plating bath to remove the metal seed layer. After the metal seed layer has grown to a predetermined thickness, the insulating base material is immersed in a solder bath to fill the micropores and form bump-like protrusions on the surface of the insulating base material. There is such a thing.
［発明が解決しようとする課題］
しかしながら、上記した従来の異方性導電膜の製造方法
では、異方性導電膜の導電部を絶縁性基社内に所定パタ
ーン状（必要な部分のみ）には形成せず略均−な分布で
形成していたため、特に電極部が凹状になっているＬＳ
Ｉチップを回路基板等に実装する際、位置合わせが必要
になる等ＬＳＩチップを信軌性良く実装し難いという問
題があった。[Problems to be Solved by the Invention] However, in the above-described conventional method for manufacturing an anisotropic conductive film, the conductive parts of the anisotropic conductive film are formed in a predetermined pattern (only necessary parts) within an insulating base. Because it was not formed and was formed with an approximately uniform distribution, the LS where the electrode part is concave in particular
When mounting an I chip on a circuit board or the like, there is a problem that alignment is required, making it difficult to mount the LSI chip with good reliability.
そこで、本発明は、複数の微細貫通孔が形成された絶縁
性基材片面に所定の貫通孔をマスクするようにマスクパ
ターンを形成するとともに、貫通孔が露出された開口部
を形成し、開口部を覆うように電析用電極を形成した後
、電析用電極を陰極とし、電析により電析用電極上の貫
通孔内に埋め込むように、かつ絶縁性基村上でバンプ状
に導電性部材を形成するようにしたため、必要な部分の
み所定パターン状のバンプ付導電部を形成することがで
き、位置合わせを不要とすることができ、電極部が凹状
になっているＬＳＩチップ等を回路基板等に信軌性良く
実装することができる異方性導電膜の製造方法を提供す
ることを目的としている。Therefore, in the present invention, a mask pattern is formed on one side of an insulating base material in which a plurality of fine through holes are formed so as to mask predetermined through holes, and an opening in which the through hole is exposed is formed. After forming an electrode for electrodeposition so as to cover the electrode, the electrode for electrodeposition is used as a cathode, and a conductive electrode is formed in a bump shape on the insulating base layer so as to be embedded in the through hole on the electrode for electrodeposition by electrodeposition. Since the conductive part with bumps can be formed in a predetermined pattern only in the necessary parts, there is no need for alignment. It is an object of the present invention to provide a method for manufacturing an anisotropic conductive film that can be mounted on a substrate or the like with good reliability.
本発明による異方性導電膜の製造方法は上記目的達成の
ため、絶縁性基材に複数の微細貫通孔を形成する工程と
、該絶縁性基材片面に所定の該貫通孔をマスクするよう
にマスクパターンを形成するとともに、該貫通孔が露出
された開口部を形成する工程と、該開口部を覆うように
電析用電極を形成する工程と、該電析用電極を陰極とし
、電析により該電析用電極上の該貫通孔内に埋め込むよ
うに、かつ該絶縁性基材上でバンプ状に導電性部材を形
成する工程と、該電析用電極及び該マスクパターンを除
去する工程と、を含むものである。In order to achieve the above object, the method for manufacturing an anisotropic conductive film according to the present invention includes a step of forming a plurality of fine through holes in an insulating base material, and a step of masking predetermined through holes on one side of the insulating base material. A step of forming a mask pattern on the surface and forming an opening in which the through hole is exposed, a step of forming an electrode for electrodeposition so as to cover the opening, and a step of forming an electrode for electrodeposition using the electrode for electrodeposition as a cathode. forming a conductive member in the form of a bump on the insulating base material so as to be embedded in the through-hole on the electrodeposition electrode by electrolysis; and removing the electrodeposition electrode and the mask pattern. It includes a process.
本発明による異方性導電膜の製造方法は上記目的達成の
ため、絶縁性基材に複数の微細貫通孔を形成する工程と
、該絶縁性基材片面に所定の該貫通孔をマスクするよう
にマスクパターンを形成するとともに、該貫通孔が露出
された開口部を形成する工程と、該開口部を覆うように
電析用電極を形成する工程と、該電析用電極を陰極とし
、電析により該電析用電極上の該貫通孔内を埋め込むよ
うに、かつ該絶縁性基材上でバンプ状に第１の導電性部
材を形成する工程と、該電析用電極を除去する工程と、
バンプ状に形成された該第１の導電性部材を陰極とし、
電析により該開口部内の該絶縁性基材上でハンプ状に第
２の導電性部材を形成する工程と、該マスクパターンを
除去する工程と、を含むものである。In order to achieve the above object, the method for manufacturing an anisotropic conductive film according to the present invention includes a step of forming a plurality of fine through holes in an insulating base material, and a step of masking predetermined through holes on one side of the insulating base material. A step of forming a mask pattern on the surface and forming an opening in which the through hole is exposed, a step of forming an electrode for electrodeposition so as to cover the opening, and a step of forming an electrode for electrodeposition using the electrode for electrodeposition as a cathode. a step of forming a first conductive member in a bump shape on the insulating base material so as to fill the through hole on the electrodeposition electrode by electrolysis; and a step of removing the electrodeposition electrode. and,
The first conductive member formed in a bump shape is used as a cathode,
The method includes the steps of forming a hump-shaped second conductive member on the insulating base material within the opening by electrodeposition, and removing the mask pattern.
以下、本発明を図面に基づいて説明する。Hereinafter, the present invention will be explained based on the drawings.
第１図は本発明に係る異方性導電膜の製造方法の一実施
例を説明する図である。第１図において、■はＡ２□０
３等からなる絶縁性基材、２は絶縁性基材１に形成され
た貫通孔、３はレジスト等からなるマスクパターン、４
はマスクパターン３に形成された開口部、５はＮｉ等か
らなる電析用電極、６はＮｉ等からなる導電性部材、７
は電極バッド８を有するＬＳＩチップ、９は電極パッド
８間に形成された５ｉ０２等からなるバッシヘーション
膜、１０は電極パッド１１が形成された回路基板である
。FIG. 1 is a diagram illustrating an embodiment of the method for manufacturing an anisotropic conductive film according to the present invention. In Figure 1, ■ is A2□0
2 is a through hole formed in the insulating base material 1; 3 is a mask pattern made of resist or the like; 4
is an opening formed in the mask pattern 3; 5 is an electrode for electrodeposition made of Ni or the like; 6 is a conductive member made of Ni or the like; 7
1 is an LSI chip having electrode pads 8, 9 is a bashing film made of 5i02 or the like formed between the electrode pads 8, and 10 is a circuit board on which electrode pads 11 are formed.
次に、その製造方法について説明する。Next, the manufacturing method will be explained.
まず、第１図（ａ）に示すように膜厚４５μｍ程度のＡ
Ｉ！、２０３絶縁性基材１にエツチング等により孔径０
．２μｍ程度の複数の微細貫通孔２を形成する。First, as shown in FIG. 1(a), a film with a thickness of about 45 μm is
I! , 203 Insulating base material 1 has a pore diameter of 0 by etching etc.
．． A plurality of fine through holes 2 of about 2 μm are formed.
次に、第１図（ｂ）に示すように、絶縁性基材１片面に
レジストを塗布した後、露光・現像により所定の貫通孔
２をマスクするようにレジストをバターニングしてマス
クパターン３を形成する。Next, as shown in FIG. 1(b), after applying a resist to one side of the insulating base material 1, the resist is patterned by exposure and development so as to mask the predetermined through holes 2, and a mask pattern 3 is formed. form.
この時、貫通孔２が露出された開口部４が形成される。At this time, an opening 4 in which the through hole 2 is exposed is formed.
次に、第１図（Ｃ）に示すように、スパッタリング、蒸
着等により開口部４を覆うようにＮｉを堆積して電析用
電極５を形成する。Next, as shown in FIG. 1C, Ni is deposited by sputtering, vapor deposition, etc. so as to cover the opening 4 to form an electrodeposition electrode 5.
次に、第１図（ｄ）に示すように、電析用電極５を陰極
とし、電析により電析用電極５上の貫通孔２内を埋め込
むように、かつ絶縁性基材１上でバンプ状にＮｉからな
る導電性部材６を形成する。Next, as shown in FIG. 1(d), the electrodeposition electrode 5 is used as a cathode, and the through hole 2 on the electrodeposition electrode 5 is filled by electrodeposition, and the electrode is placed on the insulating base material 1. A conductive member 6 made of Ni is formed in a bump shape.
ここでの電析条件は、スルファミン酸ニッケル浴、液温
５０°Ｃ１電流密度１．５Ａ／ｄｍ” 、電析時間６０
分である。なお、電流密度は０．５Ａ ／ｄｍ” 〜５
Ａ ／ｄｍ”の範囲内で貫通孔２内に良好な導電性部
材６を形成することができるが、電流密度を高くし過ぎ
ると、ガス発生等によりＡｌ１． Ｏ，絶縁性基材１に
割れが発生したり、鍍金不良が生じたりする等好ましく
ないので、これら不良が発生しないように電流密度は適
宜調節して行なう。The electrodeposition conditions here were: nickel sulfamate bath, liquid temperature 50°C, current density 1.5A/dm", electrodeposition time 60
It's a minute. In addition, the current density is 0.5A/dm" ~ 5
A good electrically conductive member 6 can be formed within the through hole 2 within the range of "A/dm", but if the current density is too high, the Al1. Since this is undesirable as it may cause the occurrence of oxidation or plating defects, the current density should be adjusted as appropriate to prevent these defects from occurring.
そして、電析用電極５及びマスクパターン３をエツチン
グ等により除去することにより、第１図（ｅ）に示すよ
うな異方性導電膜を得ることができる。Then, by removing the electrodeposition electrode 5 and the mask pattern 3 by etching or the like, an anisotropic conductive film as shown in FIG. 1(e) can be obtained.
なお、この異方性導電膜は、第２図に示すように、回路
基板１０上にＬＳＩチップ７をフェイスダウン実装する
場合等に好ましく用いることができる。Note that this anisotropic conductive film can be preferably used when mounting the LSI chip 7 face-down on the circuit board 10, as shown in FIG.
すなわち、上記実施例では、複数の微細貫通孔２が形成
された絶縁性基材１片面に所定の貫通孔２をマスクする
ようにマスクパターン３を形成するとともに、貫通孔２
が露出された開口部４を形成し、開口部４を覆うように
電析用電極５を形成した後、電析用電極５を陰極とし、
電析により電析用電極５上の該貫通孔２内に埋め込むよ
うに、かつ絶縁性基材ｌ上でハンプ状に導電性部材６を
形成するようにしたため、必要な部分のみ所定パターン
状のハンプ付導電部を形成することができる。このため
、第２図に示すように、電極バッド８が凹状になってい
るＬＳ＋チップ７を回路基板１０に信軌性良く実装する
ことができる。That is, in the above embodiment, a mask pattern 3 is formed on one side of an insulating base material 1 in which a plurality of fine through holes 2 are formed so as to mask predetermined through holes 2, and the through holes 2 are
After forming an exposed opening 4 and forming an electrodeposition electrode 5 to cover the opening 4, the electrodeposition electrode 5 is used as a cathode,
Since the conductive member 6 is embedded in the through hole 2 on the electrodeposition electrode 5 by electrodeposition and is formed in a hump shape on the insulating base material l, only the necessary portions are formed in a predetermined pattern. A conductive portion with a hump can be formed. Therefore, as shown in FIG. 2, the LS+ chip 7 having the concave electrode pads 8 can be mounted on the circuit board 10 with good reliability.
また、微細貫通孔２を有する絶縁性基材１に八！２０３
を用いているため、ＬＳＩ実装等において、放熱性を良
くすることができるとともに、密な微細貫通孔２を形成
できるので、接続ピッチの微細化を行うことができる。In addition, the insulating base material 1 having minute through holes 2 has eight! 203
Since this is used, heat dissipation can be improved in LSI packaging, etc., and dense fine through-holes 2 can be formed, so the connection pitch can be made finer.
更に１枚のマスクパターン３で所定パターン状の導電部
を有する異方性導電膜を形成できるため、導電部の表裏
の位置ずれがなく、微細ピッチで接続を行うことができ
る。Furthermore, since an anisotropic conductive film having a predetermined pattern of conductive parts can be formed using one mask pattern 3, there is no misalignment between the front and back sides of the conductive parts, and connections can be made at fine pitches.
なお、上記実施例では、絶縁性基材１片面でのみ導電性
部材６をバンプ状に形成する場合について説明したが、
本発明はこれに限定されるものではなく、第３図に示す
ように、絶縁性基材１両面で導電性部材６．１５をバン
プ状に形成する場合であってもよい。その製造方法は具
体的には、第３図（ａ）に示すように、上記実施例の場
合と同様、電析用電極５を陰極とし、電析により電析用
電極５上の貫通孔２内を埋め込むように、かつ絶縁性基
材１上でバンプ状にＮｉからなる導電性部材６を形成し
た後、第３図（ｂ）に示すように、電析用電極５をエツ
チング等により除去する（ここまでの工程は上記実施例
と同じ）。この時、開口部４内に導電性部材６及び絶縁
性基材１が露出される。そして、第３図（Ｃ）に示すよ
うに、バンプ状に形成された導電性部材６を陰極とし、
導電性部材６を形成した際と同様、電析により開口部４
内の絶縁性基材１上でバンプ状に導電性部材１５を形成
した後、マスクパターン３を除去することにより第３図
（ｄ）に示すような異方性導電膜を得ることができる。In addition, in the above embodiment, the case where the conductive member 6 is formed in a bump shape only on one side of the insulating base material 1 has been described.
The present invention is not limited to this, and as shown in FIG. 3, the conductive members 6.15 may be formed in a bump shape on both sides of the insulating base material 1. Specifically, as shown in FIG. 3(a), the electrodeposition electrode 5 is used as a cathode, and the through holes 2 on the electrodeposition electrode 5 are formed by electrodeposition, as shown in FIG. 3(a). After forming a conductive member 6 made of Ni in a bump shape on the insulating base material 1 so as to embed the inside of the electrode, the electrode 5 for electrodeposition is removed by etching or the like, as shown in FIG. 3(b). (The steps up to this point are the same as in the above example). At this time, the conductive member 6 and the insulating base material 1 are exposed within the opening 4. Then, as shown in FIG. 3(C), the conductive member 6 formed in a bump shape is used as a cathode,
Similar to when forming the conductive member 6, the opening 4 is formed by electrodeposition.
After forming the conductive member 15 in the shape of a bump on the insulating base material 1, the mask pattern 3 is removed to obtain an anisotropic conductive film as shown in FIG. 3(d).
なお、この異方性導電膜は、第４図に示すように、ＬＳ
Ｉチップ上にＬＳＩチップ７を実装する場合等に用いる
ことができる。Note that, as shown in FIG. 4, this anisotropic conductive film is
It can be used when mounting the LSI chip 7 on an I-chip.
この実施例では、上記実施例と同様の効果を得ることか
できる他、表裏導通部の位置ずれかない両面バンプ付き
の異方性導電膜が得られるため、ＬＳＩチップ７上への
ＬＳＩチップ７の実装等両面電極部が凹状になっていて
も信顧性良く実装することができる。In this example, in addition to obtaining the same effects as in the above example, an anisotropic conductive film with bumps on both sides without misalignment of the front and back conductive parts can be obtained, so that the LSI chip 7 can be placed on the LSI chip 7. Even when the double-sided electrode portion is concave, it can be mounted with good reliability.
本発明によれば、複数の微細貫通孔が形成された絶縁性
基材片面に所定の貫通孔をマスクするようにマスクパタ
ーンを形成するとともに、貫通孔が露出された開口部を
形成し、開口部を覆うように電析用電極を形成した後、
電析用電極を陰極とし、電析により電析用電極上の貫通
孔内に埋め込むように、かつ絶縁性基材上でバンプ状に
導電性性部材を形成するようにしたため、必要な部分の
み所定パターン状のバンプ付導電部を形成することがで
き、位置合わせを不要とすることができ、電極部が凹状
になっているＬＳＩチップ等を回路基板等に信顛性良く
実装することができるという効果がある。According to the present invention, a mask pattern is formed on one side of an insulating base material in which a plurality of fine through holes are formed so as to mask predetermined through holes, and an opening in which the through holes are exposed is formed. After forming electrodeposition electrodes to cover the
The electrodeposition electrode is used as a cathode, and the conductive member is embedded in the through hole on the electrodeposition by electrodeposition, and the conductive member is formed in the form of a bump on the insulating base material, so only the necessary parts can be used. It is possible to form conductive parts with bumps in a predetermined pattern, eliminating the need for alignment, and it is possible to reliably mount LSI chips, etc., with concave electrode parts, on circuit boards, etc. There is an effect.
第１図及び第２図は本発明に係る異方性導電膜の製造方
法の一実施例を説明する図であり、第１図は一実施例の
製造方法を説明する図、第２図は一実施例の異方性導電
膜の実装例を示す図、
第３図は他の実施例の製造方法を説明する図、第４図は
他の実施例の異方性導電膜の実装例を示す図である。
■・・・・・・絶縁性基材、
２・・・・・・貫通孔、
３・・・・・・マスクパターン、
４・・・・・・開口部、
５・・・・・・電析用電極、
６．１５・・・・・・導電性部材。1 and 2 are diagrams for explaining one embodiment of the method for manufacturing an anisotropic conductive film according to the present invention, FIG. 1 is a diagram for explaining the manufacturing method of one embodiment, and FIG. A diagram showing an example of mounting an anisotropic conductive film of one embodiment, FIG. 3 is a diagram explaining a manufacturing method of another embodiment, and FIG. 4 shows an example of mounting an anisotropic conductive film of another embodiment. FIG. ■...Insulating base material, 2...Through hole, 3...Mask pattern, 4...Opening, 5...Electric analysis electrode, 6.15... Conductive member.
Claims (2)
、 該絶縁性基材片面に所定の該貫通孔をマスクするように
マスクパターンを形成するとともに、該貫通孔が露出さ
れた開口部を形成する工程と、該開口部を覆うように電
析用電極を形成する工程と、 該電析用電極を陰極とし、電析により該電析用電極上の
該貫通孔内に埋め込むように、かつ該絶縁性基材上でバ
ンプ状に導電性部材を形成する工程と、 該電析用電極及び該マスクパターンを除去する工程と、
を含むことを特徴とする異方性導電膜の製造方法。(1) Forming a plurality of fine through holes in an insulating base material, forming a mask pattern on one side of the insulating base material to mask a predetermined through hole, and exposing the through hole. a step of forming an opening, a step of forming an electrodeposition electrode to cover the opening, and using the electrodeposition electrode as a cathode, embedding it in the through hole on the electrodeposition electrode by electrodeposition. a step of forming a conductive member in a bump shape on the insulating base material, and a step of removing the electrodeposition electrode and the mask pattern,
A method for producing an anisotropic conductive film, comprising:
、 該絶縁性基材片面に所定の該貫通孔をマスクするように
マスクパターンを形成するとともに、該貫通孔が露出さ
れた開口部を形成する工程と、該開口部を覆うように電
析用電極を形成する工程と、 該電析用電極を陰極とし、電析により該電析用電極上の
該貫通孔内を埋め込むように、かつ該絶縁性基材上でバ
ルプ状に第１の導電性部材を形成する工程と、 該電析用電極を除去する工程と、 バンプ状に形成された該第１の導電性部材を陰極とし、
電析により該開口部内の該絶縁性基材上でバンプ状に第
２の導電性部材を形成する工程と、 該マスクパターンを除去する工程と、を含むことを特徴
とする異方性導電膜の製造方法。(2) forming a plurality of fine through holes in an insulating base material, forming a mask pattern on one side of the insulating base material to mask a predetermined through hole, and exposing the through hole; a step of forming an opening, a step of forming an electrodeposition electrode to cover the opening, and using the electrodeposition electrode as a cathode, filling the through hole on the electrodeposition electrode by electrodeposition. a step of forming a first conductive member in a bump shape on the insulating base material, a step of removing the electrodeposition electrode, and a step of forming the first conductive member in a bump shape. is the cathode,
An anisotropic conductive film comprising: forming a second conductive member in the shape of a bump on the insulating base material within the opening by electrodeposition; and removing the mask pattern. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29755590A JPH04170036A (en) | 1990-11-01 | 1990-11-01 | Manufacture of anisotropic conductive film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29755590A JPH04170036A (en) | 1990-11-01 | 1990-11-01 | Manufacture of anisotropic conductive film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04170036A true JPH04170036A (en) | 1992-06-17 |
Family
ID=17848065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29755590A Pending JPH04170036A (en) | 1990-11-01 | 1990-11-01 | Manufacture of anisotropic conductive film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04170036A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0798772A1 (en) * | 1996-03-26 | 1997-10-01 | Commissariat A L'energie Atomique | Process for realizing a deposition on a detachable support, and realized deposition on a support |
| USRE37840E1 (en) * | 1994-11-21 | 2002-09-17 | International Business Machines Corporation | Method of preparing a printed circuit board |
| DE102004061853A1 (en) * | 2004-12-22 | 2006-03-02 | Infineon Technologies Ag | Combined support structure and manufacturing jig panel for integrated circuit with chip, jig panel and supporting circuit board |
| WO2009113486A1 (en) | 2008-03-14 | 2009-09-17 | 富士フイルム株式会社 | Probe guard |
-
1990
- 1990-11-01 JP JP29755590A patent/JPH04170036A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE37840E1 (en) * | 1994-11-21 | 2002-09-17 | International Business Machines Corporation | Method of preparing a printed circuit board |
| EP0798772A1 (en) * | 1996-03-26 | 1997-10-01 | Commissariat A L'energie Atomique | Process for realizing a deposition on a detachable support, and realized deposition on a support |
| FR2746678A1 (en) * | 1996-03-26 | 1997-10-03 | Commissariat Energie Atomique | METHOD FOR MAKING A DEPOSIT ON A REMOVABLE MEDIUM, AND DEPOSIT CARRIED OUT ON A MEDIUM |
| DE102004061853A1 (en) * | 2004-12-22 | 2006-03-02 | Infineon Technologies Ag | Combined support structure and manufacturing jig panel for integrated circuit with chip, jig panel and supporting circuit board |
| WO2009113486A1 (en) | 2008-03-14 | 2009-09-17 | 富士フイルム株式会社 | Probe guard |
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