USRE37840E1 - Method of preparing a printed circuit board - Google Patents

Method of preparing a printed circuit board Download PDF

Info

Publication number
USRE37840E1
USRE37840E1 US09/159,360 US15936098A USRE37840E US RE37840 E1 USRE37840 E1 US RE37840E1 US 15936098 A US15936098 A US 15936098A US RE37840 E USRE37840 E US RE37840E
Authority
US
United States
Prior art keywords
holes
printed circuit
circuit board
subcomposite
plated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US09/159,360
Inventor
Anilkumar C. Bhatt
Roy H. Magnuson
Voya R. Markovich
Konstantinos I. Papathomas
Douglas O. Powell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Technologies LLC
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US09/159,360 priority Critical patent/USRE37840E1/en
Application granted granted Critical
Publication of USRE37840E1 publication Critical patent/USRE37840E1/en
Assigned to TESSERA INTELLECTUAL PROPERTIES, INC. reassignment TESSERA INTELLECTUAL PROPERTIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to INVENSAS CORPORATION reassignment INVENSAS CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: TESSERA INTELLECTUAL PROPERTIES, INC.
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/092—Exposing inner circuit layers or metal planes at the walls of high aspect ratio holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

  • the printed circuit boards have high circuit and component density, including either or both of surface mount components or additional circuitry layers directly atop plated through holes.
  • the printed circuit boards of the invention are especially useful where the density of plated through holes required to service the I/O's of the surface mount devices is such that there is no surface area available for attachment pads interstitial to the plated through hole grid.
  • the printed circuit boards of the invention are useful with fine pitch Ball Grid Array (BGA) integrated circuit modules and flip chip attach integrated circuit chips.
  • BGA Ball Grid Array
  • the printed circuit boards are prepared by first laminating a subcomposite with exterior sheets. Then a first pattern of holes are drilled through the subcomposite for plated through holes. This is followed by plating over the exposed surfaces of the subcomposite and the plated through hole barrels to form plated through holes. Fill material is forced through the drilled exterior sheets and into the plated through hole to fill the plated through holes with plated through hole filler composition. The subcomposite is then drilled to form a second pattern of through holes that are to remain unfilled. The through holes of this second pattern are plated, and a desired circuit pattern of surface circuitization is formed.
  • the increased circuit and component density in the printed circuit boards makes the ability to locate either solder surface mount components or place additional circuitry layers directly above plated through holes highly desirable. This is especially the case when the density of the plated through holes required to service the I/O's of the surface mount components is such that there is no surface area available for attachment pads interstitial to the plated through hole grid.
  • soldering of these surface mount components to the surface pads, i.e., lands, of conventional plated through holes is highly undesirable. This is because the solder used for assembly tends to wick down into the plated through holes. The result is low volume, unreliable solder joints.
  • the printed circuit board is one having two types of plated through holes.
  • the first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component.
  • the second type of plated through holes terminate at or below the exterior surface of the printed circuit board and allow for further surface circuitization as well as surface mount attachment.
  • These plated through holes contain a fill composition, for example, an electrically or thermally conductive fill composition.
  • one or more plated through hole that terminate in a surface mount contact there is provided one or more plated through hole that terminate in a surface mount contact.
  • the plated through holes that terminate in a surface mount contact have a conductive cap bonded to the surface mount contact.
  • At least one of the plated through holes terminating at a layer of dielectric material; that is, extending to but not through the layer of dielectric material. This allows external circuitization on the dielectric that overlays the plated through hole.
  • the filler is a composition of an organic polymeric material, optionally with a particulate filler added thereto to modify the thermal or electrical conductivity or the coefficient of thermal expansion.
  • the filler composition may be a thermally or electrically conductive fill composition.
  • the filler composition is compounded to have a coefficient of thermal expansion matched to the coefficient of thermal expansion of the printed circuit board substrate.
  • the fill composition includes as components a resin, also referred to herein as a binder, and a particulate, conductive or non-conductive filler component.
  • FIG. 1 is a cutaway side elevation of a printed circuit board of the invention.
  • a printed circuit board having two types of plated through holes.
  • the first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component.
  • the second type of plated through holes are filled plated through holes. These filled plated through holes terminate below the exterior surface of the printed circuit board, for example, below or adjacent to pads or lands, or below external circuitization.
  • These plated through holes contain a fill composition, for example, a thermally and/or electrically conductive fill composition.
  • These filled plated through are adapted to receive a surface mount component having a contact such as controlled collapse chip connection contact, including a controlled collapse chip connection contact surrounded by an encapsulant.
  • the surface mount contacts are typically a plurality of surface mount contacts, and the plurality of surface mount contacts are adapted to receive area array contacts. Alternatively, the surface mount contact is adapted to receive a wire lead bond.
  • FIG. 1 A typical printed circuit board 1 of the invention is shown in FIG. 1 .
  • the printed circuit board 1 shown in FIG. 1 has a subcomposite 3 and a film redistribution layer 5 . Extending through the subcomposite 3 are plated through holes 7 a and 7 b. Each of the plated through holes 7 a and 7 b has plated barrels 9 . Plated through hole 7 a is unfilled, and is for insertion of a pin-in-through-hole component (not shown). Plated through hole 7 b is filled with fill composition 11 , and extends through the subcomposite 3 up to the optional film redistribution layer 5 , when present, where it terminates in a conductive copper cap 13 .
  • the subcomposite has external circuitization 21 , buried beneath the film redistribution layer 5 , as well as internal power and signal lines.
  • the optional film redistribution layer 5 when present, formed of a photoimagable dielectric has surface circuitization 31 , including pads 33 .
  • Pads 33 are for mounting surface mount devices, e.g., integrated circuit chips with solder balls 41 .
  • the plated through holes that terminate in a surface mount contact can have a conductive cap atop the plated through hole and bonded to the surface mount contact, as a land or a pad.
  • At least one of the plated through holes terminating at a layer of dielectric material. That is, the plated through hole extends to but not through the layer of dielectric. This allows external circuitization on the dielectric that overlays the plated through hole.
  • the filler in at least one of the second plurality of plated through holes may be a conductive filler.
  • the filler composition is compounded to have a coefficient of thermal expansion after cure more closely matched to the coefficient of thermal expansion of the printed circuit board substrate then that of the unfilled resin.
  • Typical cured organic substrate materials have a coefficient of thermal expansion of from about 10 ppm/degree C. to about 28 ppm/degree C.
  • the coefficient of thermal expansion of the cured fill composition for example, the cured conductive fill composition, can be from about 17 ppm/degree C. to about 45 ppm/degree C. and preferably from about 25 ppm/degree C. to about 40 ppm/degree C.
  • the fill composition including both the filler resin or binder, and the filler particles, when present, should be chemically compatible with the printed circuit board fabrication processes and chemistry, including plating and etching processes and chemistries.
  • the fill composition should also have good adhesion and plating properties.
  • the fluid properties of the compounded, but uncured, fill material that is the viscosity and surface tension, among other properties, should allow sufficient flow to fill and coat small, high aspect ratio plated through hole barrels.
  • One particularly desired property of the fill composition constituents is the property of minimal volumetric change on solidification.
  • thermosetting resins filled with suitable particulates or powders.
  • suitable particulates for example metallic particulates.
  • suitable particulates for example metallic particulates.
  • silver or copper particles are examples of suitable particulates.
  • the blended fill composition contains approximately 30 to 90 weight percent of a particulate, balance organics, as a catalyst and a binder, also referred to herein as a resin.
  • the binder or resin composition is either an epoxy composition, a cyanate composition, or combinations thereof.
  • the epoxy composition is comprised of epoxy resin, curing agent, particulate filler, and catalyst.
  • the epoxy resin is either a cycloaliphatic epoxy resin or an epoxy cresol novolac resin. Depending on the epoxy resin used additional components are also employed.
  • the particulate component of the blended filler composition when present in the composition, can be one or more of carbon powders, organics, and metallic powders, such as copper, silver, nickel, molybdenum, gold, palladium, platinum, aluminum powder and mixtures thereof, having an average particle size of 0.1 to 75 microns, preferably 0.5 microns to 25 microns, more preferably about 0.5 to about 10 microns.
  • Suitable copper powders are commercially available from Alcan Powders & Pigments or Metz Metallurgical Corporation.
  • electrically insulating powders such as aluminum oxide, 92% alumina, 96% alumina, aluminum nitride, silicon nitride, silicon carbide, beryllium oxide, boron nitride, silicas, silicates, and diamond powder may be added to the blend.
  • binder and “resin” mean the nonparticulate, nonsolvent, organic components of the fill composition.
  • An important feature of the invention is the process for selectively mass filling the plated through holes.
  • the fill composition is coated as a thin layer, for example from about 0.5 mil to about 6 mils thick, on a carrier film or foil. This thin layer is dried and/or partially cured to form an easy to handle, tack free carrier.
  • the composite, multilayer printed circuit board, with copper foil on its external surfaces is conventionally drilled with the pattern of plated through holes intended to be filled.
  • a masking film is also prepared with the same pattern as the plated through holes to be filled.
  • the drilled holes in the printed circuit board are conventionally activated and plated with metal.
  • the masking film is aligned with the printed circuit board, that is, the holes in the masking sheet are aligned with the drilled and activated plated through holes in the printed circuit board.
  • the coated carrier, coated with fill material, is placed over the printed circuit board and masking sheet.
  • the coated carrier, the masking film, and the printed circuit board are laminated in, for example, a vacuum laminating press.
  • the press cycle of the vacuum laminating press is activated, which results in air being removed from the stack of the coated carrier, the masking film, and the printed circuit board.
  • the heat causes the fill material to flow through the holes in the masking film or foil into the plated through holes under the force of the applied pressure.
  • the stack is then removed from the laminating press, and the mask and carrier sheets are peeled away. Additional processing is, however, required to make the printed circuit board ready for circuitization.
  • the plated through hole fill process has raised nubs of fill material at each of the plated through holes, and some of the fill material may have bled between the mask sheet and the printed circuit board.
  • the nubs and surface film of cured fill material must be removed before circuitization. This can be accomplished by surface abrasion, or by well known printed circuit board chemical hole clean processes which chemically remove cured epoxies.
  • the printed circuit board panel is overplated with a thin layer of metal, such as copper.
  • the copper overplate provides electrical conductivity for additive circuitization and solderability.
  • the printed circuit board panel, with filled, plated through holes can now be circuitized.
  • the through holes intended to be filled are prepared first, substantially as described above. Thereafter, the through holes not intended to be filled are drilled. This results in selectively filled through holes.
  • the drilling process is carried out after filling the plated through holes intended to be filled, and either before or after the nub and bleed removal processes. The processes used for overplating the filled plated through holes can then be used to also plate the barrels of the unfilled through holes.
  • a thin layer of plating is applied atop the unfilled plated through holes, for example, about 0.0001 to 0.0010 inch of Cu.
  • the resulting sub-composite is circuitized using known print and etch methods.
  • a photoimageable dielectric is applied atop the circuitized sub-composite.
  • the photoimageable dielectric is photoprocessed to form vias to the underlying subcomposite.
  • the vias are formed above filled through holes and also where connectivity is desired between the sub-composite circuitization and the circuitization to be formed on the surface of the photoimageable dielectric.
  • Blind vias may be formed above filled through holes and other circuit features on the subcomposite.
  • Photovias should be formed concentric to and larger than unfilled through holes. Photo vias may also be formed above filled through holes where this is desired as part of the circuitization.
  • the surface of the photoimagable dielectric can then be treated to improve the adhesion of the circuitry to be formed thereon.
  • the surface of the photoimagable dielectric is activated and circuitized. Circuitization can be accomplished by full panel plating and subtractive etching, pattern electroplating, or pattern electrolessplating. In all of these methods the barrels of the unfilled plated through holes, which had only a thin layer of metal plated on them previously, are again plated so that the combined thickness of the two plating steps is sufficient for plated through hole conductivity.
  • This example illustrates a method of preparing a printed circuit board having a film redistribution layer and selective filled plated through holes. The method includes the steps of:
  • a composition is prepared containing approximately 70 to 80 weight percent of Cu powder having a maximum particle size of 6 micrometers, and approximately 20 to 30 weight percent phenol cured cresol-novolac resin, with sufficient methyl ethyl ketone solvent to achieve a suitable viscosity for coating.
  • a tertiary amine catalyst is added to the composition.
  • the composition is then coated onto a 1 ounce/square foot Cu foil.
  • the coated Cu foil is heated to remove solvent and to provide a tack free surface with a dried coating thickness of about 0.002 to 0.006 inch.
  • a printed circuit board subcomposite is laminated with 0.5 ounce/square foot Cu foil on both sides, and vapor grit blasted to remove epoxy residue from the lamination process.
  • the laminated Cu foil is then thinned by etching to about 0.00025 inch. Holes for the plated through holes are drilled, and a sheet of polyimide is drilled with the same plated through hole pattern. Meanwhile, the drilled subcomposite is deburred and chemically hole cleaned to prepare the through hole barrels for plating.
  • the sub-composite is seeded with a palladium/tin colloidal suspension. This palladium/tin seed plating makes the exposed surfaces catalytic for electroless Cu plating. Copper is electrolessly plated over the exposed surfaces and in the plated through hole barrels to a thickness of about 0.001 to 0.0012 inch.
  • the drilled polyimide sheet is placed on the sub-composite and aligned with the plated through holes.
  • the sheet of epoxy-Cu coated foil is placed atop the sub-composite.
  • the resulting stack is placed in a vacuum laminating press, a vacuum pulled, and heat and pressure applied. The heat and pressure cause the coating composition of epoxy and Cu to soften and flow through the holes in the drilled polyimide into the plated through holes. Heating is continued to cause the epoxy in the through holes to cure.
  • the laminator is then cooled, the pressure released, and the filled sub-composite is removed from the laminator.
  • the surface thereof is mechanically abraded to remove nubs of the epoxy-Cu fill material from the tops of the filled plated through holes, as well as to remove any epoxy residues on the surface of the copper due to bleed between the polyimide mask and the sub-composite.
  • the subcomposite is drilled with the pattern of plated through holes that are to remain unfilled. This is followed by a mechanical deburring operation and a chemical hole cleaning operation to prepare the unfilled plated through hole barrels for plating.
  • the subcomposite is again seeded with a palladium/tin colloidal suspension, and electrolessly copper plated with an additional 0.0002 to 0.0003 inch of copper.
  • the subcomposite is pumice scrubbed, and a layer of photoresist is applied, exposed, and developed to define a desired pattern for subtractive surface circuitization of the subcomposite.
  • the exposed surface of the subcomposite is etched in cupric chloride to form the desired circuit pattern.
  • the thickness of the copper etched is about 0.0014 to 0.0018 inch, which facilitates etching of fine lines and spaces. Thereafter the photoresist is stripped.
  • the subcomposite is then processed through a sequence of chloriting steps to enhance adhesion of a photoimagable dielectric layer.
  • a dry film photoimagable, dielectric polymer about 0.0020 to 0.0040 inch thick, is applied and adhered to the one or both surfaces of the subcomposite. Adhesion can be by vacuum lamination.
  • This photoimagable dielectric is then exposed with the pattern of the desired vias between the subcomposite circuitry and the circuitry to be formed on the top surface of the dielectric. The via openings are developed, and the dielectric is exposed and heated to further cure the dielectric.
  • the surface of the cured, photoimaged dielectric may then be vapor blasted and subjected to a chemical hole clean process to enhance the adhesion of subsequent circuitization thereon.
  • the dielectric is seeded with colloidal palladium/tin, and a subsequent dry film photoresist layer is laminated thereto, over the palladium/tin seed layer.
  • the photoresist is then imaged with the image of the circuitization to be formed, and developed.
  • the seeded composite with imaged photoresist is placed in an electroless copper plating bath for a time sufficient to plate copper to a thickness of 0.0007 to 0.0010 inch. This results in the formation of a top surface circuitization layer and a blind via interconnection. Plating also occurs in unfilled plated through holes having access to the surface to a final barrel thickness of about 0.0010 to 0.0013 inch.
  • the photomask is chemically stripped, and the surface cleaned.
  • Composite circuitization is complete. Gold, or tin-lead features or solder masks can be applied to the circuitized composite with a film redistribution layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Disclosed is a printed circuit board and a method of preparing the printed circuit board. The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surfaces of the printed circuit board. These plated through holes contain a bill composition.

Description

This is a divisional of copending application Ser. No. 08/342,533 filed on Nov. 21, 1994, now U.S. Pat. No. 5,487,218.
FIELD OF THE INVENTION
This invention relates to printed circuit boards and methods of fabricating them. The printed circuit boards have high circuit and component density, including either or both of surface mount components or additional circuitry layers directly atop plated through holes. The printed circuit boards of the invention are especially useful where the density of plated through holes required to service the I/O's of the surface mount devices is such that there is no surface area available for attachment pads interstitial to the plated through hole grid. The printed circuit boards of the invention are useful with fine pitch Ball Grid Array (BGA) integrated circuit modules and flip chip attach integrated circuit chips.
The printed circuit boards are prepared by first laminating a subcomposite with exterior sheets. Then a first pattern of holes are drilled through the subcomposite for plated through holes. This is followed by plating over the exposed surfaces of the subcomposite and the plated through hole barrels to form plated through holes. Fill material is forced through the drilled exterior sheets and into the plated through hole to fill the plated through holes with plated through hole filler composition. The subcomposite is then drilled to form a second pattern of through holes that are to remain unfilled. The through holes of this second pattern are plated, and a desired circuit pattern of surface circuitization is formed.
BACKGROUND OF THE INVENTION
Increasing levels of integration of integrated circuit chips reduces the chip count of a functional circuit, while significantly increasing the I/O count of the individual integrated circuits making up the functional circuit. This drive for increased circuit and component density in the individual integrated circuit chips leads to a parallel drive for increased circuit and component density in the printed circuit boards carrying the chips and in the assemblies using them.
The increased circuit and component density in the printed circuit boards makes the ability to locate either solder surface mount components or place additional circuitry layers directly above plated through holes highly desirable. This is especially the case when the density of the plated through holes required to service the I/O's of the surface mount components is such that there is no surface area available for attachment pads interstitial to the plated through hole grid.
The problem is especially severe with fine pitch ball grid array components (BGA) and flip chip attach integrated circuits. Soldering of these surface mount components to the surface pads, i.e., lands, of conventional plated through holes is highly undesirable. This is because the solder used for assembly tends to wick down into the plated through holes. The result is low volume, unreliable solder joints.
One solution that has been proposed is filling the plated through holes. However, known methods of filling plated through holes of printed circuit boards have deficiencies. For example, they suffer from bleed of the resin component of the PTH fill material along the surface of the boards. This resin also bleeds into holes which are not to be filled. This leads to short circuits and to soldering defects during assembly.
OBJECTS OF THE INVENTION
It is a primary object of the invention to facilitate the connection of high I/O density integrated circuit chips to highly packed printed circuit boards and cards.
It is a further object of the invention to provide for high interconnection escape.
It is a still further object of the invention to provide a process to make high function density printed circuit boards having selectively filled through holes.
SUMMARY OF THE INVENTION
These and other objects of the invention are achieved by the printed circuit board of our invention. The printed circuit board is one having two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component. The second type of plated through holes terminate at or below the exterior surface of the printed circuit board and allow for further surface circuitization as well as surface mount attachment. These plated through holes contain a fill composition, for example, an electrically or thermally conductive fill composition.
According to a further embodiment of our invention there is provided one or more plated through hole that terminate in a surface mount contact. Typically the plated through holes that terminate in a surface mount contact have a conductive cap bonded to the surface mount contact.
According to a still further embodiment of our invention there is provided at least one of the plated through holes terminating at a layer of dielectric material; that is, extending to but not through the layer of dielectric material. This allows external circuitization on the dielectric that overlays the plated through hole.
According to our invention the filler is a composition of an organic polymeric material, optionally with a particulate filler added thereto to modify the thermal or electrical conductivity or the coefficient of thermal expansion. In at least one of the second plurality of plated through holes the filler composition may be a thermally or electrically conductive fill composition. The filler composition is compounded to have a coefficient of thermal expansion matched to the coefficient of thermal expansion of the printed circuit board substrate. The fill composition includes as components a resin, also referred to herein as a binder, and a particulate, conductive or non-conductive filler component.
THE FIGURES
The invention may be understood by reference to the FIGURE appended hereto.
FIG. 1 is a cutaway side elevation of a printed circuit board of the invention.
DETAILED DESCRIPTION OF THE INVENTION
According to our invention there is provided a printed circuit board having two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component. The second type of plated through holes are filled plated through holes. These filled plated through holes terminate below the exterior surface of the printed circuit board, for example, below or adjacent to pads or lands, or below external circuitization. These plated through holes contain a fill composition, for example, a thermally and/or electrically conductive fill composition. These filled plated through are adapted to receive a surface mount component having a contact such as controlled collapse chip connection contact, including a controlled collapse chip connection contact surrounded by an encapsulant. The surface mount contacts are typically a plurality of surface mount contacts, and the plurality of surface mount contacts are adapted to receive area array contacts. Alternatively, the surface mount contact is adapted to receive a wire lead bond.
A typical printed circuit board 1 of the invention is shown in FIG. 1. The printed circuit board 1 shown in FIG. 1 has a subcomposite 3 and a film redistribution layer 5. Extending through the subcomposite 3 are plated through holes 7a and 7b. Each of the plated through holes 7a and 7b has plated barrels 9. Plated through hole 7a is unfilled, and is for insertion of a pin-in-through-hole component (not shown). Plated through hole 7b is filled with fill composition 11, and extends through the subcomposite 3 up to the optional film redistribution layer 5, when present, where it terminates in a conductive copper cap 13. The subcomposite has external circuitization 21, buried beneath the film redistribution layer 5, as well as internal power and signal lines.
The optional film redistribution layer 5, when present, formed of a photoimagable dielectric has surface circuitization 31, including pads 33. Pads 33 are for mounting surface mount devices, e.g., integrated circuit chips with solder balls 41.
According to our invention there is provided one or more plated through holes that terminate in a surface mount contact, as plated through hole 7b in FIG. 1. Typically the plated through holes that terminate in a surface mount contact can have a conductive cap atop the plated through hole and bonded to the surface mount contact, as a land or a pad.
According to a still further embodiment of our invention there is provided at least one of the plated through holes terminating at a layer of dielectric material. That is, the plated through hole extends to but not through the layer of dielectric. This allows external circuitization on the dielectric that overlays the plated through hole.
According to our invention the filler in at least one of the second plurality of plated through holes may be a conductive filler. The filler composition is compounded to have a coefficient of thermal expansion after cure more closely matched to the coefficient of thermal expansion of the printed circuit board substrate then that of the unfilled resin. Typical cured organic substrate materials have a coefficient of thermal expansion of from about 10 ppm/degree C. to about 28 ppm/degree C. Thus the coefficient of thermal expansion of the cured fill composition, for example, the cured conductive fill composition, can be from about 17 ppm/degree C. to about 45 ppm/degree C. and preferably from about 25 ppm/degree C. to about 40 ppm/degree C.
Moreover, the fill composition, including both the filler resin or binder, and the filler particles, when present, should be chemically compatible with the printed circuit board fabrication processes and chemistry, including plating and etching processes and chemistries. The fill composition should also have good adhesion and plating properties. Additionally, the fluid properties of the compounded, but uncured, fill material, that is the viscosity and surface tension, among other properties, should allow sufficient flow to fill and coat small, high aspect ratio plated through hole barrels.
One particularly desired property of the fill composition constituents is the property of minimal volumetric change on solidification.
These and other desirable attributes and properties are attained in fill compositions that includes thermosetting resins filled with suitable particulates or powders. Especially useful resins are epoxy resins of the same type used to make epoxy/glass pre-pregs used for printed circuit board construction, and filled with suitable particulates, for example metallic particulates. Exemplary are silver or copper particles.
The blended fill composition contains approximately 30 to 90 weight percent of a particulate, balance organics, as a catalyst and a binder, also referred to herein as a resin. Specifically, the binder or resin composition is either an epoxy composition, a cyanate composition, or combinations thereof. The epoxy composition is comprised of epoxy resin, curing agent, particulate filler, and catalyst. The epoxy resin is either a cycloaliphatic epoxy resin or an epoxy cresol novolac resin. Depending on the epoxy resin used additional components are also employed.
The particulate component of the blended filler composition, when present in the composition, can be one or more of carbon powders, organics, and metallic powders, such as copper, silver, nickel, molybdenum, gold, palladium, platinum, aluminum powder and mixtures thereof, having an average particle size of 0.1 to 75 microns, preferably 0.5 microns to 25 microns, more preferably about 0.5 to about 10 microns. Suitable copper powders are commercially available from Alcan Powders & Pigments or Metz Metallurgical Corporation. Optionally, electrically insulating powders such as aluminum oxide, 92% alumina, 96% alumina, aluminum nitride, silicon nitride, silicon carbide, beryllium oxide, boron nitride, silicas, silicates, and diamond powder may be added to the blend.
As used herein “binder” and “resin” mean the nonparticulate, nonsolvent, organic components of the fill composition.
An important feature of the invention is the process for selectively mass filling the plated through holes. In this process the fill composition is coated as a thin layer, for example from about 0.5 mil to about 6 mils thick, on a carrier film or foil. This thin layer is dried and/or partially cured to form an easy to handle, tack free carrier.
Meanwhile, the composite, multilayer printed circuit board, with copper foil on its external surfaces is conventionally drilled with the pattern of plated through holes intended to be filled. A masking film is also prepared with the same pattern as the plated through holes to be filled. The drilled holes in the printed circuit board are conventionally activated and plated with metal. Thereafter, the masking film is aligned with the printed circuit board, that is, the holes in the masking sheet are aligned with the drilled and activated plated through holes in the printed circuit board.
The coated carrier, coated with fill material, is placed over the printed circuit board and masking sheet. The coated carrier, the masking film, and the printed circuit board are laminated in, for example, a vacuum laminating press. The press cycle of the vacuum laminating press is activated, which results in air being removed from the stack of the coated carrier, the masking film, and the printed circuit board. The heat causes the fill material to flow through the holes in the masking film or foil into the plated through holes under the force of the applied pressure.
The stack is then removed from the laminating press, and the mask and carrier sheets are peeled away. Additional processing is, however, required to make the printed circuit board ready for circuitization. For example, the plated through hole fill process has raised nubs of fill material at each of the plated through holes, and some of the fill material may have bled between the mask sheet and the printed circuit board. The nubs and surface film of cured fill material must be removed before circuitization. This can be accomplished by surface abrasion, or by well known printed circuit board chemical hole clean processes which chemically remove cured epoxies.
In order to facilitate electrical connection as well as the formation of a solder cap atop the filled plated through holes, the printed circuit board panel is overplated with a thin layer of metal, such as copper. The copper overplate provides electrical conductivity for additive circuitization and solderability. The printed circuit board panel, with filled, plated through holes can now be circuitized.
Where it is desired to have both filled plated through holes and unfilled plated through holes, the through holes intended to be filled are prepared first, substantially as described above. Thereafter, the through holes not intended to be filled are drilled. This results in selectively filled through holes. The drilling process is carried out after filling the plated through holes intended to be filled, and either before or after the nub and bleed removal processes. The processes used for overplating the filled plated through holes can then be used to also plate the barrels of the unfilled through holes.
Where it is desired to provide a film redistribution layer atop a circuitized printed circuit board, only a thin layer of plating is applied atop the unfilled plated through holes, for example, about 0.0001 to 0.0010 inch of Cu. The resulting sub-composite is circuitized using known print and etch methods. Thereafter a photoimageable dielectric is applied atop the circuitized sub-composite. The photoimageable dielectric is photoprocessed to form vias to the underlying subcomposite. The vias are formed above filled through holes and also where connectivity is desired between the sub-composite circuitization and the circuitization to be formed on the surface of the photoimageable dielectric. Blind vias may be formed above filled through holes and other circuit features on the subcomposite. Photovias should be formed concentric to and larger than unfilled through holes. Photo vias may also be formed above filled through holes where this is desired as part of the circuitization. The surface of the photoimagable dielectric can then be treated to improve the adhesion of the circuitry to be formed thereon. The surface of the photoimagable dielectric is activated and circuitized. Circuitization can be accomplished by full panel plating and subtractive etching, pattern electroplating, or pattern electrolessplating. In all of these methods the barrels of the unfilled plated through holes, which had only a thin layer of metal plated on them previously, are again plated so that the combined thickness of the two plating steps is sufficient for plated through hole conductivity.
EXAMPLE
This example illustrates a method of preparing a printed circuit board having a film redistribution layer and selective filled plated through holes. The method includes the steps of:
a. Laminating a subcomposite with exterior sheets.
b. Drilling a first pattern of holes through the subcomposite for plated through holes.
c. Plating over the exposed surfaces of the subcomposite and the plated through hole barrels.
d. Forcing fill material through the drilled exterior sheets and into the plated through hole to fill the plated through holes.
e. Drilling the subcomposite with a second pattern of through holes that are to remain unfilled;
f. Plating the second pattern of through holes.
g. This is followed by forming a desired circuit pattern of surface circuitization.
According to one embodiment of the invention a composition is prepared containing approximately 70 to 80 weight percent of Cu powder having a maximum particle size of 6 micrometers, and approximately 20 to 30 weight percent phenol cured cresol-novolac resin, with sufficient methyl ethyl ketone solvent to achieve a suitable viscosity for coating. A tertiary amine catalyst is added to the composition. The composition is then coated onto a 1 ounce/square foot Cu foil. The coated Cu foil is heated to remove solvent and to provide a tack free surface with a dried coating thickness of about 0.002 to 0.006 inch.
A printed circuit board subcomposite is laminated with 0.5 ounce/square foot Cu foil on both sides, and vapor grit blasted to remove epoxy residue from the lamination process. The laminated Cu foil is then thinned by etching to about 0.00025 inch. Holes for the plated through holes are drilled, and a sheet of polyimide is drilled with the same plated through hole pattern. Meanwhile, the drilled subcomposite is deburred and chemically hole cleaned to prepare the through hole barrels for plating. The sub-composite is seeded with a palladium/tin colloidal suspension. This palladium/tin seed plating makes the exposed surfaces catalytic for electroless Cu plating. Copper is electrolessly plated over the exposed surfaces and in the plated through hole barrels to a thickness of about 0.001 to 0.0012 inch.
After plating, the drilled polyimide sheet is placed on the sub-composite and aligned with the plated through holes. The sheet of epoxy-Cu coated foil is placed atop the sub-composite. The resulting stack is placed in a vacuum laminating press, a vacuum pulled, and heat and pressure applied. The heat and pressure cause the coating composition of epoxy and Cu to soften and flow through the holes in the drilled polyimide into the plated through holes. Heating is continued to cause the epoxy in the through holes to cure. The laminator is then cooled, the pressure released, and the filled sub-composite is removed from the laminator.
After removing the sub-composite, the surface thereof is mechanically abraded to remove nubs of the epoxy-Cu fill material from the tops of the filled plated through holes, as well as to remove any epoxy residues on the surface of the copper due to bleed between the polyimide mask and the sub-composite.
Next, the subcomposite is drilled with the pattern of plated through holes that are to remain unfilled. This is followed by a mechanical deburring operation and a chemical hole cleaning operation to prepare the unfilled plated through hole barrels for plating. The subcomposite is again seeded with a palladium/tin colloidal suspension, and electrolessly copper plated with an additional 0.0002 to 0.0003 inch of copper. The subcomposite is pumice scrubbed, and a layer of photoresist is applied, exposed, and developed to define a desired pattern for subtractive surface circuitization of the subcomposite.
The exposed surface of the subcomposite is etched in cupric chloride to form the desired circuit pattern. The thickness of the copper etched is about 0.0014 to 0.0018 inch, which facilitates etching of fine lines and spaces. Thereafter the photoresist is stripped.
The subcomposite is then processed through a sequence of chloriting steps to enhance adhesion of a photoimagable dielectric layer. After chloriting, a dry film photoimagable, dielectric polymer, about 0.0020 to 0.0040 inch thick, is applied and adhered to the one or both surfaces of the subcomposite. Adhesion can be by vacuum lamination. This photoimagable dielectric is then exposed with the pattern of the desired vias between the subcomposite circuitry and the circuitry to be formed on the top surface of the dielectric. The via openings are developed, and the dielectric is exposed and heated to further cure the dielectric.
The surface of the cured, photoimaged dielectric may then be vapor blasted and subjected to a chemical hole clean process to enhance the adhesion of subsequent circuitization thereon.
The dielectric is seeded with colloidal palladium/tin, and a subsequent dry film photoresist layer is laminated thereto, over the palladium/tin seed layer. The photoresist is then imaged with the image of the circuitization to be formed, and developed.
The seeded composite with imaged photoresist is placed in an electroless copper plating bath for a time sufficient to plate copper to a thickness of 0.0007 to 0.0010 inch. This results in the formation of a top surface circuitization layer and a blind via interconnection. Plating also occurs in unfilled plated through holes having access to the surface to a final barrel thickness of about 0.0010 to 0.0013 inch.
After additive circuitization, the photomask is chemically stripped, and the surface cleaned. Composite circuitization is complete. Gold, or tin-lead features or solder masks can be applied to the circuitized composite with a film redistribution layer.
While the invention has been described with respect to certain preferred embodiments and exemplifications, it is not intended to limit the scope of the invention thereby, but solely by the claims appended hereto.

Claims (23)

We claim:
1. A method of preparing a printed circuit board having a film redistribution layer and selective filled plated through holes comprising the steps of:
a. laminating a printed circuit board subcomposite with 0.5 ounce/square foot Cu foil on both sides thereof;
b. thinning the copper foil to about 0.00025 inch;
c. drilling a pattern of holes through the subcomposite for plated through holes, and drilling a sheet of polyimide with the same plated through hole pattern;
d. seeding the drilled subcomposite with a palladium/tin, colloidal suspension whereby to make the exposed surfaces catalytic for electroless Cu plating;
e. electrolessly plating copper over the exposed surfaces of the subcomposite and in the plated through hole barrels to a thickness of about 0.001 to 0.0012 inch;
f. positioning the drilled polyimide sheet on the subcomposite aligned with the plated through holes;
g. placing a sheet of foil coated with plated through hole filler composition atop the sub-composite to form a stack;
h. laminating the stack to cause the coating composition to soften and flow through the holes in the drilled polyimide into the plated through holes and thereafter cure;
i. abrading the surface thereof to remove nubs of the fill material from the tops of the filled plated through holes, and remove fill residues on the surface of the copper foil from bleed between the mask and the sub-composite;
j. drilling the subcomposite with the pattern of plated through holes that are to remain unfilled, deburring, and chemical hole cleaning the unfilled plated through hole barrels for plating;
k. seeding the subcomposite with a palladium/tin colloidal suspension, and electrolessly copper plating the seeded subcomposite with an additional 0.0002 to 0.0003 inch of copper;
l. applying a layer of photoresist to the subcomposite, and exposing and developing the layer of photoresist to define a desired pattern of surface circuitization;
m. etching the exposed surface of the subcomposite to form a desired circuit pattern;
n. stripping the photoresist;
o. applying a dry film photoimagable, dielectric polymer, to one or both surfaces of the subcomposite;
p. exposing the photoimagable dielectric with the pattern of the desired vias between the subcomposite circuitry and the circuitry to be formed on the top surface of the dielectric;
q. developing the pattern of via openings, and thereafter processing the dielectric to further cure the dielectric;
r. seeding the dielectric with a colloidal palladium/tin suspension;
s. laminating a subsequent dry film photoresist layer thereto, over the palladium/tin seed layer, imaging the photoresist with the image of the circuitization to be formed, and developing the imaged photoresist;
t. plating the subcomposite with copper to form a film redistribution layer thereon;
u. stripping the photomask from the circuitized composite.
2. A printed circuit board having first and second pluralities of electrically conductive through holes and a layer of dielectric material positioned on a surface of said printed circuit board, said layer of dielectric material including at least one surface mount contact, said first plurality of electrically conductive through holes extending through said layer of dielectric material on said surface of said printed circuit board for receipt of a pin-in-through-hole module or component, at least one of said second plurality of electrically conductive through holes terminating at, but not through, said layer of dielectric material on said surface of said printed circuit board and being substantially filled with a fill composition.
3. The printed circuit board of claim 2 wherein at least one of said second plurality of electrically conductive through holes terminates in said surface mount contact.
4. The printed circuit board of claim 3 wherein said surface mount contact is adapted to receive a flip chip attach contact.
5. The printed circuit board of claim 3 wherein said surface mount contact is adapted to receive a controlled collapse chip connection contact.
6. The printed circuit board of claim 3 wherein said surface mount contact is adapted to receive an area array contact.
7. The printed circuit board of claim 3 wherein said surface mount contact is adapted to receive a wire lead bond.
8. The printed circuit board of claim 3 wherein said surface mount contact is adapted to receive a surface mount component.
9. The printed circuit board of claim 8 wherein said surface mount component is adapted for being attached to said surface mount contact.
10. The printed circuit board of claim 9 wherein said surface mount contact and said surface mount component are substantially surrounded by an encapsulant.
11. The printed circuit board of claim 2 wherein at least one of said second plurality of electrically conductive through holes terminates in a conductive cap bonded to said surface mount contact.
12. The printed circuit board of claim 2 having external circuitization on said layer of dielectric material overlying said at least one of said second plurality of electrically conductive through holes which terminates at, but not through, said layer of dielectric material.
13. The printed circuit board of claim 12 wherein said external circuitization has a thickness of from about 0.0002 to about 0.0004 inches.
14. The printed circuit board of claim 2 wherein said fill composition has a coefficient of thermal expansion closely matched to the coefficient of thermal expansion of said printed circuit board.
15. The printed circuit board of claim 14 wherein said fill composition coefficient of thermal expansion is from about 17 to about 45 ppm/degree Celsius.
16. The printed circuit board of claim 2 wherein said fill composition in at least one of said second plurality of electrically conductive through holes is a conductive fill composition.
17. The printed circuit board of claim 16 wherein said conductive fill composition comprises a conductive powder and an organic resin.
18. The printed circuit board of claim 17 wherein said fill composition is an electrically conductive fill composition.
19. A method of preparing a printed circuit board comprising the steps of:
providing a subcomposite having first and second opposing surfaces;
providing a first pattern of through holes through said first and second opposing surfaces of said subcomposite;
applying a first electrically conductive layer over said first and second opposing surfaces of said subcomposite and in said first pattern of through holes;
applying a mask over said first electrically conductive layer, said mask having holes therein which align with respective ones of said through holes of said first pattern of through holes within said subcomposite;
forcing a quantity of fill material through said holes in said mask and into said first pattern of through holes in said subcomposite to substantially fill said through holes in said subcomposite with said fill material; and thereafter
removing said mask.
20. The method of claim 19 further including the steps of:
providing said subcomposite with a second pattern of through holes that are to remain unfilled;
applying a second electrically conductive layer on said first electrically conductive layer, the exposed ends of said filler material in said pattern of through holes and in said second pattern of through holes;
modifying said second electrically conductive layer and said first electrically conductive layer to form a predetermined circuit pattern, thereby exposing portions of said first and second opposing surfaces of said subcomposite.
21. The method of claim 20 further comprising the step of forming a film redistribution layer on said predetermined circuit pattern and on portions of said exposed first and second opposing surfaces of said subcomposite.
22. The method of claim 21 wherein the step of forming said film distribution layer comprises the steps of:
applying a photo-imageable dielectric layer on said predetermined circuit pattern and on portions of said exposed first and second opposing surfaces of said subcomposite;
forming at least one opening in said photo-imageable dielectric layer to expose a portion of said predetermined circuit pattern; and
applying a conductive layer on said photo imageable dielectric so as to connect said conductive layer to said exposed portion of said predetermined circuit pattern.
23. The method of claim 19 wherein the step of providing a subcomposite comprises providing a substrate having a metal foil on both sides thereof.
US09/159,360 1994-11-21 1998-09-23 Method of preparing a printed circuit board Expired - Lifetime USRE37840E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/159,360 USRE37840E1 (en) 1994-11-21 1998-09-23 Method of preparing a printed circuit board

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/342,533 US5487218A (en) 1994-11-21 1994-11-21 Method for making printed circuit boards with selectivity filled plated through holes
US08/463,344 US5557844A (en) 1994-11-21 1995-06-05 Method of preparing a printed circuit board
US09/159,360 USRE37840E1 (en) 1994-11-21 1998-09-23 Method of preparing a printed circuit board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08/463,344 Reissue US5557844A (en) 1994-11-21 1995-06-05 Method of preparing a printed circuit board

Publications (1)

Publication Number Publication Date
USRE37840E1 true USRE37840E1 (en) 2002-09-17

Family

ID=23342250

Family Applications (3)

Application Number Title Priority Date Filing Date
US08/342,533 Expired - Lifetime US5487218A (en) 1994-11-21 1994-11-21 Method for making printed circuit boards with selectivity filled plated through holes
US08/463,344 Ceased US5557844A (en) 1994-11-21 1995-06-05 Method of preparing a printed circuit board
US09/159,360 Expired - Lifetime USRE37840E1 (en) 1994-11-21 1998-09-23 Method of preparing a printed circuit board

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US08/342,533 Expired - Lifetime US5487218A (en) 1994-11-21 1994-11-21 Method for making printed circuit boards with selectivity filled plated through holes
US08/463,344 Ceased US5557844A (en) 1994-11-21 1995-06-05 Method of preparing a printed circuit board

Country Status (3)

Country Link
US (3) US5487218A (en)
EP (1) EP0713359A1 (en)
KR (1) KR100273933B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020139578A1 (en) * 2001-03-28 2002-10-03 International Business Machines Corporation Hyperbga buildup laminate
US20030112582A1 (en) * 2001-12-13 2003-06-19 Sanders Michael C. Redundant data and power infrastructure for modular server components in a rack
US20050098882A1 (en) * 2001-09-28 2005-05-12 Fujitsu Limited Multilayer wiring circuit board

Families Citing this family (222)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6210862B1 (en) 1989-03-03 2001-04-03 International Business Machines Corporation Composition for photoimaging
US5766670A (en) * 1993-11-17 1998-06-16 Ibm Via fill compositions for direct attach of devices and methods for applying same
US5834824A (en) 1994-02-08 1998-11-10 Prolinx Labs Corporation Use of conductive particles in a nonconductive body as an integrated circuit antifuse
US5813881A (en) 1994-02-08 1998-09-29 Prolinx Labs Corporation Programmable cable and cable adapter using fuses and antifuses
US5917229A (en) 1994-02-08 1999-06-29 Prolinx Labs Corporation Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect
NL9400424A (en) * 1994-03-17 1995-11-01 Jei Lee Corp Method and device for producing sheets for packaging products
US5962815A (en) 1995-01-18 1999-10-05 Prolinx Labs Corporation Antifuse interconnect between two conducting layers of a printed circuit board
JP3290041B2 (en) * 1995-02-17 2002-06-10 インターナショナル・ビジネス・マシーンズ・コーポレーション Multilayer printed circuit board, method for manufacturing multilayer printed circuit board
JPH08264956A (en) * 1995-03-23 1996-10-11 Internatl Business Mach Corp <Ibm> Electrical connecting structure
US5534356A (en) * 1995-04-26 1996-07-09 Olin Corporation Anodized aluminum substrate having increased breakdown voltage
US6195883B1 (en) 1998-03-25 2001-03-06 International Business Machines Corporation Full additive process with filled plated through holes
US6384344B1 (en) 1995-06-19 2002-05-07 Ibiden Co., Ltd Circuit board for mounting electronic parts
US5699613A (en) * 1995-09-25 1997-12-23 International Business Machines Corporation Fine dimension stacked vias for a multiple layer circuit board structure
US5906042A (en) 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
US5767575A (en) 1995-10-17 1998-06-16 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
KR100216839B1 (en) * 1996-04-01 1999-09-01 김규현 Solder ball land structure of bga semiconductor package
US5872338A (en) 1996-04-10 1999-02-16 Prolinx Labs Corporation Multilayer board having insulating isolation rings
US5809641A (en) 1996-04-25 1998-09-22 International Business Machines Corporation Method for printed circuit board repair
US5993945A (en) * 1996-05-30 1999-11-30 International Business Machines Corporation Process for high resolution photoimageable dielectric
US5753976A (en) * 1996-06-14 1998-05-19 Minnesota Mining And Manufacturing Company Multi-layer circuit having a via matrix interlayer connection
US5827386A (en) * 1996-06-14 1998-10-27 International Business Machines Corporation Method for forming a multi-layered circuitized substrate member
JP3050807B2 (en) * 1996-06-19 2000-06-12 イビデン株式会社 Multilayer printed wiring board
US5822856A (en) * 1996-06-28 1998-10-20 International Business Machines Corporation Manufacturing circuit board assemblies having filled vias
US6268016B1 (en) 1996-06-28 2001-07-31 International Business Machines Corporation Manufacturing computer systems with fine line circuitized substrates
JP3405131B2 (en) * 1996-07-16 2003-05-12 株式会社村田製作所 Electronic components
JP3050812B2 (en) * 1996-08-05 2000-06-12 イビデン株式会社 Multilayer printed wiring board
US6214525B1 (en) 1996-09-06 2001-04-10 International Business Machines Corp. Printed circuit board with circuitized cavity and methods of producing same
DE69637246T2 (en) 1996-09-12 2008-02-14 Ibiden Co., Ltd., Ogaki PCB FOR MOUNTING ELECTRONIC COMPONENTS
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
US5920123A (en) * 1997-01-24 1999-07-06 Micron Technology, Inc. Multichip module assembly having via contacts and method of making the same
US5798563A (en) * 1997-01-28 1998-08-25 International Business Machines Corporation Polytetrafluoroethylene thin film chip carrier
JPH1174651A (en) 1997-03-13 1999-03-16 Ibiden Co Ltd Printed wiring board and its manufacture
JP3173410B2 (en) * 1997-03-14 2001-06-04 松下電器産業株式会社 Package substrate and method of manufacturing the same
EP0865231A1 (en) * 1997-03-14 1998-09-16 Photo Print Electronic GmbH Method for producing printed circuit boards with through-platings
US6272745B1 (en) 1997-03-14 2001-08-14 Photo Print Electronics Gmbh Methods for the production of printed circuit boards with through-platings
US6323436B1 (en) * 1997-04-08 2001-11-27 International Business Machines Corporation High density printed wiring board possessing controlled coefficient of thermal expansion with thin film redistribution layer
US6022670A (en) * 1997-05-08 2000-02-08 International Business Machines Corporation Process for high resolution photoimageable dielectric
US6015520A (en) * 1997-05-15 2000-01-18 International Business Machines Corporation Method for filling holes in printed wiring boards
US6162997A (en) * 1997-06-03 2000-12-19 International Business Machines Corporation Circuit board with primary and secondary through holes
US6015955A (en) * 1997-06-20 2000-01-18 International Business Machines Corporation Reworkability solution for wirebound chips using high performance capacitor
DE19861009B4 (en) * 1997-08-28 2004-08-19 Mitsubishi Denki K.K. Packaged semiconductor device has a ball grid array substrate
JP4190602B2 (en) * 1997-08-28 2008-12-03 株式会社ルネサステクノロジ Semiconductor device
US6317333B1 (en) 1997-08-28 2001-11-13 Mitsubishi Denki Kabushiki Kaisha Package construction of semiconductor device
US6388202B1 (en) * 1997-10-06 2002-05-14 Motorola, Inc. Multi layer printed circuit board
US6005198A (en) * 1997-10-07 1999-12-21 Dimensional Circuits Corporation Wiring board constructions and methods of making same
US6052287A (en) * 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier
US6620731B1 (en) 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US6107109A (en) * 1997-12-18 2000-08-22 Micron Technology, Inc. Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate
US6833613B1 (en) * 1997-12-18 2004-12-21 Micron Technology, Inc. Stacked semiconductor package having laser machined contacts
TW421980B (en) * 1997-12-22 2001-02-11 Citizen Watch Co Ltd Electronic component device, its manufacturing process, and collective circuits
US6169664B1 (en) * 1998-01-05 2001-01-02 Texas Instruments Incorporated Selective performance enhancements for interconnect conducting paths
US6034427A (en) 1998-01-28 2000-03-07 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
US6680440B1 (en) 1998-02-23 2004-01-20 International Business Machines Corporation Circuitized structures produced by the methods of electroless plating
US6023029A (en) * 1998-03-19 2000-02-08 International Business Machines Corporation Use of blind vias for soldered interconnections between substrates and printed wiring boards
US6303881B1 (en) 1998-03-20 2001-10-16 Viasystems, Inc. Via connector and method of making same
US6598291B2 (en) 1998-03-20 2003-07-29 Viasystems, Inc. Via connector and method of making same
SG75841A1 (en) 1998-05-02 2000-10-24 Eriston Invest Pte Ltd Flip chip assembly with via interconnection
US6406939B1 (en) 1998-05-02 2002-06-18 Charles W. C. Lin Flip chip assembly with via interconnection
US6079100A (en) * 1998-05-12 2000-06-27 International Business Machines Corporation Method of making a printed circuit board having filled holes and fill member for use therewith
US6037096A (en) * 1998-05-26 2000-03-14 International Business Machines Corporation Film composition and method for a planar surface atop a plated through hole
US6009620A (en) * 1998-07-15 2000-01-04 International Business Machines Corporation Method of making a printed circuit board having filled holes
US6323435B1 (en) 1998-07-31 2001-11-27 Kulicke & Soffa Holdings, Inc. Low-impedance high-density deposited-on-laminate structures having reduced stress
US6090474A (en) * 1998-09-01 2000-07-18 International Business Machines Corporation Flowable compositions and use in filling vias and plated through-holes
US6066889A (en) * 1998-09-22 2000-05-23 International Business Machines Corporation Methods of selectively filling apertures
US6204456B1 (en) 1998-09-24 2001-03-20 International Business Machines Corporation Filling open through holes in a multilayer board
JP3206561B2 (en) * 1998-10-01 2001-09-10 日本電気株式会社 Multilayer wiring board
US6181219B1 (en) 1998-12-02 2001-01-30 Teradyne, Inc. Printed circuit board and method for fabricating such board
US6175087B1 (en) 1998-12-02 2001-01-16 International Business Machines Corporation Composite laminate circuit structure and method of forming the same
TW444236B (en) 1998-12-17 2001-07-01 Charles Wen Chyang Lin Bumpless flip chip assembly with strips and via-fill
SG82591A1 (en) * 1998-12-17 2001-08-21 Eriston Technologies Pte Ltd Bumpless flip chip assembly with solder via
SG78324A1 (en) 1998-12-17 2001-02-20 Eriston Technologies Pte Ltd Bumpless flip chip assembly with strips-in-via and plating
AU2855400A (en) * 1999-01-22 2000-08-07 Interworks Computer Products, Inc. System and method for interconnecting layers in a printed circuit board
US6252779B1 (en) 1999-01-25 2001-06-26 International Business Machines Corporation Ball grid array via structure
US6073344A (en) * 1999-01-28 2000-06-13 International Business Machines Corporation Laser segmentation of plated through-hole sidewalls to form multiple conductors
US6125531A (en) * 1999-03-01 2000-10-03 International Business Machines Corporation Method of making a printed circuit board having filled holes and a fill member for use therewith including reinforcement means
JP2000261147A (en) * 1999-03-10 2000-09-22 Shinko Electric Ind Co Ltd Multilayer wiring board and manufacture thereof
JP4442832B2 (en) * 1999-04-13 2010-03-31 イビデン株式会社 Multilayer printed wiring board
TWI239798B (en) 1999-05-28 2005-09-11 Toppan Printing Co Ltd Photo electric wiring substrate, mounted substrate, and the manufacture method of the photo electric wiring substrate
WO2000076281A1 (en) 1999-06-02 2000-12-14 Ibiden Co., Ltd. Multilayer printed wiring board and method of manufacturing multilayer printed wiring board
JP3287408B2 (en) * 1999-06-16 2002-06-04 日本電気株式会社 Semiconductor device and method of forming semiconductor substrate through conductor
US6492600B1 (en) 1999-06-28 2002-12-10 International Business Machines Corporation Laminate having plated microvia interconnects and method for forming the same
US6291779B1 (en) * 1999-06-30 2001-09-18 International Business Machines Corporation Fine pitch circuitization with filled plated through holes
US6188027B1 (en) * 1999-06-30 2001-02-13 International Business Machines Corporation Protection of a plated through hole from chemical attack
US6555762B2 (en) * 1999-07-01 2003-04-29 International Business Machines Corporation Electronic package having substrate with electrically conductive through holes filled with polymer and conductive composition
US6423470B1 (en) 1999-08-20 2002-07-23 3M Innovative Properties Company Printed circuit substrate with controlled placement covercoat layer
IT1313117B1 (en) * 1999-08-25 2002-06-17 Morton Int Inc VACUUM APPLICATION EQUIPMENT EQUIPPED WITH CONVEYING VEHICLES PROCEDURE FOR APPLYING A DRY FILM RESIST TO A PANEL OF
US6452117B2 (en) 1999-08-26 2002-09-17 International Business Machines Corporation Method for filling high aspect ratio via holes in electronic substrates and the resulting holes
US20080035370A1 (en) * 1999-08-27 2008-02-14 Lex Kosowsky Device applications for voltage switchable dielectric material having conductive or semi-conductive organic material
US7446030B2 (en) * 1999-08-27 2008-11-04 Shocking Technologies, Inc. Methods for fabricating current-carrying structures using voltage switchable dielectric materials
US20100044080A1 (en) * 1999-08-27 2010-02-25 Lex Kosowsky Metal Deposition
US7825491B2 (en) * 2005-11-22 2010-11-02 Shocking Technologies, Inc. Light-emitting device using voltage switchable dielectric material
US20100044079A1 (en) * 1999-08-27 2010-02-25 Lex Kosowsky Metal Deposition
US7695644B2 (en) * 1999-08-27 2010-04-13 Shocking Technologies, Inc. Device applications for voltage switchable dielectric material having high aspect ratio particles
AU6531600A (en) * 1999-08-27 2001-03-26 Lex Kosowsky Current carrying structure using voltage switchable dielectric material
DE60027141T2 (en) * 1999-10-26 2006-12-28 Ibiden Co., Ltd., Ogaki PRINTED MULTILAYER PLATE AND MANUFACTURING METHOD FOR PRINTED MULTILAYER PLATE
KR100760337B1 (en) * 1999-12-15 2007-09-20 롬 앤드 하스 일렉트로닉 머트어리얼즈, 엘.엘.씨 Seed layer repair method
US6485892B1 (en) 1999-12-17 2002-11-26 International Business Machines Corporation Method for masking a hole in a substrate during plating
JP3775970B2 (en) * 2000-03-27 2006-05-17 新光電気工業株式会社 Manufacturing method of electronic component mounting board
US6467160B1 (en) 2000-03-28 2002-10-22 International Business Machines Corporation Fine pitch circuitization with unfilled plated through holes
KR100333627B1 (en) * 2000-04-11 2002-04-22 구자홍 Multi layer PCB and making method the same
US6320137B1 (en) 2000-04-11 2001-11-20 3M Innovative Properties Company Flexible circuit with coverplate layer and overlapping protective layer
US6720502B1 (en) * 2000-05-15 2004-04-13 International Business Machine Corporation Integrated circuit structure
US6747862B1 (en) * 2000-07-17 2004-06-08 Alcatel System and method for providing high voltage withstand capability between pins of a high-density compliant pin connector
TW525417B (en) * 2000-08-11 2003-03-21 Ind Tech Res Inst Composite through hole structure
US6403460B1 (en) 2000-08-22 2002-06-11 Charles W. C. Lin Method of making a semiconductor chip assembly
US6350633B1 (en) 2000-08-22 2002-02-26 Charles W. C. Lin Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint
US6562657B1 (en) 2000-08-22 2003-05-13 Charles W. C. Lin Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint
US6436734B1 (en) 2000-08-22 2002-08-20 Charles W. C. Lin Method of making a support circuit for a semiconductor chip assembly
US6402970B1 (en) 2000-08-22 2002-06-11 Charles W. C. Lin Method of making a support circuit for a semiconductor chip assembly
US6660626B1 (en) 2000-08-22 2003-12-09 Charles W. C. Lin Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint
US6562709B1 (en) 2000-08-22 2003-05-13 Charles W. C. Lin Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint
US6551861B1 (en) 2000-08-22 2003-04-22 Charles W. C. Lin Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive
JP3546823B2 (en) * 2000-09-07 2004-07-28 インターナショナル・ビジネス・マシーンズ・コーポレーション Through-hole structure and printed circuit board including the through-hole structure
US6350386B1 (en) 2000-09-20 2002-02-26 Charles W. C. Lin Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly
US6350632B1 (en) 2000-09-20 2002-02-26 Charles W. C. Lin Semiconductor chip assembly with ball bond connection joint
US6511865B1 (en) 2000-09-20 2003-01-28 Charles W. C. Lin Method for forming a ball bond connection joint on a conductive trace and conductive pad in a semiconductor chip assembly
US6544813B1 (en) 2000-10-02 2003-04-08 Charles W. C. Lin Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment
US6448108B1 (en) 2000-10-02 2002-09-10 Charles W. C. Lin Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment
US6908788B1 (en) 2000-10-13 2005-06-21 Bridge Semiconductor Corporation Method of connecting a conductive trace to a semiconductor chip using a metal base
US7262082B1 (en) 2000-10-13 2007-08-28 Bridge Semiconductor Corporation Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture
US7075186B1 (en) 2000-10-13 2006-07-11 Bridge Semiconductor Corporation Semiconductor chip assembly with interlocked contact terminal
US7094676B1 (en) 2000-10-13 2006-08-22 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal pillar
US6876072B1 (en) 2000-10-13 2005-04-05 Bridge Semiconductor Corporation Semiconductor chip assembly with chip in substrate cavity
US6576493B1 (en) 2000-10-13 2003-06-10 Bridge Semiconductor Corporation Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps
US7264991B1 (en) 2000-10-13 2007-09-04 Bridge Semiconductor Corporation Method of connecting a conductive trace to a semiconductor chip using conductive adhesive
US6537851B1 (en) 2000-10-13 2003-03-25 Bridge Semiconductor Corporation Method of connecting a bumped compliant conductive trace to a semiconductor chip
US6673710B1 (en) 2000-10-13 2004-01-06 Bridge Semiconductor Corporation Method of connecting a conductive trace and an insulative base to a semiconductor chip
US6440835B1 (en) 2000-10-13 2002-08-27 Charles W. C. Lin Method of connecting a conductive trace to a semiconductor chip
US6740576B1 (en) 2000-10-13 2004-05-25 Bridge Semiconductor Corporation Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly
US6548393B1 (en) 2000-10-13 2003-04-15 Charles W. C. Lin Semiconductor chip assembly with hardened connection joint
US7132741B1 (en) 2000-10-13 2006-11-07 Bridge Semiconductor Corporation Semiconductor chip assembly with carved bumped terminal
US7319265B1 (en) 2000-10-13 2008-01-15 Bridge Semiconductor Corporation Semiconductor chip assembly with precision-formed metal pillar
US7009297B1 (en) 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
US7129113B1 (en) 2000-10-13 2006-10-31 Bridge Semiconductor Corporation Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture
US6492252B1 (en) 2000-10-13 2002-12-10 Bridge Semiconductor Corporation Method of connecting a bumped conductive trace to a semiconductor chip
US6984576B1 (en) 2000-10-13 2006-01-10 Bridge Semiconductor Corporation Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip
US7071089B1 (en) 2000-10-13 2006-07-04 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with a carved bumped terminal
US6872591B1 (en) 2000-10-13 2005-03-29 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with a conductive trace and a substrate
US7129575B1 (en) 2000-10-13 2006-10-31 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped metal pillar
US6949408B1 (en) 2000-10-13 2005-09-27 Bridge Semiconductor Corporation Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps
US7414319B2 (en) * 2000-10-13 2008-08-19 Bridge Semiconductor Corporation Semiconductor chip assembly with metal containment wall and solder terminal
US6576539B1 (en) 2000-10-13 2003-06-10 Charles W.C. Lin Semiconductor chip assembly with interlocked conductive trace
US6699780B1 (en) 2000-10-13 2004-03-02 Bridge Semiconductor Corporation Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching
US6667229B1 (en) 2000-10-13 2003-12-23 Bridge Semiconductor Corporation Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip
US7190080B1 (en) 2000-10-13 2007-03-13 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal pillar
AU2002220022A1 (en) * 2000-11-06 2002-05-15 Mcnc Method of connecting conductors on different levels of a microelectronic device and associated apparatus
US6444489B1 (en) 2000-12-15 2002-09-03 Charles W. C. Lin Semiconductor chip assembly with bumped molded substrate
US6429527B1 (en) 2001-01-17 2002-08-06 International Business Corporation Method and article for filling apertures in a high performance electronic substrate
US6653170B1 (en) 2001-02-06 2003-11-25 Charles W. C. Lin Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit
US6630743B2 (en) * 2001-02-27 2003-10-07 International Business Machines Corporation Copper plated PTH barrels and methods for fabricating
US6455355B1 (en) * 2001-04-10 2002-09-24 Siliconware Precision Industries, Co., Ltd. Method of mounting an exposed-pad type of semiconductor device over a printed circuit board
JP4034046B2 (en) * 2001-06-07 2008-01-16 日本碍子株式会社 Multi-layer board having high-precision through hole and circuit board
US6810583B2 (en) 2001-08-07 2004-11-02 International Business Machines Corporation Coupling of conductive vias to complex power-signal substructures
US20030034175A1 (en) * 2001-08-20 2003-02-20 Honeywell Advanced Circuits, Inc. Configurations and methods for improved copper distribution uniformity in printed wiring boards
US20030080174A1 (en) * 2001-10-31 2003-05-01 Kennedy Craig M. Header for surface mount between parallel circuit boards
JP4062907B2 (en) * 2001-11-12 2008-03-19 松下電器産業株式会社 Circuit board and manufacturing method thereof
US6593224B1 (en) 2002-03-05 2003-07-15 Bridge Semiconductor Corporation Method of manufacturing a multilayer interconnect substrate
US7358607B2 (en) * 2002-03-06 2008-04-15 Intel Corporation Substrates and systems to minimize signal path discontinuities
US6908845B2 (en) * 2002-03-28 2005-06-21 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US20030183943A1 (en) * 2002-03-28 2003-10-02 Swan Johanna M. Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6848177B2 (en) 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6617690B1 (en) * 2002-08-14 2003-09-09 Ibm Corporation Interconnect structures containing stress adjustment cap layer
JP4046026B2 (en) * 2003-06-27 2008-02-13 株式会社日立製作所 Semiconductor device
US7205649B2 (en) * 2003-06-30 2007-04-17 Intel Corporation Ball grid array copper balancing
US7583513B2 (en) * 2003-09-23 2009-09-01 Intel Corporation Apparatus for providing an integrated printed circuit board registration coupon
US7993983B1 (en) 2003-11-17 2011-08-09 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with chip and encapsulant grinding
US7425759B1 (en) 2003-11-20 2008-09-16 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped terminal and filler
US7538415B1 (en) 2003-11-20 2009-05-26 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped terminal, filler and insulative base
WO2005074335A1 (en) * 2004-01-23 2005-08-11 Textron Systems Corporation Conductive vias and associated methods and structures
US7494925B2 (en) * 2004-02-23 2009-02-24 Micron Technology, Inc. Method for making through-hole conductors for semiconductor substrates
DE102004021062A1 (en) * 2004-04-29 2005-11-24 Siemens Ag Process for the production of printed circuit boards and / or corresponding constructs
US7852635B1 (en) * 2004-05-25 2010-12-14 Lineage Power Corporation Multi-connection via
JP4993848B2 (en) * 2004-05-28 2012-08-08 三洋電機株式会社 Wiring substrate
DE102004032706A1 (en) * 2004-07-06 2006-02-02 Epcos Ag Method for producing an electrical component and the component
US7375288B1 (en) * 2004-07-30 2008-05-20 Intel Corp. Apparatuses and methods for improving ball-grid-array solder joint reliability
US7268421B1 (en) 2004-11-10 2007-09-11 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond
US7446419B1 (en) 2004-11-10 2008-11-04 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar of stacked metal balls
US7750483B1 (en) 2004-11-10 2010-07-06 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal
KR100601485B1 (en) * 2004-12-30 2006-07-18 삼성전기주식회사 BGA package board and method for manufacturing thereof
TWI250629B (en) * 2005-01-12 2006-03-01 Ind Tech Res Inst Electronic package and fabricating method thereof
US7503111B2 (en) * 2005-03-31 2009-03-17 International Business Machines Corporation Method for increasing wiring channels/density under dense via fields
US7169313B2 (en) * 2005-05-13 2007-01-30 Endicott Interconnect Technologies, Inc. Plating method for circuitized substrates
KR100649683B1 (en) * 2005-08-17 2006-11-27 삼성전기주식회사 Printed circuit board and method for manufacturing the same
JP2007059803A (en) * 2005-08-26 2007-03-08 Fuji Xerox Co Ltd Printed circuit board, electronic substrate, and electronic apparatus
KR20080084812A (en) 2005-11-22 2008-09-19 쇼킹 테크놀로지스 인코포레이티드 Semiconductor devices including voltage switchable materials for over-voltage protection
US20100263200A1 (en) * 2005-11-22 2010-10-21 Lex Kosowsky Wireless communication device using voltage switchable dielectric material
US7404250B2 (en) * 2005-12-02 2008-07-29 Cisco Technology, Inc. Method for fabricating a printed circuit board having a coaxial via
US7906850B2 (en) * 2005-12-20 2011-03-15 Unimicron Technology Corp. Structure of circuit board and method for fabricating same
US8076244B2 (en) 2006-02-10 2011-12-13 Micron Technology, Inc. Methods for causing fluid to flow through or into via holes, vents and other openings or recesses that communicate with surfaces of substrates of semiconductor device components
US7604871B2 (en) * 2006-06-07 2009-10-20 Honeywell International Inc. Electrical components including abrasive powder coatings for inhibiting tin whisker growth
US7968010B2 (en) * 2006-07-29 2011-06-28 Shocking Technologies, Inc. Method for electroplating a substrate
US20080032049A1 (en) * 2006-07-29 2008-02-07 Lex Kosowsky Voltage switchable dielectric material having high aspect ratio particles
US20080029405A1 (en) * 2006-07-29 2008-02-07 Lex Kosowsky Voltage switchable dielectric material having conductive or semi-conductive organic material
KR20090055017A (en) * 2006-09-24 2009-06-01 쇼킹 테크놀로지스 인코포레이티드 Formulations for voltage switchable dielectric material having a stepped voltage response and methods for making the same
US7811863B1 (en) 2006-10-26 2010-10-12 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment
US7494843B1 (en) 2006-12-26 2009-02-24 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding
US20120119168A9 (en) * 2006-11-21 2012-05-17 Robert Fleming Voltage switchable dielectric materials with low band gap polymer binder or composite
US7999192B2 (en) 2007-03-14 2011-08-16 Amphenol Corporation Adjacent plated through holes with staggered couplings for crosstalk reduction in high speed printed circuit boards
US7793236B2 (en) * 2007-06-13 2010-09-07 Shocking Technologies, Inc. System and method for including protective voltage switchable dielectric material in the design or simulation of substrate devices
TW200924148A (en) * 2007-11-26 2009-06-01 Ind Tech Res Inst Structure of three-dimensional stacked dies with vertical electrical self-interconnections and method for manufacturing the same
US8206614B2 (en) * 2008-01-18 2012-06-26 Shocking Technologies, Inc. Voltage switchable dielectric material having bonded particle constituents
US8006934B2 (en) * 2008-03-31 2011-08-30 United Technologies Corporation Heating architecture for a composite fairing
US8203421B2 (en) * 2008-04-14 2012-06-19 Shocking Technologies, Inc. Substrate device or package using embedded layer of voltage switchable dielectric material in a vertical switching configuration
WO2010033635A1 (en) * 2008-09-17 2010-03-25 Shocking Technologies, Inc. Voltage switchable dielectric material containing boron compound
WO2010039902A2 (en) * 2008-09-30 2010-04-08 Shocking Technologies, Inc. Voltage switchable dielectric material containing conductive core shelled particles
US9208931B2 (en) * 2008-09-30 2015-12-08 Littelfuse, Inc. Voltage switchable dielectric material containing conductor-on-conductor core shelled particles
US8923007B2 (en) * 2008-10-02 2014-12-30 Oracle America, Inc. Multi-diameter unplugged component hole(s) on a printed circuit board (PCB)
US8362871B2 (en) * 2008-11-05 2013-01-29 Shocking Technologies, Inc. Geometric and electric field considerations for including transient protective material in substrate devices
US9226391B2 (en) 2009-01-27 2015-12-29 Littelfuse, Inc. Substrates having voltage switchable dielectric materials
US8272123B2 (en) 2009-01-27 2012-09-25 Shocking Technologies, Inc. Substrates having voltage switchable dielectric materials
US8399773B2 (en) 2009-01-27 2013-03-19 Shocking Technologies, Inc. Substrates having voltage switchable dielectric materials
CN102550132A (en) 2009-03-26 2012-07-04 肖克科技有限公司 Components having voltage switchable dielectric materials
US9053844B2 (en) * 2009-09-09 2015-06-09 Littelfuse, Inc. Geometric configuration or alignment of protective material in a gap structure for electrical devices
US20110198544A1 (en) * 2010-02-18 2011-08-18 Lex Kosowsky EMI Voltage Switchable Dielectric Materials Having Nanophase Materials
US9224728B2 (en) * 2010-02-26 2015-12-29 Littelfuse, Inc. Embedded protection against spurious electrical events
US9082622B2 (en) 2010-02-26 2015-07-14 Littelfuse, Inc. Circuit elements comprising ferroic materials
US9320135B2 (en) * 2010-02-26 2016-04-19 Littelfuse, Inc. Electric discharge protection for surface mounted and embedded components
US9844136B2 (en) 2014-12-01 2017-12-12 General Electric Company Printed circuit boards having profiled conductive layer and methods of manufacturing same
TWI654723B (en) * 2015-02-06 2019-03-21 矽品精密工業股份有限公司 Method of manufacturing package structure
US10251270B2 (en) * 2016-09-15 2019-04-02 Innovium, Inc. Dual-drill printed circuit board via
KR102029101B1 (en) * 2017-12-28 2019-10-07 삼성전자주식회사 Semiconductor package
US10477672B2 (en) * 2018-01-29 2019-11-12 Hewlett Packard Enterprise Development Lp Single ended vias with shared voids

Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE245788C (en) *
US3322881A (en) * 1964-08-19 1967-05-30 Jr Frederick W Schneble Multilayer printed circuit assemblies
US3334395A (en) * 1962-11-26 1967-08-08 Northrop Corp Method of making a metal printed circuit board
US3813773A (en) * 1972-09-05 1974-06-04 Bunker Ramo Method employing precision stamping for fabricating the wafers of a multiwafer electrical circuit structure
US4211603A (en) * 1978-05-01 1980-07-08 Tektronix, Inc. Multilayer circuit board construction and method
US4287253A (en) * 1975-04-08 1981-09-01 Photocircuits Division Of Kollmorgen Corp. Catalytic filler for electroless metallization of hole walls
US4479991A (en) * 1982-04-07 1984-10-30 At&T Technologies, Inc. Plastic coated laminate
US4718972A (en) * 1986-01-24 1988-01-12 International Business Machines Corporation Method of removing seed particles from circuit board substrate surface
DE3708000A1 (en) * 1987-03-12 1988-09-22 Isola Werke Ag METHOD FOR PRODUCING ELECTRIC CIRCUITS CONTAINING METAL CORES AND BASE MATERIAL THEREFOR
JPH025358A (en) * 1988-06-23 1990-01-10 Toshiba Lighting & Technol Corp Short arc electric discharge lamp
US4994349A (en) * 1988-06-27 1991-02-19 At&T Bell Laboratories Printed wiring board fabrication method
US5116459A (en) * 1991-03-06 1992-05-26 International Business Machines Corporation Processes for electrically conductive decals filled with organic insulator material
JPH04170036A (en) * 1990-11-01 1992-06-17 Ricoh Co Ltd Manufacture of anisotropic conductive film
US5232548A (en) * 1991-10-29 1993-08-03 International Business Machines Corporation Discrete fabrication of multi-layer thin film, wiring structures
US5261154A (en) * 1991-07-22 1993-11-16 Macdermid, Incorporated Process for fabricating multilayer printed circuits
US5309632A (en) * 1988-03-28 1994-05-10 Hitachi Chemical Co., Ltd. Process for producing printed wiring board
US5322593A (en) * 1991-11-21 1994-06-21 Nec Corporation Method for manufacturing polyimide multilayer wiring substrate
US5329695A (en) * 1992-09-01 1994-07-19 Rogers Corporation Method of manufacturing a multilayer circuit board
US5337466A (en) * 1990-10-17 1994-08-16 Nec Corporation Method of making a multilayer printed wiring board
US5426849A (en) * 1991-01-09 1995-06-27 Nec Corporation Method of producing a polyimide multilayer wiring board
US5440805A (en) * 1992-03-09 1995-08-15 Rogers Corporation Method of manufacturing a multilayer circuit
US5450290A (en) * 1993-02-01 1995-09-12 International Business Machines Corporation Printed circuit board with aligned connections and method of making same
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2451343C3 (en) * 1973-10-26 1978-10-05 Matsushita Electric Industrial Co., Ltd., Kadoma, Osaka (Japan) Printed circuit
DE2453788A1 (en) * 1973-11-21 1975-05-22 Litton Industries Inc METHOD OF MANUFACTURING CIRCUIT PANELS WITH PRINTED CIRCUITS
US5001605A (en) * 1988-11-30 1991-03-19 Hughes Aircraft Company Multilayer printed wiring board with single layer vias
US5243142A (en) * 1990-08-03 1993-09-07 Hitachi Aic Inc. Printed wiring board and process for producing the same
JP2874329B2 (en) * 1990-11-05 1999-03-24 日本電気株式会社 Method for manufacturing multilayer printed wiring board
US5319159A (en) * 1992-12-15 1994-06-07 Sony Corporation Double-sided printed wiring board and method of manufacture thereof

Patent Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE245788C (en) *
US3334395A (en) * 1962-11-26 1967-08-08 Northrop Corp Method of making a metal printed circuit board
US3322881A (en) * 1964-08-19 1967-05-30 Jr Frederick W Schneble Multilayer printed circuit assemblies
US3813773A (en) * 1972-09-05 1974-06-04 Bunker Ramo Method employing precision stamping for fabricating the wafers of a multiwafer electrical circuit structure
US4287253A (en) * 1975-04-08 1981-09-01 Photocircuits Division Of Kollmorgen Corp. Catalytic filler for electroless metallization of hole walls
US4211603A (en) * 1978-05-01 1980-07-08 Tektronix, Inc. Multilayer circuit board construction and method
US4479991A (en) * 1982-04-07 1984-10-30 At&T Technologies, Inc. Plastic coated laminate
US4718972A (en) * 1986-01-24 1988-01-12 International Business Machines Corporation Method of removing seed particles from circuit board substrate surface
DE3708000A1 (en) * 1987-03-12 1988-09-22 Isola Werke Ag METHOD FOR PRODUCING ELECTRIC CIRCUITS CONTAINING METAL CORES AND BASE MATERIAL THEREFOR
US5309632A (en) * 1988-03-28 1994-05-10 Hitachi Chemical Co., Ltd. Process for producing printed wiring board
JPH025358A (en) * 1988-06-23 1990-01-10 Toshiba Lighting & Technol Corp Short arc electric discharge lamp
US4994349A (en) * 1988-06-27 1991-02-19 At&T Bell Laboratories Printed wiring board fabrication method
US5337466A (en) * 1990-10-17 1994-08-16 Nec Corporation Method of making a multilayer printed wiring board
JPH04170036A (en) * 1990-11-01 1992-06-17 Ricoh Co Ltd Manufacture of anisotropic conductive film
US5426849A (en) * 1991-01-09 1995-06-27 Nec Corporation Method of producing a polyimide multilayer wiring board
US5116459A (en) * 1991-03-06 1992-05-26 International Business Machines Corporation Processes for electrically conductive decals filled with organic insulator material
US5261154A (en) * 1991-07-22 1993-11-16 Macdermid, Incorporated Process for fabricating multilayer printed circuits
US5232548A (en) * 1991-10-29 1993-08-03 International Business Machines Corporation Discrete fabrication of multi-layer thin film, wiring structures
US5322593A (en) * 1991-11-21 1994-06-21 Nec Corporation Method for manufacturing polyimide multilayer wiring substrate
US5440805A (en) * 1992-03-09 1995-08-15 Rogers Corporation Method of manufacturing a multilayer circuit
US5329695A (en) * 1992-09-01 1994-07-19 Rogers Corporation Method of manufacturing a multilayer circuit board
US5450290A (en) * 1993-02-01 1995-09-12 International Business Machines Corporation Printed circuit board with aligned connections and method of making same
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Research Disclosure No. 25 906; "A Printer Circuit Card With Filled Vias for Surface Mount Technology", Nov. 1985. *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020139578A1 (en) * 2001-03-28 2002-10-03 International Business Machines Corporation Hyperbga buildup laminate
US6879492B2 (en) * 2001-03-28 2005-04-12 International Business Machines Corporation Hyperbga buildup laminate
US20050098882A1 (en) * 2001-09-28 2005-05-12 Fujitsu Limited Multilayer wiring circuit board
US7253023B2 (en) * 2001-09-28 2007-08-07 Fujitsu Limited Multilayer wiring circuit board
US20030112582A1 (en) * 2001-12-13 2003-06-19 Sanders Michael C. Redundant data and power infrastructure for modular server components in a rack

Also Published As

Publication number Publication date
EP0713359A1 (en) 1996-05-22
US5487218A (en) 1996-01-30
US5557844A (en) 1996-09-24
KR100273933B1 (en) 2000-12-15
KR960020642A (en) 1996-06-17

Similar Documents

Publication Publication Date Title
USRE37840E1 (en) Method of preparing a printed circuit board
US7068519B2 (en) Printed circuit board and method manufacturing the same
US6323436B1 (en) High density printed wiring board possessing controlled coefficient of thermal expansion with thin film redistribution layer
KR100268212B1 (en) Computer system with photomask screened joining material and process
US6000129A (en) Process for manufacturing a circuit with filled holes
US7018866B2 (en) Circuit component built-in module with embedded semiconductor chip and method of manufacturing
KR100670751B1 (en) Semiconductor device, semiconductor wafer, semiconductor module and manufacturing method of semiconductor device
US20010023779A1 (en) Transfer material, method for producing the same and wiring substrate produced by using the same
JP2002170921A (en) Semiconductor device and its manufacturing method
US20030127725A1 (en) Metal wiring board, semiconductor device, and method for manufacturing the same
JP4606685B2 (en) Module with built-in circuit components
JP2002361475A (en) Solder paste and multilayer printed wiring board and semiconductor chip having solder bump formed by using the solder paste
US7038310B1 (en) Power module with improved heat dissipation
JP2012142557A (en) Wiring board and manufacturing method thereof
JP2004247668A (en) Lamination forming mid wiring member, wiring board, and their manufacturing method
KR19990023206A (en) Dendrite interconnect member for planarization in a semiconductor manufacturing process and method for manufacturing the same
JP4421081B2 (en) Power module and manufacturing method thereof
US20080241359A1 (en) Method of making circuitized substrate with selected conductors having solder thereon
US6125531A (en) Method of making a printed circuit board having filled holes and a fill member for use therewith including reinforcement means
JP3605313B2 (en) Wiring board and method of manufacturing the same
WO2003100850A1 (en) Substrate, wiring board, semiconductor package-use substrate, semiconductor package and production methods for them
JP4103482B2 (en) Semiconductor mounting substrate, semiconductor package using the same, and manufacturing method thereof
EP1197131A1 (en) A via connector and method of making same
JP2002100861A (en) Forming method of solder bump

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: TESSERA INTELLECTUAL PROPERTIES, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:022990/0023

Effective date: 20090604

AS Assignment

Owner name: INVENSAS CORPORATION, CALIFORNIA

Free format text: CHANGE OF NAME;ASSIGNOR:TESSERA INTELLECTUAL PROPERTIES, INC.;REEL/FRAME:026423/0286

Effective date: 20110425