WO2005074335A1

WO2005074335A1 - Conductive vias and associated methods and structures

Info

Publication number: WO2005074335A1
Application number: PCT/US2004/041925
Authority: WO
Inventors: Bruce Pettengill
Original assignee: Textron Systems Corporation
Priority date: 2004-01-23
Filing date: 2004-12-10
Publication date: 2005-08-11

Abstract

Embodiments of the present invention are directed to methods and structures providing completely filled electrical interconnections, or vias, that are disposed through a surface land mounting area, or pad, on a dielectric substrate (104). A via (100) includes a first conducting layer (106) on the inner surface (102c) of a via hole. The via hole is filled with a thermally conductive material (110) with a desired viscosity and/or thixotropic ratio. The via fill material may be a metal powder in an epoxy matrix. The dielectric substrate may be used in rigid and/or flexible circuit components such as PWBs. High levels of surface land co-planarity, or surface flatness for pads on such substrates may be achieved by the use of conductive layers formed by immersion processes. Aspects of the invention may provide reduced amounts of lead (Pb) or eliminate lead altogether from a substrate.

Description

CONDUCTIVE VIAS AND ASSOCIATED METHODS AND STRUCTURES

BACKGROUND

Electronic systems are made up of electronic circuits composed typically of integrated circuits (ICs) and other electronic components. The ICs contain desired electronic circuits, and implemented on a semiconductor substrate. The overall substrate surface area of an IC is referred to as a "die". Dies are typically placed within a protective structures, or packages. Packages are also referred to as "chips". Chips are typically placed on and connected to an electronic circuit assembly such as a printed wiring board (PWB) that includes a dielectric substrate and electrical interconnections. PWBs electrically interconnect the related IC(s) to other electrical components of the related electronic system.

As used in a PWB, the dielectric substrate typically includes a number of insulating dielectric layers interposed with metallic layers that have been selectively patterned. The selectively patterned metallic layers form electrical interconnections between the various components and/or ICs that are mounted to or on the substrate. The metallic layers are sometimes referred to as "trace", "circuit", or "signal" layers of the PWB. The interconnect lines are sometimes referred to as "traces."

As technology advances, the number of input output (I/O) connections for individual ICs has also generally increased. Each I/O connection from an IC requires a corresponding amount of surface area of the underlying PWB substrate both for physical mounting and to form an electrical connection. Because of this increase in the number of I/O connections, the die and package sizes have increased as well. These increased IC die and package sizes have required correspondingly larger mounting areas on the associated PWB substrates.

Traces located within different layers are typically connected electrically to other layers and/or components mounted on the surface of the substrate by electrical interconnections, or "vias". A via can be made by forming a hole through some or all of the layers of a substrate and then coating or plating the interior hole surface with an electrically conductive material such as copper or tungsten. Nias are accordingly sometimes referred to as plated through holes. When a via does not extend through the associated substrate from one surface to the other, the via is referred to as a "blind" via. Vias with diameters less than an arbitrary size, e.g., as defined by the IPC at 0.006 inches or 150 microns, are often referred to as "microvias."

One of the conventional ways of mounting components on a dielectric substrate is a ball grid array (BGA). A BGA package is typically a square package with terminals, in the form of an array of solder balls, protruding from the bottom of the package. These terminals are designed to be mounted on a plurality of corresponding pads located on the surface of a PWB or other substrate, such as a flex-circuit substrate.

In order to increase the packing density of electronic components and ICs on a PWB substrate, via-in-pad structures have been developed. A via-in-pad structure is a via that is located within a conductive pad. A via-in-pad structure includes an exposed outer surface of the via that is used as a land, or pad, to which an electrical connection can be made to a system component, e.g., a particular I/O connection of an IC. Use of such a via-in-pad structure conserves valuable space on the substrate surface when compared to the space necessary to implement a single via with a trace connection to a pad, which is sometime referred to as a "dogbone" because of the outline of the joined structures.

Prior art via structures and via-in-pad structures configured for fine pitch components, such as BGAs, have limitations including the spacing, or pitch, between rows and/or columns of the structures. Prior art via-in-pad structures have also been limited by the degree of co- planarity, or surface flatness, of the included pad structures, that prevents optimal electrical and thermal contact between the I/O connections of ICs and the related substrate and circuitry. Prior art vias, including, via-in-pad structures have proved to be relatively unstable thermally, with variations in circuit resistance occurring over ranges of temperature. Such changes in resistance have been observed when pads are disconnected from the underlying substrate due to thermal expansion. Prior art vias structures have additionally been limited from a toxicity standpoint by employing lead (Pb) in tin-lead compositions such as solder and etch-resist.

SUMMARY

The present invention addresses the limitations in the prior art, as described previously.

Aspects of the present invention are directed to completely filled electrical interconnections, or vias, that are disposed through a surface land mounting area, or pad, of a dielectric substrate, as used in rigid and/or flexible circuit components, e.g., PWBs. A via according to the present invention may include a first conducting layer on an inner surface of a via hole.

The via hole can be filled with a thermally conductive material with a desired viscosity and/or thixotropic ratio. The via fill material may be a metal powder in an epoxy matrix. The dielectric substrate may be used in rigid and/or flexible circuit components such as

PWBs. High levels of surface land co-planarity, or surface flatness for pads on such substrates may be achieved by the use of conductive layers formed by immersion processes.

Aspects of the invention may provide reduced amounts of lead (Pb) or eliminate lead altogether from a substrate.

One embodiment of the present invention includes a method of making a via-in-pad structure. A via hole is formed in a substrate having a first and second surfaces. The via hole has an inner via surface and a via aperture in each of the first and second surfaces. A first electrical conductor is applied onto the inner via surface of the via hole. The via hole is filled with a thermally conductive via fill material having a desired viscosity or thixotropic ratio. The via apertures are covered with a second conductive material, forming a closed via. First and second pads are formed on the first and second surfaces from the second conductive material, forming a via-in-pad structure. The step of filling the via hole with a thermally conductive via fill material may include introducing a silver-epoxy material into the via hole. The first and second pads may be formed having a co-planarity of less than 0.5 mil per linear inch of pad span. The step of covering the via apertures with a second conductive material may include a step of flash copper plating. The step of covering the via apertures may include steps of applying tin-lead, electroless-nickel-immersion-gold, or immersion-silver. A syringe may be used to fill the via hole with a thermally conductive via fill material. A vacuum may be applied to either one of the first and second surfaces, creating a pressure differential between opposing ends of said via hole, causing the via fill material to flow into and fill the via hole. The via hole may be formed in the substrate by using a laser to ablate material of the substrate. The via hole may be formed in the substrate by using a punch to form a hole in the substrate. A solder ball of a ball grid array may be affixed to the via-in-pad structure.

A further embodiment includes a via-in-pad structure. The via-in-pad structure includes a dielectric substrate having first and second surfaces. A via hole extends through the substrate from the first surface to the second surface. The via hole has a height, a diameter, and inner via surface with an area. The inner via surface defines a lateral boundary of a via volume. A first electrical conductor is disposed on the inner via surface and covers substantially all of the inner via surface. A second electrical conductor is disposed on the first and second surfaces of the substrate. The second electrical conductor defines first and second pads. A respective one of the pair is disposed on the first and second surfaces. The first and second pads define respectively first and second axial surfaces of the via volume. The first and second pads are electrically connected to one another by the first electrical conductor. A via fill material is disposed within the via volume. The via fill material has a thermal conductivity, and substantially fills all of the via volume not filled by the first electrical conductor.

The first electrical conductor may include copper, which may be electroplated copper. The first electrical conductor may have a thickness of about 0.002 inches. The first electrical conductor may include palladium. The via fill material may include a powder of electrical material in an epoxy matrix. The electrical conductor of the via fill material may include silver. The via fill material may have a viscosity between about 110,000 centipoise and about 140,000 centipoise. The via fill material may have a viscosity greater than 140,000 centipoise. The via fill material may have a thixotropic index or ratio between about 3 : 1 and about 5:1 for an increase of shear rate of 100 times. The aspect ratio of the via surface height and the via surface diameter is between about 3:1 and about 6:1. The substrate may be rigid. The substrate may include FR4. The substrate may be flexible. The substrate may include polyimide. The second electrical conductor may include a metal coating selected from the group consisting of tin-lead, immersion gold, electroless-nickel-immersion gold, immersion silver, and copper. The co-planarity of the first and second pads may be less than about one mil per linear inch of pad span. The co-planarity may be about 0.5 mils per linear inch of pad span. The co-planarity may be less than 0.5 mils per linear inch of pad span. The via hole diameter may be between about 5 mils and about 15 mils. A plurality of trace layers may be disposed within the substrate, with the one or more via-in-pads being operable to provide electrical connections between the one or more trace layers and pads on the first and second surfaces. Each of the trace layers is electrically insulated from different trace layers by the substrate, and the first electrical conductor may electrically connect one or more of the plurality of trace layers. The plurality of trace layers may include a power and a ground layer. A pair of opaque layers may be disposed within the substrate so as to block the view of the plurality of trace layers.

A further embodiment may include a blind- via-in-pad structure. The blind- via-in-pad structure includes a dielectric substrate having first and second surfaces. A via hole is disposed in the substrate through the first surface. The via hole has a height, a diameter, and an inner surface with an area. The inner surface defines a lateral boundary and an axial surface of a via volume. A first electrical conductor is disposed on the inner via surface, and covers substantially all of the inner via surface. A second electrical conductor is disposed on the first surfaces of the substrate. The second electrical conductor defines a first pad, which defines a second axial surface of the via volume. The first pad is electrically connected to the first electrical conductor. A via fill material is disposed within the via volume. The via fill material is thermally conductive, and substantially fills all of the via volume not filled by the first electrical conductor. The via fill material may include a powder of electrical conductor material in an epoxy matrix. The electrical conductor of the via fill material may be silver. The via fill material may have a viscosity between about 110,000 centipoise and about 140,000 centipoise. The via fill material may have a thixotropic index or ratio between about 3 : 1 and about 5 : 1 for an increase of shear rate of 100 times. The co-planarity of the first pad may be less than about one mil per linear inch of pad span. The co-planarity may be about 0.5 mils per linear inch of pad span. The co-planarity may be less than 0.5 mils per linear inch of pad span. The via hole diameter may be between about 5 mils and about 15 mils.

A further embodiment may include a method of making a blind-via-in-pad structure. A via hole may be formed in a substrate having first and second surfaces. The via hole may have a an inner via surface and a via aperture in the first surface of the substrate. A first electrical conductor may be applied onto the inner via surface of the via hole. The via hole may be filled with a thermally conductive via fill material having a desired viscosity or thixotropic ratio. The via aperture may be covered with a second conductive material, forming a blind via. A first pad may be formed with the second conductive material, forming a blind-via-in- pad structure. The step of filling the via hole with a thermally conductive via fill material may include a step of introducing a conductor-epoxy material to the via hole. A silver-epoxy material may be introduced to the via hole. The step of covering the via aperture with a second conductive material may include a step of flash copper plating. The step of covering the via aperture may include steps of applying tin-lead, electroless-nickel-immersion-gold, or immersion-silver. A syringe may be used for introducing the via fill material to the via hole to fill the via hole. The first pad of second conductive material may be formed with a co- planarity of less than 0.5 mil per linear inch of pad span.

A further embodiment includes a printed circuit board. The printed circuit board may include a dielectric substrate having first and second surfaces. A plurality of via holes may extend through the substrate from the first surface to the second surface. Each of the plurality of via holes has a height, a diameter, and an inner via surface with an area. The inner via surface defines a lateral boundary of a via volume for each respective via hole. A first electrical conductor is disposed on the inner via surface of each of the plurality of via holes, and covers substantially all of the inner via surface of each of the plurality of via holes. A second electrical conductor is disposed on the first and second surfaces of the substrate. The second electrical conductor defines a plurality of pairs of first and second pads. A respective one of each pair is disposed on the first and second surfaces. Each pair of first and second pads defines respectively first and second axial surfaces of a via volume of an associated via hole. The first and second pads of each pair is electrically connected by the first electrical conductor of the associated via hole. A via fill material is disposed within the via volume of each via hole. The via fill material is thermally conductive, and substantially fills all of the via volume not filled by the first electrical conductor. A plurality of trace layers is disposed within the substrate. Each of the trace layers is electrically insulated from different trace layers by the substrate. The first electrical conductor of each of the plurality of via holes electrically connects one or more of the plurality of trace layers to pairs of pads.

The pairs of pads may be configured in a square array to receive a ball grid array. A pitch between rows or columns of the array may be less than or equal to about 19 mils. The second electrical conductor may include copper, electroless-nickel-immersion-gold, or immersion silver. The pairs of first and second pads may have a co-planarity of less then 0.5 mil per inch of pad length.

DESCRIPTION OF THE DRAWINGS

These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed on illustration of principles of the invention. The drawings include the following figures:

FIG. 1 depicts a side cross sectional view of a via structure according to the present invention.

FIG. 2 depicts a side cross sectional view of the via structure of FIG. 1 with an additional layer of conductive material applied by a panel plating process.

FIG. 3 is a microscope photograph of a cross sectional view of via structure according to the present invention. FIG. 4 depicts the results of a scanning electron microscope elemental (SEM) spectrum analysis indicating fill properties of the via structure of FIG. 3.

FIG. 5 includes FIG. 5A and FIG. 5B which depict the results of a thermal shock endurance test according to Mil-STD-202, Method 107 using test condition A-1 that was performed on a printed circuit board according to the present invention. The test was performed using modified temperature limits of -25°F (-32°C), 77°F (25°C), 230°F (110°C), and 77°F (25°C).

FIG. 6 depicts a side cross sectional view of a substrate structure according to certain embodiments of the present invention.

FIG. 7 depicts steps in a method of forming a via-in-pad structure according to the present invention.

FIG. 8 depicts a side cross sectional view of a blind via structure according to the present invention.

FIG. 9 depicts steps in a method of forming a blind-via-in-pad structure according to the present invention.

DETAILED DESCRIPTION

The present invention may be understood by the following detailed description, which should be read in conjunction with the attached drawings. The following detailed description of certain embodiments is by way of example only and is not meant to limit the scope of the present invention.

Aspects of the present invention are directed to a filled via, that extends through one or both surfaces of a dielectric substrate. A via aperture on either surface of the substrate may be covered by an electrical pad. Suitable substrates may be rigid and/or flexible. A via according to the present invention may include a first conducting layer on an inner surface of the via hole. The via hole can be filled with a thermally conductive material with a desired viscosity and/or thixotropic characteristic. The thixotropic characteristic, referring to a materials change in viscosity between different shear rates, may be a thixotropic index, or ratio. The via fill material may be a metal powder that is dispersed or suspended in an epoxy matrix. A via according to the present invention may provide for high levels of surface co- planarity, or surface flatness of associated pads on a corresponding substrate. Aspects of the invention may provide reduced amounts of lead (Pb) or eliminate lead altogether from a substrate.

FIG. 1 depicts a side cross sectional view of a via structure 100 according to one embodiment of the present invention. A via hole 102 extends through a dielectric substrate 104 that has first and second surfaces 104a- 104b. The via hole 102 has first and second openings or apertures 102a- 102b in the first and second surfaces 104a- 104b, respectively. The via hole 102 also has an inner surface 102c and a diameter 102d. The inner surface 102c has defines a cylindrical shape that has a height substantially equal to the thickness of the substrate 104 and an area that is equal to the substrate thickness multiplied by the circumference of the apertures 102a- 102b. A first layer of electrically conductive material 106 is disposed on the via hole inner surface 102c. The first layer 106 of electrical conductor may include palladium and/or copper, in certain embodiments. A second layer of electrically conductive material 108 is disposed on the first and second surfaces 104a-104b of the substrate 104. The second layer of conductive material 108 can include one or more layers such as a sputtered- deposited layer of copper 108a and a flash copper plating layer 108b. The remaining portion of the via volume not occupied by the first conductive layer 106 is filled with a thermally conductive via fill material 110. The aspect ratio of the via surface height and the via surface diameter may be as desired. In certain embodiments, the aspect ration may be between about 3:1 and about 6:1.

The via fill material 110 has a desired viscosity or thixotropic characteristic that facilitates the filling of the via hole 102 with few if any voids. In certain embodiments, the via fill material has 110 has a viscosity is between about 110,000 centipoise and about 140,000 centipoise. The via fill material may have a viscosity greater than 140,000 centipoise. In certain embodiments, the via fill material 110 may be electrically conductive as well as thermally conductive. The via fill material 110 preferably does not contain any solvent materials, which further facilitates the minimization of voids within the via fill material 110. As a consequence of these physical attributes, the number of voids within the via fill material 110 and via structure 100 is minimized. This provides the via structure 100 with electrical characteristics that are extremely stable over wide temperature ranges, as described in greater detail for FIG. 5. The via fill material 110 may have low coefficient of thermal expansion to facilitate thermal stability. Suitable materials for the via fill material 110 include metal powders dispersed of suspended in an epoxy matrix. For example, silver powder in an epoxy matrix may be used in certain embodiments.

In preferred embodiments, the via fill material 110 is a mixture of two epoxy/silver based via hole fill materials manufactured by Jodan Technology of 231 Treetop Lane, Yorktown Heights, NY, 10598. The via fill material 110 for these embodiments may be made by mixing product code AG-1200-HV (high viscosity) and AG-1200-LV (low viscosity). Preferred ratios for the mixture may range from 0.1 : 1 to 1 :4 on a volumetric basis, where the ratio indicates the volume of AG-1200-HV to the volume of AG-1200-LV. An exemplary ratio is 1:3 of AG-1200-HV to AG-1200-LV. These materials exhibit a thixotropic ratio of between about 3 and about 5, when shear velocities are increased on the order of 100 times. Other suitable thermally conductive via fill materials with similar physical characteristics may be used within the scope of the invention.

FIG. 2 depicts a side cross sectional view of via structure 100 of FIG. 1, with an additional conductive layer 108c disposed on the second conductive layer 108. The additional layer

108c may be applied by a panel plating process and/or an immersion process. The additional conductive layer 108c covers and bridges the first and second apertures 102a-102b of the via hole 102. In doing so, the additional conductive layer 108c forms a level surface over the first and second apertures. The level surface formed by conductive layer 108c has a high degree of co-planarity, which may be particularly well suited for a mounting pad for desired surface mount components, e.g., BGAs.

The substrate 104 may be of any suitable type. In certain embodiments, suitable rigid dielectric materials may be used for the substrate 104. Such rigid materials may include, but are not limited to, FR4, resin coated copper (RCC), alumina, beryllium oxides, and the like. In certain other embodiments, suitable flexible dielectric materials may be used for the substrate. Such flexible materials may include, but are not limited to, polyimide materials, polyester materials, and other suitable polymer thick film (PTF) dielectric materials. FIG. 3 is a microscope photograph of a cross sectional view of a via structure 300 according to the present invention. The location on the cross section of the via structure 300 at which an SEM spectrum analysis was performed is indicated by the arrow 302. The SEM spectrum analysis is described below with respect to Fig. 4. The via structure 300 includes a via 301 that extends through a dielectric substrate 304 that has first and second surfaces 306a and 306b. The via 301 includes a via inner hole surface 303 with a first conductive layer 305, forming a plated through hole structure. The via 301 was filled with a via fill material consisting of the previously described Jodan Technology via fill materials at a ratio of 1 :3 of AG-1200-HN to AG-1200-LN.

As referenced above, FIG. 4 depicts the results of a scanning electron microscope elemental (SEM) spectrum analysis 400 indicating fill properties of the via structure 300 of FIG. 3 at the location indicated by arrow 302. Two major peaks 402 and 404 in the spectrum analysis 400 indicate a high content of silver in the via fill material of the filled via structure 300. The spectrum analysis also indicates that few trace elements are present in the via fill material of the via structure 300. This is advantageous because the presence of significant amounts of trace elements in the via fill material can lead to deleterious thermal effects on the via fill material of the filled via 300 and/or associated substrate 304. For example, the presence of significant amounts of trace elements can reduce the continuity of the grain structure of the via fill material within the filled via 300. Discontinuities, such as voids, within the via fill material can prevent or reduce the ability of the filled via to act as a heat conducting thermal path for any ICs or other components mounted to the associated substrate 304.

In addition to the potential for disrupting the continuity of grain structure for heat conduction, the presence of significant amounts of trace elements is undesirable since they can reduce the electrical conductivity of the via 300 and consequently the ability of the filled via 301 for transferring an electrical signal from or to and ICs or other components mounted to the associated substrate.

FIG. 5 includes FIG. 5A and FIG. 5B which depict a table with the results of a thermal shock endurance test according to Mil-STD-202, Method 107 using test condition A-1 for a printed circuit board (PWB) containing via structures according one embodiment of the present invention. The test condition included modified temperature limits of -25°F (-32°C), 77°F (25°C), 230°F (110°C), and 77°F (25°C). Before the thermal shock endurance test, the incoming acceptance of the PWB was verified. Three via structures of the PWB were subject to destructive physical analysis (DP A) in accordance with testing procedure IPC-6012 of the Institute for Interconnecting and Packaging Electronic Circuits (IPC). Testing in this acceptance procedure included all requirements of the normal Group A test series of IPC- 6012. No anomalies were found during the acceptance procedure.

In the thermal shock endurance test, six independent circuits, C1-C6, of the PWB were electronically monitored for resistance, Ω, through the entire period of the test plan for a total of twenty-five cycles. There were no observed failures throughout the test sequence. All changes in resistance values were within the allowable variation, i.e., plus or minus 5%, of the test plan for each circuit being tested. Because each of the six circuits was different in total length, width, and/or actual copper weight, the resistance readings were different from circuit to circuit.

Referring to FIGS. 5A-5B, the results of the thermal testing indicate that the printed circuit board met the certification requirements of IPC-TM-650, Method 2.6.7. The change in resistance, Ω, for any of the six circuits, C1-C6, did not vary by more than 50% and in no case exceeded 1 ohm from the initial readings at ambient room temperature. The high resistance stability that the testing indicated was due in part to total hole fill with the via fill material.

FIG. 6 depicts side cross sectional view of a substrate structure 600 according to certain embodiments of the present invention. The substrate structure 600 includes a dielectric substrate 601 that has planar first and second surfaces 604a-604b, and may be part of a PWB. Multiple electrically conductive layers 606a-606c are disposed on the first surface and second surfaces 604a-604b. The multiple conductive layers 606a-606c are patterned as a pair of first and second conductive pads 608a-608b suitable for the mounting of a connection of a surface mount component. For example, in one embodiment, the connection mounted to pad 608a may be a solder ball of a BGA with a pitch of 19 mils. The pads 608a-608b cover respective via apertures 605a-605b of a via hole 605 extending through the substrate 601. An inner surface of the via hole 605 is covered by an electrically conductive via layer 605c. A thermally conductive via fill material 610 substantially fills all of the volume bounded by the conductive via layer and the first and second pads 608a-608b. The substrate structure 600 includes multiple signal layers 612a-612c for transferring electrical signals. The signal layers 612a-612c may include a power and ground layer. The pads 608a-608b may be patterned and formed by suitable lithography and etching processes. A pair of opaque layers may be disposed within the substrate 601 so as to block the view of the plurality of signal layers 612a-612c, for certain applications.

The conductive layers 606a-606c of the pad include a sputter deposited copper layer 606a that is covered with a copper plating layer 606b. An outer conductive layer 606c covers the copper plating layer 606b. The outer conductive layer 606c has a surface co-planarity 609 that may be of a desired level of flatness, e.g., less than 0.5 mils per inch of linear pad length. In certain embodiments, a tin-lead solder layer may be deposited as the conductive layer 606c on the copper plating layer 606b. A suitable tin-lead solder layer 606c may be formed by a hot air surface leveling (HASL) reflow process. The surface co-planarity 609 of first and second pads 608a-608b in one embodiment employing a tin-lead solder for the outer conductive layer 606c was measured to be 0.0052 inches per linear inch of pad length. In certain other embodiments, the outer conductive layer 606c may be electroless nickel- immersion-gold, such as formed by immersion of the substrate structure 600 in an electroless- nickel-immersion-gold bath. The surface co-planarity 609 of first and second pads 608a- 608b in an alternate embodiment employing electroless-nickel-immersion-gold for the outer conductive layer 606c was measured to be less than 0.0005 inches per linear inch of pad length. This co-planarity 609 of the electroless nickel-immersion-gold layer represents an improvement of an order of magnitude compared to the tin-lead solder layer. In a preferred embodiments, immersion-silver is used for the outer conductive layer 606c. An immersion- silver layer conductive layer 606c may be formed by immersion of the substrate 600 in an immersion-silver bath. The surface co-planarity 609 of first and second pads 608a-608b in an alternate embodiment employing immersion-silver for the outer conductive layer 606c was measured to be less than 0.0006 inches per linear inch of pad length. The use of electroless- nickel-immersion gold and/or immersion-silver may facilitate reduced or lead-free PWB processing and PWB structures. The use of electroless-nickel-immersion gold and/or immersion-silver may also facilitate the reduction or elimination of solder bridging for components, e.g., BGAs, mounted to the associated PWB. FIG. 7 depicts steps in a method 700 of making a via-in-pad structure. A via hole may be formed, as described in step 702, in a substrate having a first and second surfaces. The via hole has an inner via surface, or via sidewall, and a via aperture in each of said first and second surfaces. A first electrical conductor may be applied, as described in step 704, onto the sidewall of the via hole. The via hole may be filled, as described in step 706, with a thermally conductive via fill material having a desired viscosity and/or thixotropic ratio. The via apertures may be covered, as described in step 708, with a second conductive material to form a closed via a is formed. First and second pads may be formed, as described in step 710, from said second conductive material to form a via-in-pad structure. The step of covering the via aperture may include steps of applying tin-lead, electroless nickel- immersion-gold, or immersion-silver. A syringe may be used for introducing the via fill material to the via hole to fill the via hole. The first and second pads of second conductive material may be formed with a co-planarity of less than 0.5 mil per linear inch of pad span.

FIG. 8 depicts a side cross sectional view of a blind via structure 800 according to one embodiment of the present invention. A via hole 802 extends partially through a dielectric substrate 804 that has first and second surfaces 804a-804b. The via hole 802 has an opening, or aperture, 802a in the first surfaces 104a. The via hole 802 also has an inner surface 802c and a diameter 802d. The inner surface 802c defines a cylindrical shape that has a height less than the thickness of the substrate 804 and an area that is equal to the height multiplied by the circumference of the apertures 802a. A first layer of electrically conductive material 806 is disposed on the via hole inner surface 802c. A second layer 808 of electrically conductive material is disposed on the first surface 804a, and possibly the second surface 804b. The second layer 808 can include one or more layers such as a sputtered-deposited layer of copper 808a and a flash copper plating layer 808b. The remaining portion of the via volume not occupied by the first conductive layer 806 is filled with a thermally conductive via fill material 810. The second layer may form a pad covering the via aperture 802a.

FIG. 9 depicts steps in a method of making a blind-via-in-pad structure. A via hole may be formed, as described in step 902, in a substrate having a first and second surfaces. The via hole has an inner via surface, or via sidewall, and a via aperture in the first via surface. A first electrical conductor may be applied, as described in step 904, onto the sidewall of said via hole. The via hole may be filled, as described in step 906, with a thermally conductive via fill material having a desired viscosity. The via aperture may be filled, as described in step 908, with a second conductive material to form a blind via is formed. A first pad may be formed, as described in step 910, with the second conductive material to form a blind- via-in- pad structure.

Accordingly, embodiments of the present invention may offer advantages over the prior art. Embodiments may be used to provide pads having co-planarity of less than one (1) mil (0.001 inch) per linear inch of pad length. Embodiments may be used to provide pads having co- planarity of less than one-half mil (0.0005 inch) per linear inch of pad length. Surface pads according to the present invention may facilitate solder mounting of a surface mount component to pads that each have a relatively small area compared to the prior art. Via-in- pad structures according to the present invention may facilitate, or provide complete, testing accessibility to specific circuits of an associated PWB. Via-in-pad structures maybe used as probe test points to measure any electrical characteristics, e.g., resistance, capacitance, failure, etc., of components of interest on the associated PWB. Conductive surface coatings according to the present invention may facilitate lead-free PWBs. The relatively small pad surface areas that are obtainable through use of the present invention may be well suited for high density interconnect (HDI) circuitry, such as fine pitch components, e.g., BGAs. Aspects of the present invention may eliminate the need for use of a solder mask in a PWB. Certain embodiments may provide opaque layers that block sight of trace or signal layers inside a substrate. The high co-planarity afforded by the present invention may also eliminate the need for solder masks.

While the present invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. For example, while certain embodiments have been described as including a specific material for a dielectric substrate other materials may be used. Further, while BGAs have been described that employ solder balls made of tin- lead (Sn/Pb) solder alloys, other solder alloys may be used. For example, in certain embodiments tin-silver-copper (Sn/Ag/Cu, or "SAC") alloys may be used for lead-free processing.

Claims

CLAIMSWhat is claimed is:

1. A method of making a via-in-pad structure, said method comprising the steps of: forming a via hole in a substrate having a first and second surfaces, wherein said via hole has a via inner surface and a via aperture in each of said first and second surfaces; applying a first electrical conductor onto said via inner surface of said via hole; filling said via hole with a thermally conductive via fill material having a desired viscosity or thixotropic ratio; and covering said via apertures with a second conductive material, whereby a closed via is formed; and forming first and second pads on said first and second surfaces from said second conductive material, whereby a via-in-pad structure is formed.

2. The method of Claim 1 , wherein said step of filling said via hole with a thermally conductive via fill material comprises a step of introducing a silver-epoxy material into said via hole.

3. The method of Claim 2, wherein said step of forming first and second pads with said second conductive material comprises forming first and second pads having a co-planarity of less than 0.5 mil per linear inch of pad span.

4. The method of Claim 1, wherein said step of covering said via apertures with a second conductive material comprises a step of flash copper plating.

5. The method of Claim 1, wherein said step of filling said via hole with a thermally conductive via fill material comprises a step of using a syringe to introduce said fill material to said via hole.

6. The method of Claim 1, wherein said step of filling said via hole with a thermally conductive via fill material comprises a step of applying a vacuum to one of said first and second surfaces, wherein a pressure differential exists between opposing ends of said via hole, whereby said via fill material flows into and fills said via hole.

7. The method of Claim 1, wherein said step of forming a via hole in a substrate comprises a step of using a laser to ablate material of said substrate.

8. The method of Claim 1, wherein said step of forming a via hole in a substrate comprises a step of using a punch to form a hole in said substrate.

9. The method of Claim 1 , further comprising a step of affixing a solder ball of a ball grid array to said via-in-pad structure.

10. The method of Claim 1, wherein said step of covering said via apertures with a second conductive material, whereby a closed via is formed, comprises a step of covering said via apertures with immersion-silver.

11. The method of Claim 1, wherein said step of covering said via apertures with a second conductive material, whereby a closed via is formed, comprises a step of covering said via apertures with electroless-nickel-immersion-gold.

12. A via-in-pad structure comprising: a dielectric substrate having first and second surfaces; a via hole extending through said substrate from said first surface to said second surface, said via hole having a height, a diameter, and an inner via surface with an area, said inner via surface defining a lateral boundary of a via volume; a first electrical conductor disposed on said inner via surface, wherein said first electrical conductor covers substantially all of said inner via surface; a second electrical conductor disposed on said first and second surfaces of said substrate, wherein said second electrical conductor defines first and second pads, wherein a respective one of said pair is disposed on said first and second surfaces, wherein said first and second pads define respectively first and second axial surfaces of said via volume, wherein said first and second pads are electrically connected to one another by said first electrical conductor; and a via fill material disposed within said via volume, wherein said via fill material ihas a thermal conductivity, and wherein said via fill material substantially fills all of said via volume not filled by said first electrical conductor.

13. The structure of Claim 12, wherein said first electrical conductor comprises copper.

14. The structure of Claim 13, wherein said first electrical conductor comprises electroplated copper.

15. The structure of Claim 14 wherein said first electrical conductor has a thickness of about 0.002 inches.

16. The structure of Claim 12, wherein said first electrical conductor comprises palladium.

17. The structure of Claim 12, wherein said via fill material comprises a powder or electrical material in an epoxy matrix.

18. The structure of Claim 17, wherein said electrical conductor is silver.

19. The structure of Claim 12, wherein said via fill material has a viscosity is between about 1 10,000 centipoise and about 140,000 centipoise.

20. The structure of Claim 12, wherein said via fill material has a thixotropic ratio between about 3:1 and about 5:1 for an increase of shear rate of 100 times.

21. The structure of Claim 12, wherein said dielectric substrate comprises one or more circuit layers disposed between said first and second surfaces, wherein said one or more via- in-pads are operable to provide electrical connections between said one or more circuit layers and said first and second surfaces.

22. The structure of Claim 12, wherein an aspect ratio of said via hole surface height and said via hole diameter is between about 3 : 1 and about 6:1.

23. The structure of Claim 12, wherein said substrate is rigid.

24. The structure of Claim 23, wherein said substrate comprises FR4.

25. The structure of Claim 12, wherein said substrate is flexible.

26. The structure of Claim 25, wherein said substrate comprises polyimide.

27. The structure of Claim 12, wherein said second electrical conductor includes a metal coating selected from the group consisting of tin-lead, immersion-gold, electroless-nickel- immersion-gold, immersion-silver, and copper.

28. The structure of Claim 12, wherein a co-planarity of said first and second pads is less than about one mil per linear inch of pad span.

29. The structure of Claim 28, wherein said co-planarity is about 0.5 mils per linear inch of pad span.

30. The structure of Claim 29, wherein said co-planarity is less than 0.5 mils per linear inch of pad span.

31. The structure of Claim 12, wherein said via aperture diameter is between about 5 mils and about 15 mils.

32. The structure of Claim 12, further comprising a plurality of trace layers disposed within said substrate, wherein each of said trace layers is electrically insulated from different trace layers by said substrate, and wherein said first electrical conductor electrically connects one or more of said plurality of trace layers.

33. The structure of Claim 32, wherein said plurality of trace layers comprise a power and a ground layer.

34. The structure of Claim 32, further comprising a pair of opaque layers disposed within said substrate so as to block the view of said plurality of trace layers.

35. A. blind-via-in-pad structure comprising: a dielectric substrate having first and second surfaces; a via hole disposed in said substrate through said first surface, said via hole having a height, a diameter, and an inner via surface with an area, said inner via surface defining a lateral boundary and an axial surface of a via volume; a first electrical conductor disposed on said inner via surface, wherein said first electrical conductor covers substantially all of said inner via surface; a second electrical conductor disposed on said first surfaces of said substrate, wherein said second electrical conductor defines a first pad, wherein said first pad defines a second axial surfaces of said via volume, wherein said first pad is electrically connected to said first electrical conductor; and a via fill material disposed within said via volume, wherein said via fill material is thermally conductive, and wherein said via fill material substantially fills all of said via volume not filled by said first electrical conductor.

36. The structure of Claim 35, wherein said via fill material comprises a powder or electrical material in an epoxy matrix.

37. The structure of Claim 36, wherein said electrical conductor is silver.

38. The structure of Claim 35, wherein said via fill material has a viscosity is between about 110,000 centipoise and about 140,000 centipoise.

39. The structure of Claim 35, wherein said via fill material has a thixotropic ratio between about 3:1 and about 5:1 for an increase of shear rate of 100 times.

40. The structure of Claim 35, wherein a co-planarity of said first pad is less than about one mil per linear inch of pad span.

41. The structure of Claim 40, wherein said co-planarity is about 0.5 mils per linear inch of pad span.

42. The structure of Claim 40, wherein said co-planarity is less than 0.5 mils per linear inch of pad span.

43. The structure of Claim 35, wherein said via hole diameter is between about 5 mils and about 15 mils.

44. A method of making a blind-via-in-pad structure, said method comprising the steps of: forming a via hole in a substrate having a first and second surfaces, wherein said via hole has a via sidewall and a via aperture disposed in said first via surface; applying a first electrical conductor onto said sidewall of said via hole; filling said via hole with a thermally conductive via fill material having a desired viscosity or thixotropic ratio; and covering said via aperture with a second conductive material , whereby a blind via is formed; and forming a first pad with said second conductive material, whereby a blind-via-in-pad structure is formed.

45. The method of Claim 44, wherein said step of filling said via hole with a thermally conductive via fill material comprises a step of introducing a conductor-epoxy material to said via hole.

46. The method of Claim 45, wherein said step of filling said via hole with a thermally conductive via fill material includes a step of introducing a silver-epoxy material to said via hole.

47. The method of Claim 44, wherein said step of covering said via aperture with a second conductive material comprises a step of flash copper plating.

48. The method of Claim 44, wherein said step of covering said via aperture with a second conductive material comprises a step of applying electroless-nickel-immersion-gold or immersion-silver.

49. The method of Claim 44, wherein said step of filling said via hole with a thermally conductive via fill material comprises a step of using a syringe to introduce said fill material to said via hole.

50. The method of Claim 44, wherein said step of forming a first pad with said second conductive material comprises forming a first pad with a co-planarity of less than 0.5 mil per linear inch of pad span.

51. A printed circuit board comprising: a dielectric substrate having first and second surfaces; a plurality of via holes extending through said substrate from said first surface to said second surface, each of said plurality of via holes having a height, a diameter, and inner via surface with an area, said inner via surface defining a lateral boundary of a via volume for a respective via hole; a first electrical conductor disposed on said inner via surface of each of said plurality of via holes, wherein said first electrical conductor covers substantially all of said inner via surface of each of said plurality of via holes; a second electrical conductor disposed on said first and second surfaces of said substrate, wherein said second electrical conductor defines a plurality of pairs of first and second pads, wherein a respective one of each said pair is disposed on said first and second surfaces, wherein each of said first and second pads of said plurality of pairs of pads define respectively first and second axial surfaces of a via volume of an associated via hole, wherein each first pad is electrically connected to a corresponding second pad by said first electrical conductor in said associated via hole; a via fill material disposed within said via volume of each said plurality of via holes, wherein said via fill material is thermally conductive, and wherein said via fill material substantially fills all of said via volume not filled by said first electrical conductor; and a plurality of trace layers disposed within said substrate, wherein each of said trace layers is electrically insulated from different trace layers by said substrate, and wherein said first electrical conductor of each of said plurality of via holes electrically connects one or more of said plurality of trace layers.

52. The printed circuit board of Claim 51 , wherein said pairs of pads are configured in a square array to receive a ball grid array.

53. The printed circuit board of Claim 52, wherein in a pitch between rows or columns of said aπay is less than or equal to 19 mils.

54. The printed circuit board of Claim 51 , wherein said second electrical conductor comprises copper, electroless-nickel-immersion-gold, or immersion silver.

55. The printed circuit board of Claim 51 , wherein said pairs of first and second pads have a co-planarity of less then 0.5 mil per inch of pad length.