JPH04168127A - Prepreg and multi-layer circuit board - Google Patents
Prepreg and multi-layer circuit boardInfo
- Publication number
- JPH04168127A JPH04168127A JP29673090A JP29673090A JPH04168127A JP H04168127 A JPH04168127 A JP H04168127A JP 29673090 A JP29673090 A JP 29673090A JP 29673090 A JP29673090 A JP 29673090A JP H04168127 A JPH04168127 A JP H04168127A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- fep
- prepreg
- circuit board
- cloth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920001343 polytetrafluoroethylene Polymers 0.000 claims abstract description 22
- 239000004810 polytetrafluoroethylene Substances 0.000 claims abstract description 22
- 229920001577 copolymer Polymers 0.000 claims abstract description 9
- -1 polytetrafluoroethylene Polymers 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- BFKJFAAPBSQJPD-UHFFFAOYSA-N tetrafluoroethene Chemical group FC(F)=C(F)F BFKJFAAPBSQJPD-UHFFFAOYSA-N 0.000 claims 1
- 239000004744 fabric Substances 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract 2
- 238000004904 shortening Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 49
- 239000000835 fiber Substances 0.000 description 12
- 238000010438 heat treatment Methods 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 239000011889 copper foil Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000005470 impregnation Methods 0.000 description 8
- 239000011888 foil Substances 0.000 description 7
- 239000006185 dispersion Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 238000007598 dipping method Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229920006231 aramid fiber Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 239000004699 Ultra-high molecular weight polyethylene Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005243 fluidization Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000012784 inorganic fiber Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229920000785 ultra high molecular weight polyethylene Polymers 0.000 description 1
- 239000002759 woven fabric Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は電子機器、通信機器、コンピュータ等の高周波
域を利用する各種機器の製造に好適なプリプレグ、この
プリプレグを用いて成る多層回路板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a prepreg suitable for manufacturing various devices that utilize high frequency ranges such as electronic equipment, communication equipment, and computers, and a multilayer circuit board using this prepreg. .
従来、高周波域を利用する各種機器には、ガラスクロス
にポリテトラフルオロエチレン（以下、ＰＴＦＥと称す
）を含浸せしめたプリプレグの表面に銅箔を重ね合わせ
、加熱加圧により両者を一体化した積層板を得、この積
層板の銅箔をパターン化して回路板とし、この回路板の
所定枚を一体化して成る多層回路板が使用されることが
ある（特開昭６４−６１２４５号公報）。Conventionally, various devices that use high frequencies have been manufactured by laminating copper foil on the surface of a prepreg made of glass cloth impregnated with polytetrafluoroethylene (hereinafter referred to as PTFE) and integrating the two by heating and pressing. A multilayer circuit board is sometimes used in which a board is obtained, the copper foil of the laminated board is patterned to form a circuit board, and predetermined circuit boards are integrated (Japanese Patent Laid-Open No. 64-61245).
［発明が解決しようとする課題〕
ところで、上記従来の多層回路板の製造に際しては、布
状基材にＰＴＦＥを含浸させたプリプレグと回路板とを
接着させなければならず、従って、加熱加圧作業時の温
度は当然のことながら、ＰＴＦＥの融点以上、実際的に
は約３８０〜４００℃という高温を必要とし、また、圧
力も約１０〜８０ｋｇ／ｃｉと高いものである。このた
め、複雑高価な製造設備を設置しなければならなかった
。更に、接着を十分に行うために長時間を要し、生産性
も悪いという問題もあった。[Problems to be Solved by the Invention] By the way, when manufacturing the above-mentioned conventional multilayer circuit board, it is necessary to bond the circuit board to the prepreg in which a cloth-like base material is impregnated with PTFE. Needless to say, the working temperature needs to be higher than the melting point of PTFE, in practice, about 380 to 400°C, and the pressure is also high, about 10 to 80 kg/ci. For this reason, complicated and expensive manufacturing equipment had to be installed. Furthermore, there were also problems in that it took a long time to sufficiently bond and the productivity was poor.
本発明者は上記問題を解決するため鋭意研究の結果、プ
リプレグにおけるフッ素樹脂層を従来品のようなＰＴＦ
Ｅ単層ではなく、テトラフルオロエチレン−へキサフル
オロプロピレン共重合体（以下、ＦＥＰと称す）または
テトラフルオロエチレン−パーフルオロアルキルビニル
エーテル共重合体（以下、ＰＦＡと称す）から成る層、
ＰＴＦＥ層および第２のＦＥＰ層の複層構造とすること
により、所期の目的を達成し得ることを見い出し、本発
明を完成するに至ったものである。As a result of intensive research in order to solve the above problem, the present inventors found that the fluororesin layer in the prepreg was replaced with PTF like conventional products.
E not a single layer, but a layer consisting of a tetrafluoroethylene-hexafluoropropylene copolymer (hereinafter referred to as FEP) or a tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer (hereinafter referred to as PFA),
The present invention was completed based on the discovery that the desired object could be achieved by forming a multilayer structure of a PTFE layer and a second FEP layer.
即ち、本発明に係るプリプレグは布状基材にＦＥＰまた
はＰＦＡの含浸による層が形成されており、更にこの層
上にＰＴＦＥ層およびＦＥＰ層が順次設けられて成るも
のである。That is, the prepreg according to the present invention has a cloth-like base material impregnated with FEP or PFA to form a layer, and a PTFE layer and a FEP layer are sequentially provided on this layer.
そして、本発明はこのプリプレグを用いた多層回路板を
も提供する。この多層回路板は回路板と金属パターンが
上記プリプレグを介して一体化されて成るか、あるいは
回路板相互が上記プリプレグを介して一体化されて成る
ものである。The present invention also provides a multilayer circuit board using this prepreg. This multilayer circuit board is formed by integrating a circuit board and a metal pattern via the prepreg, or by integrating the circuit boards together via the prepreg.
本発明には従来からプリプレグ材料として使用されてい
た布状基材をそのまま用いることができる。かような布
状基材の具体例としてはガラス繊維、アラミド繊維、ア
ルミナ繊維、ボロン繊維、窒化ホウ素繊維、シリコーン
カーバイト繊維、チタニア繊維等の無機繊維、あるいは
芳香族ポリアミド繊維（アラミド繊維）、ＰＴＦＥ繊維
、超高分子量ポリエチレン繊維、芳香族ポリエステル繊
維等の有機繊維の単独またはこれらの２種以上を用いた
複合糸から成る織布や不織布を挙げることができる。こ
の基材の厚さは適宜選択するが、通常、約５０〜２００
μｍである。In the present invention, cloth-like base materials conventionally used as prepreg materials can be used as they are. Specific examples of such cloth-like base materials include inorganic fibers such as glass fiber, aramid fiber, alumina fiber, boron fiber, boron nitride fiber, silicone carbide fiber, and titania fiber, or aromatic polyamide fiber (aramid fiber). Examples include woven fabrics and nonwoven fabrics made of composite yarns using organic fibers such as PTFE fibers, ultra-high molecular weight polyethylene fibers, and aromatic polyester fibers alone or in combination with two or more of these. The thickness of this base material is selected appropriately, but is usually about 50 to 200 mm.
It is μm.
本発明に係るプリプレグは布状基材にＦＥＰの含浸によ
る層（以下、この層を第１ ＦＥＰ層と称す）またはＰ
ＦＡの含浸による層が形成される。The prepreg according to the present invention is a layer formed by impregnating a cloth-like base material with FEP (hereinafter, this layer is referred to as the first FEP layer) or a layer formed by impregnating a cloth-like base material with FEP
A layer is formed by impregnation with FA.
布状基材へのＦＥＰあるいはＰＦＡの含浸量が多い場合
、これらは基材を構成する繊維に浸透すると共に基材表
面に比較的厚手の層を形成し、また、基材が網目を有す
るときはこの網目を閉塞することもある。一方、ＦＥＰ
あるいはＰＦＡの浸透量が少ない場合、これらは基材を
構成する繊維に浸透し且つその表面に比較的薄手の層を
形成する。When a large amount of FEP or PFA is impregnated into a cloth-like base material, these penetrate into the fibers that make up the base material and form a relatively thick layer on the surface of the base material. may occlude this mesh. On the other hand, FEP
Alternatively, if the amount of PFA permeated is small, it permeates into the fibers constituting the base material and forms a relatively thin layer on its surface.
布状基材へのＦＥＰ、ＰＦＡの含浸は、例えば、（イ）
布状基材をＦＥＰあるいはＰＦＡディスバージョン中に
浸漬して引上げ、次いで、ＦＥＰあるいはＰＦＡの融点
以上の温度で加熱する方法（所望により、浸漬および加
熱を繰り返す）、（ロ）布状基材にＦＥＰあるいはＰＦ
Ａディスバージョンをスプレー塗布し、次いで、ＦＥＰ
あるいはＰＦＡの融点以上の温度で加熱する方法（所望
により、塗布および加熱を繰り返す）、（ハ）布状基材
とＦＥＰあるいはＰＦＡシートを重ね合わせ、次いで、
ＦＥＰあるいはＰＦＡの融点以上の温度で加熱する方法
、等によって行うことができる。For example, impregnation of FEP and PFA into a cloth-like base material is performed by (a)
A method of dipping a cloth-like base material in FEP or PFA dispersion, pulling it up, and then heating it at a temperature equal to or higher than the melting point of FEP or PFA (repeating dipping and heating if desired); FEP or PF
Spray application of A disversion, then FEP
Alternatively, a method of heating at a temperature equal to or higher than the melting point of PFA (repeating application and heating as desired); (c) laminating the cloth-like base material and FEP or PFA sheet;
This can be carried out by heating at a temperature higher than the melting point of FEP or PFA.
かように布状基材に形成された第１ ＦＥＰ層あるいは
ＰＦＡ層上には、更にＰＴＦＥ層およびＦＥＰ層（以下
、このＦＥＰ層を第２ＦＥＰ層と称す）が順次形成され
る。これらＰＴＦＥ層および第２ＦＥＰ層の形成は、Ｐ
ＴＦＥあるいはＦＥＰのデイスパージョンやフィルムを
用い、上記（イ）〜（ハ）の方法に準じて行うことがで
きる。On the first FEP layer or PFA layer thus formed on the cloth-like base material, a PTFE layer and an FEP layer (hereinafter, this FEP layer will be referred to as a second FEP layer) are successively formed. The formation of these PTFE layers and the second FEP layer
This can be carried out using a TFE or FEP dispersion or film according to the methods (a) to (c) above.
布状基材へのこれらフッ素樹脂の含浸率は種々の要因に
応じて適宜設定するが、通常、約５５〜８５％である。The impregnation rate of these fluororesins into the cloth-like base material is appropriately set depending on various factors, but is usually about 55 to 85%.
この含浸率は布状基材の含浸前の重量Ｍ０、第１ ＦＥ
Ｐ層あるいはＰＦＡ層、ＰＴＦＥ層および第２ＦＥＰ層
形成後の布状基材の重量Ｍ、を用い下記式（Ｉ）により
算出する。This impregnation rate is based on the weight M0 of the fabric base material before impregnation, the first FE
It is calculated by the following formula (I) using the weight M of the cloth-like base material after the formation of the P layer, the PFA layer, the PTFE layer, and the second FEP layer.
８層および第２ＦＥＰ層を形成するためのＦＥＰあるい
はＰＦＡ、ＰＴＦＥおよびＦＥＰの含浸比率は含浸樹脂
総重量中に占める第１ ＦＥＰ層あるいはＰＦＡ層形成
用ＦＥＰあるいはＰＦＡの割合が約５〜２５重量％、Ｐ
ＴＦＥ層形成用ＰＴＦＥの割合が約６０〜９３重量％、
第２ＦＥＰＮ形成用ＦＥＰの割合が約２〜１５重量％に
なるように設定することができる。The impregnation ratio of FEP or PFA, PTFE and FEP for forming the 8 layers and the second FEP layer is such that the proportion of FEP or PFA for forming the first FEP layer or PFA layer is about 5 to 25% by weight in the total weight of the impregnated resin. , P
The proportion of PTFE for forming the TFE layer is about 60 to 93% by weight,
The proportion of FEP for forming the second FEPN can be set to about 2 to 15% by weight.
第１図は本発明に係るプリプレグの構造を模式的に示す
断面図であり、プリプレグ７は布状基材１に先ず第１
ＦＥＰ層（あるいはＰＦＡ層）２が形成され、更に、該
層２上にＰＴＦＥ層３および第２ ＦＥＰ層４が形成さ
れている。FIG. 1 is a cross-sectional view schematically showing the structure of the prepreg according to the present invention.
A FEP layer (or PFA layer) 2 is formed, and a PTFE layer 3 and a second FEP layer 4 are further formed on the layer 2.
本発明のプリプレグは第１図に示すように布状基材にＦ
ＥＰあるいはＰＦＡ、ＰＴＦＥおよびＦＥＰの三者を適
用した１枚ものであってもよいが、これの所定枚数を重
ね合わせ一体化せしめた複層タイプのものであってもよ
い。この一体化に際してはプリプレグ間にＦＥＰシート
のような低融点フッ素樹脂シート等を接着剤として介在
させることもできる。The prepreg of the present invention is applied to a cloth-like base material as shown in FIG.
It may be a single sheet made of EP, PFA, PTFE, and FEP, or it may be a multilayer type in which a predetermined number of these sheets are stacked and integrated. During this integration, a low melting point fluororesin sheet such as an FEP sheet may be interposed between the prepregs as an adhesive.
本発明は多層回路板も提供する。この多層回路板は、例
えば、第２図に示すように回路板５と金属パターン６を
上記プリプレグ７を介して重ね合わせ、プリプレグ７の
最外層である第２ＦＥＰ層の融点以上の温度に加熱する
と共に加圧して一体化した構造を有する。The invention also provides a multilayer circuit board. This multilayer circuit board is produced by, for example, stacking a circuit board 5 and a metal pattern 6 with the prepreg 7 interposed therebetween as shown in FIG. It has a structure in which it is pressurized and integrated.
ここで用いる回路板５は何等格別である必要はなく、従
来から多層回路板の製造に用いられているものを使用で
きる。この回路板の代表的な具体例としては、第２図中
に図示した如くガラスクロスのような布状基材にＰＴＦ
Ｅを含浸せしめたプリプレグ８の表面に金属箔を積層し
、この金属箔をパターン加工９したものを挙げることが
できる。なお、本発明に係るプリプレグを用いて得られ
る多層回路板は、厚み分布が均一であるという利点も確
認されている。この理由は必ずしも明らかではないが、
多層回路板を得る際の加熱加圧時にプリプレグの最外層
である第２ＦＥＰ層が熱流動し、回路板の平面形状に良
く追従するためと推論される。The circuit board 5 used here does not need to be of any special type, and any circuit board conventionally used in the manufacture of multilayer circuit boards can be used. As a typical example of this circuit board, as shown in Fig. 2, PTF is used on a cloth-like base material such as glass cloth.
An example is one in which a metal foil is laminated on the surface of a prepreg 8 impregnated with E, and this metal foil is patterned 9. It has also been confirmed that the multilayer circuit board obtained using the prepreg according to the present invention has the advantage of having a uniform thickness distribution. The reason for this is not necessarily clear, but
It is inferred that this is because the second FEP layer, which is the outermost layer of the prepreg, undergoes thermal fluidization during heating and pressurization when obtaining a multilayer circuit board, and follows the planar shape of the circuit board well.
回路板を得るための金属箔のパターン化は従来からのプ
リント回路板の製造と同様に剥離現像型フォトレジスト
、溶剤現像型フォトレジストまたはアルカリ現像型フォ
トレジストを用いる方法で行うことができる。Patterning of the metal foil to obtain a circuit board can be carried out in the same manner as in the conventional manufacture of printed circuit boards, using a peel-and-develop photoresist, a solvent-developable photoresist, or an alkali-developable photoresist.
例えば、積層板の金属箔表面にアルカリ現像型フォトレ
ジスト層を形成し、その上からフォトマスクを介してパ
ターン状に露光せしめ、次いでフォトレジストの未露光
部を溶解除去して金属箔を部分的に露出せしめ、その後
金属箔の露出部をエツチングにより除去し、更に、フォ
トレジストの露光部を溶剤により除去すれば、フォトレ
ジストの露光パターンに対応するパターン状の金属箔回
路を有する回路板を得ることができる。For example, an alkali-developable photoresist layer is formed on the surface of the metal foil of a laminate, exposed to light from above in a pattern through a photomask, and then the unexposed portions of the photoresist are dissolved and removed to partially remove the metal foil. After that, the exposed portion of the metal foil is removed by etching, and the exposed portion of the photoresist is further removed with a solvent to obtain a circuit board having a patterned metal foil circuit corresponding to the exposure pattern of the photoresist. be able to.
第３図は本発明に係る多層回路板の他の実例を示し、回
路板５の所定枚（図では２枚）をプリプレグ７を介して
一体化させたものである。FIG. 3 shows another example of the multilayer circuit board according to the present invention, in which predetermined circuit boards 5 (two in the figure) are integrated via a prepreg 7.
（発明の効果）
本発明はこのように布状基材にＦＥＰ層あるいはＰＦＡ
層、ＰＴＦＥ層およびＦＥＰ層を順次設けた構成として
あり、最外層がＦＥＰであるので、その接着に際し低温
低圧で充分に作業できるばかりでなく、作業時間も短縮
できる。(Effects of the Invention) The present invention thus provides an FEP layer or a PFA layer on a cloth-like base material.
Since the outermost layer is FEP, not only can the adhesion be carried out at low temperature and pressure, but also the working time can be shortened.
以下、実施例により本発明を更に詳細に説明する。 Hereinafter, the present invention will be explained in more detail with reference to Examples.
実施例
（プリプレグの製造）
厚さ約５０μｍのガラスクロスをＦＥＰ粉末濃度４０重
量％の水性ディスバージョン中に浸漬して引上げ、温度
３２０°Ｃで２分間加熱して、第１ＦＥＰ層を形成する
。Example (Production of Prepreg) A glass cloth with a thickness of about 50 μm is immersed in an aqueous dispersion having a FEP powder concentration of 40% by weight, pulled up, and heated at a temperature of 320° C. for 2 minutes to form a first FEP layer.
次に、これをＰＴＦＥ粉末濃度６０重量％の水性ディス
バージョン中に浸漬して引上げ、温度３８０°Ｃで２分
間加熱する。そして、この浸漬と加熱を更に３回繰り返
し行うことにより、ＰＴＦＥ層を形成する。Next, this is immersed in an aqueous dispersion having a PTFE powder concentration of 60% by weight, pulled up, and heated at a temperature of 380° C. for 2 minutes. Then, by repeating this dipping and heating three more times, a PTFE layer is formed.
次いで、これを上記と同しＦＥＰディスバージョン中に
浸漬して引上げ、温度３２０°Ｃで２分間加熱して、第
２ＦＥＰ層を形成することにより、厚さ７２μｍのプリ
プレグＡを得る。Next, this is immersed in the same FEP dispersion as above, pulled up, and heated at a temperature of 320° C. for 2 minutes to form a second FEP layer, thereby obtaining a prepreg A having a thickness of 72 μm.
このプリプレグにおけるフン素樹脂の含浸率は７０％で
あり、ガラスクロスに含浸されたフッ素樹脂の総重量中
に占める第１ ＦＥＰ層形成用ＦＥＰ、ＰＴＦＥ層形成
用ＰＴＦＥおよび第２ ＦＥＰ層形成用ＦＥＰの割合は
、１４．５重量％、７８．５重置％および７重量％であ
った。The impregnation rate of the fluororesin in this prepreg is 70%, and the FEP for forming the first FEP layer, the PTFE for forming the PTFE layer, and the FEP for forming the second FEP layer account for 70% of the total weight of the fluororesin impregnated into the glass cloth. The proportions were 14.5% by weight, 78.5% by weight and 7% by weight.
（回路板の製造）
厚さ約５０μｍのガラススクロスをＰＴＦＥ粉末濃度６
０重量％の水性ディスバージョン中に浸漬して引上げ、
温度３８０°Ｃで２分間加熱する。(Manufacturing of circuit boards) Glass cloth with a thickness of about 50 μm is made of PTFE powder with a concentration of 6
immersed in 0% by weight aqueous dispersion and pulled up;
Heat at 380°C for 2 minutes.
そして、更に、この浸漬および加熱を４回繰り返し行い
、厚さ約７０μｍ、ＰＴＦＥ含浸率６８％のプリプレグ
Ｂを得る。Further, this dipping and heating are repeated four times to obtain a prepreg B having a thickness of about 70 μm and a PTFE impregnation rate of 68%.
次に、このプリプレグＢを１１枚を重ね合わせ、これら
の両側に厚さ１８μｍの銅箔を配置し、温度３８５°Ｃ
１圧力５０ｋｇ／−の条件で３０分間加熱加圧すること
により、プリプレグＢ相互およびプリプレグＢと銅箔を
一体化して積層板を得る。Next, 11 sheets of this prepreg B were stacked, copper foil with a thickness of 18 μm was placed on both sides, and the temperature was 385°C.
By heating and pressurizing for 30 minutes at a pressure of 50 kg/-, the prepregs B are integrated with each other and the prepreg B and the copper foil to obtain a laminate.
次いで、この積層板の両面の銅箔をアルカリ現像型フォ
トレジストを用いてパターン加工し、更に、これをフッ
素樹脂の表面接着処理剤である潤工社製のテトラエッチ
溶液中に３０秒間浸漬処理して、回路板を得る。Next, the copper foil on both sides of this laminate was patterned using an alkali-developable photoresist, and then immersed for 30 seconds in a Tetra-etch solution manufactured by Junkosha, which is a surface adhesive treatment agent for fluororesin. , get a circuit board.
（多層回路板の製造）
上記回路板の両面にプリプレグＡおよび厚さ１８μｍの
銅箔を配置し、温度３００°Ｃ１圧力１５ｋｇ／ｃｉｌ
ｌの条件で１５分間加熱加圧して、これらを一体化する
。(Manufacture of multilayer circuit board) Prepreg A and copper foil with a thickness of 18 μm are placed on both sides of the above circuit board, and the temperature is 300°C and the pressure is 15kg/cil.
Heat and pressurize for 15 minutes under the conditions of 1 to integrate these.
次に、両外面の銅箔をアルカリ現像型フォトレジストを
用いてパターン加工することにより、多層回路板を得た
。Next, a multilayer circuit board was obtained by patterning the copper foils on both outer surfaces using an alkali-developable photoresist.
この多層回路板における銅箔残留部分での厚み分布は±
０．０２ｍｍであった。なお、この厚み分布はＪＩＳ
Ｃ６４８１に準じた測定位置の１０個所の厚さを測定
することにより求めた。The thickness distribution of the remaining copper foil portion of this multilayer circuit board is ±
It was 0.02 mm. Note that this thickness distribution is based on JIS
It was determined by measuring the thickness at 10 measurement positions according to C6481.
比較例
多層回路板の製造に際し、回路板の両面乙こプリプレグ
Ｂおよび厚さ１８μｍの銅箔を配置した。Comparative Example When manufacturing a multilayer circuit board, prepreg B and 18 μm thick copper foil were placed on both sides of the circuit board.
そして、これらを一体化させるためには温度３９０゛Ｃ
１圧力５０ｋｇ／ｃｆｆｌの条件で４５分間加熱加圧す
る必要があった。この多層回路板の厚み分布は±０゜０
４ｍｍであった。In order to integrate these, the temperature must be 390°C.
It was necessary to heat and pressurize for 45 minutes at a pressure of 50 kg/cffl. The thickness distribution of this multilayer circuit board is ±0°0
It was 4 mm.
第１図は本発明に係るプリプレグの実例を模式的に示す
断面図、第２図および第３図は本発明に係る多層回路板
の実例を示す断面図である。FIG. 1 is a sectional view schematically showing an example of a prepreg according to the invention, and FIGS. 2 and 3 are sectional views showing an example of a multilayer circuit board according to the invention.
Claims (3)
オロプロピレン共重合体またはテトラフルオロエチレン
−パーフルオロアルキルビニルエーテル共重合体による
層が形成されており、更に該層上にポリテトラフルオロ
エチレン層およびテトラフルオロエチレン−ヘキサフル
オロプロピレン共重合体層が設けられて成るプリプレグ
。(1) A layer made of a tetrafluoroethylene-hexafluoropropylene copolymer or a tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer is formed on a cloth-like base material, and a polytetrafluoroethylene layer and a tetrafluoroethylene layer are further formed on the layer. A prepreg comprising a fluoroethylene-hexafluoropropylene copolymer layer.
グを介して一体化されて成る多層回路板。(2) A multilayer circuit board in which a circuit board and a metal pattern are integrated via the prepreg according to claim 1.
一体化されて成る多層回路板。(3) A multilayer circuit board in which the circuit boards are integrated with each other via the prepreg according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29673090A JPH04168127A (en) | 1990-10-31 | 1990-10-31 | Prepreg and multi-layer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29673090A JPH04168127A (en) | 1990-10-31 | 1990-10-31 | Prepreg and multi-layer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04168127A true JPH04168127A (en) | 1992-06-16 |
Family
ID=17837354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29673090A Pending JPH04168127A (en) | 1990-10-31 | 1990-10-31 | Prepreg and multi-layer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04168127A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2019049519A1 (en) * | 2017-09-06 | 2020-08-13 | 日本ピラー工業株式会社 | Circuit board and manufacturing method thereof |
-
1990
- 1990-10-31 JP JP29673090A patent/JPH04168127A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2019049519A1 (en) * | 2017-09-06 | 2020-08-13 | 日本ピラー工業株式会社 | Circuit board and manufacturing method thereof |
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