JPH04167555A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a resistor which is large in resistance and small in area to be ensured without increasing manufacturing processes in number by a method wherein a resistive element is provided with a low impurity concentration region formed between high impurity concentration regions, and these regions are formed at the same time when the low and the high impurity concentration regions of a MOS transistor are formed. CONSTITUTION:An N<-> region 3 of low impurity concentration serving as a resistive element is formed at the same time with a low impurity concentration drain region of LDD structure. Then, a side wall 11 of SiO2 film is formed around a gate electrode 10, and an N<+> region 4 of high impurity concentration is formed through the implantation of arsenic ions using a resist 8 as a mask. Concurrently, a source/drain regions 4 of a MOS transistor are formed using the side wall 11 and the gate electrode 10 as a mask through the above ion implantation. By this setup, a resistive element can be enhanced in resistance and also lessened in occupying area without increasing processes in number.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a method for manufacturing highly integrated semiconductor devices, and in particular, relates to a method for manufacturing resistive elements using conventional techniques. Although there is a demand for miniaturization of elements, one of the advantages of MOS transistors is that the drain force (low impurity concentration region spreads more in the channel direction than the high impurity concentration region) like the LDD structure is required for high breakdown voltage and high reliability. In the nine-resistance element, the active region formed on the substrate,
For example, in the structure shown in FIG. 3, an active region (n region) formed on the substrate is used. ) is a cross-sectional view taken along the line BB'.
1 is a P-type silicon base, Fih2 is an isolation insulator, IU4 is an active region (n10 region), 5 is an insulator IL, 6 is a contact hole, and 7 is a wiring.

Problems to be Solved by the Invention However, with conventional resistive elements, the sheet resistance in the n area is low, on the order of several tens to 100 (Ω/unit), and it is difficult to secure a sufficient resistance value and miniaturize the resistive element. Furthermore, forming a region with a low impurity concentration in order to obtain a high resistance value has the problem of increasing the number of process steps. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can ensure resistance. a step of simultaneously forming a low impurity concentration region and a low impurity concentration region of the drain of the Mo3 transistor; This method of manufacturing a semiconductor device includes a step of simultaneously forming a high impurity concentration region and a high impurity concentration region that will become the source and drain of the MO8 transistor. The low impurity concentration region of the drain of the MOS transistor can be miniaturized by ensuring a sufficiently large resistance in the small occupied area of the low impurity concentration region formed between the regions. Embodiment 'J1 Figures (a) and (b) show the structure of a semiconductor device in an embodiment of the present invention. Figure 2 (a) ) to (d) are process cross-sectional views for explaining the manufacturing method of this example.
Detailed explanation of the present invention with reference to the drawings is shown in FIG.
After forming an isolation insulating film 2 on a portion of the P-type silicon substrate 1 that will become an isolation region, a gate oxide film 9 and a polysilicon film are formed to form a MOS transistor.
After patterning the gate electrode using resist, the gate electrode 10 is formed by etching. Next, in FIG. 2(b), the n-region 3, which is a low impurity region that will become a resistance element, is treated with phosphorus or arsenic at a dose of IEI3. ~3
By ion implantation of about E 13 (cm-2), L
This layer is formed at the same time as the low impurity concentration region of the drain of the DD structure.The sheet resistance of this n-region is 2 to 1O (KΩ/unit)
Next, in FIG. 2(c), Si is placed around the gate electrode 10.
Forming the sidewall 11 with a 0g film 4 Next, a pattern is formed using the resist 8.

Next, in FIG. 2(d), using this resist 8 as a mask, the n0 region 4, which will be a high impurity region, is treated with arsenic at a dose of 3 E.
I 5 to 6 El 5 (cm-2) is formed by ion implantation. Through this ion implantation, the source/drain regions of the MoS transistor are simultaneously formed using the sidewall 11 formed by the 5ide film and the gate voltage tf 110 as a mask. An interlayer insulating film 5 is deposited on the plate on which a contact window 6 for connection with the Ln+ region is formed.
Figure 1 (a), (b)) According to this embodiment, ζ
It is possible to easily increase the resistance value of the resistor element and reduce the area of the resist pattern 8.
Due to its shape, the resistance value can be easily changed.
Although it can be manufactured without increasing the number of steps, the embodiment shown above shows a specific example of the present invention, and is not limited thereto.It has a structure in which the conductivity type is completely reversed from that of this embodiment. However, it is fine if the structure of the MOS transistor is such that the drain has a low impurity concentration region and a high impurity concentration region of the same conductivity type. As explained above, by using the method of manufacturing a semiconductor device of the present invention, it is possible to easily increase the resistance value without increasing the number of steps, and it is possible to obtain a highly integrated semiconductor device.

[Brief explanation of drawings]

Figures 1 (a) and (b) are a plan view and cross section of a semiconductor device according to an embodiment of the present invention @ Figures 2 (a) to (d) are process cross sections showing the same manufacturing method Figure 3 (a) , (b) is a plan view and a cross-sectional view of a conventional semiconductor device.P-type silicon substrate 2. Isolation insulating film 3.
・n-region [4...n-ten region destruction 5...insulating film 6...
・Contact i7...Wiring 8-...Resist. Name of agent: Patent attorney Akira Okaji and two others 1---
P Si Live Meal 2--- MinIIIJe Summer Shoes 3-71- 11 Ward 4--- n' li 1E 7-&! malt

Claims (1)

[Claims] a step of simultaneously forming a low impurity concentration region of a second conductivity type to become a resistance element and a low impurity concentration region of a drain of a MOS transistor on a semiconductor substrate of a first conductivity type; a second conductivity type high impurity concentration region at a contact portion between the low impurity concentration region of the mold and the wiring;
A method of manufacturing a semiconductor device, comprising the step of simultaneously forming regions with high impurity concentration that will become the source and drain of the MOS transistor.