JPH04167164A - Inter-processor connecting device - Google Patents

Abstract

PURPOSE:To attain the mutual accesses to the resources of the memories, etc., at a high speed between the 1st and 2nd processors by converting the address applied to the access of the 1st processor into a prescribed address of the 2nd processor through a mapping circuit. CONSTITUTION:The inter-processor connecting devices 20 and 21 are provided opposite to the processors 22 and 23 respectively and connected to these processors via the processor buses 24 and 25. At the same time, the devices 20 and 21 are connected to each other via a transfer line 26. When the processor 22 wants to have an access to the memory resources, etc., allocated to an address space 21-2 in an address space 21-1 of the processor 23, the processor 22 is defined to have an access to a specific address space 20-3 in an address space 20-1 of the processor 22 itself. Under such conditions, a mapping circuit 2 of the device 20 connected to the processor 22 is set to perform the mapping of both spaces 20-3 and 21-2. Thus the connection is easily secured between the processors of different bus forms.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device for coupling processors, and more specifically, for coupling processors together so that they can access resources such as memory of other processors. The present invention relates to an inter-processor coupling device.

[Conventional technology]

2. Description of the Related Art Conventionally, systems having a multiprocessor configuration in which a plurality of processors are connected to each other and each processor is configured to perform distributed processing or parallel processing have been employed in various fields. Conventionally, as a coupling method between processors in this type of system, a method as shown in FIG. 4 and a method as shown in FIG. 5 have been generally adopted.

The method shown in FIG. 4 connects a processor 30 and a processor 31 via a shared memory 32, and stores input data for processing by each processor 30, 31, output data such as calculation results, and control data. flag data, etc. are stored in the shared memory 32, and each processor 30, 31 can share the data by reading it directly from the shared memory 32. Note that each processor 30.31 receives a write request signal 33.31. Read request signal 34. Address signal 35. The data signal 36 allows the shared memory 32 to be used in the same manner as memory (not shown) dedicated to each processor, without being aware of other processors.

Furthermore, the system shown in FIG.
1 through a communication line 44, and the communication line 44 is connected under the communication control program 42.43 provided in each processor.
It allows data to be exchanged with each other via , allowing distributed and parallel processing to be performed. In this case, each processor 40.41 has a communication control program 42.4.
3, multiple pieces of data are sent and received according to the data width of the communication interface, and the data on the communication interface is the processor address for sending and receiving,
Data address, number of data words.

It is in a data block format that combines data, etc. 9 [Problems to be Solved by the Invention] Conventionally, the above-mentioned methods have been used to connect processors, but each method has the following problems.

In the system using shared memory shown in Figure 4, each processor is closely connected to one memory circuit, so both processors must be physically close to each other, which is difficult to construct a distributed processing system. This is a big constraint. Furthermore, it is necessary to electrically match each processor to the interface of the memory circuit, making it difficult to connect processors of different formats, such as bus formats. For example, a processor board and VME that comply with multipath-■ standards.
It is difficult to connect processor boards that conform to the BUS standard.

Furthermore, in the method using the communication interface shown in Figure 5, it is not particularly difficult to connect processors of different types as long as only the communication interface is compatible, and it is not particularly difficult to connect processors that are far apart. Although it is possible to combine them, since a communication control program is involved in each processor, data exchange inevitably takes a long time.

The present invention has been made in view of the above circumstances, and its purpose is to enable each processor to access resources such as memory of other processors at high speed even if the processors are separated by different bus formats. An object of the present invention is to provide an inter-processor coupling device capable of coupling processors in this manner.

[Means to solve the problem]

In order to achieve the above object, the inter-processor coupling device of the present invention comprises: a first FIFO group that is connected between a processor bus and a transmission/reception transmission line and holds information for each type;
a transmitting circuit that sends the information held in the FIFO group to the transmitting/receiving transmission line; a receiving circuit that receives the information sent via the transmitting/receiving transmission line; and classifying the information received by the receiving circuit. The second to hold every
a FIFO group, and after the first FIFO group holds information outputted to the processor bus by a first processor connected to the processor bus in order to access a specific address space, the transmission circuit a first control means for causing the transmission to be transmitted to the transmitting/receiving transmission line; and when the information held in the second FIFO group is information related to resource access, the first controlling means transmits the information to the first processor via the processor bus based on the information held in the second FIFO group. After accessing the resources and storing the obtained result data in the first FTFO group during a read operation, the transmitting circuit sends it out to the transmitting/receiving transmission line, and the second FIFO
a second control means for outputting the result data to the processor bus when the information held in the FO group is read result data; The address of the information output to the bus is converted into a predetermined address of the second processor connected via the transmission/reception transmission line and another inter-processor coupling device, or the information received by the reception circuit is and a mapping circuit that converts an address related to the output of the second processor into a predetermined address of the first processor.

[Effect]

In order to facilitate understanding of the operation of the inter-processor coupling device of the present invention, an example will be described in which two processors are coupled via two inter-processor coupling devices and a transmission/reception transmission line.

When the first processor outputs an address, a control flag indicating an operation such as writing or reading, data to be written at the time of writing, etc. to the processor bus in order to access a specific address space that is the mapping space of the second processor side resource. , the first control means of the first inter-processor coupling device connected to the processor bus of the first processor converts the information outputted to the processor bus into a predetermined address, that is, the mapped light by a mapping circuit. After converting into the address of the second processor, other types of information are held as they are in the first FIFO group, and then sent out to the transmitting/receiving transmission line by the transmitting circuit.

The above-mentioned information sent to the transmitting/receiving transmission line is received by the receiving circuit in the second inter-processor coupling device connected thereto, and is held for each type of information in the second FIFO group of the device. The second control means accesses the resources of the second processor via the processor bus connected to the device based on the information held in the second FIFO group. That is, at the time of writing, the resource of the second processor is written via the processor bus, and this means that the first processor has written to the resource of the second processor. Further, during a read operation, the second control means stores the result data obtained as a result of the access in the first FIFO group of the device, and then causes the transmitting circuit of the device to send the result data to the transmitting/receiving transmission line.

The above result data sent to the transmitting/receiving transmission line is received by the receiving circuit in the first inter-processor coupling device and held in the second FIFO group of the device, and the second control means of the device controls this data. The result data held in the second FIFO group is output onto the processor bus. This means that the first processor has read the second processor side resources.

In the above configuration, the mapping circuit provided in the first processor converts the address accessed by the first processor into a predetermined address of the second processor.
It is also possible to send the address accessed by the processor as it is to the second inter-processor coupling device, and convert it into a predetermined address of the second processor by the mapping circuit of the second inter-processor coupling device.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an inter-processor coupling device of the present invention, and FIG. 2 is a block diagram of a multiprocessor system in which two processors are coupled using two inter-processor coupling devices shown in FIG. FIG. 2 is a block diagram showing an example.

As shown in FIG. 2, the inter-processor coupling devices 20 and 21 of this embodiment are provided corresponding to the processors, and are connected to the corresponding processors 22 and 23 via processor buses 24 and 25, so that they can transmit and receive data between each other. They are connected by a transmission line 26. Referring to FIG. 1, the inter-processor coupling device 1 (20, 21) includes connection terminals T1 to T6 with the processor bus side, connection terminals Tll and T12 with the transmission/reception transmission line 26 side, and internal Specifically, window control circuit 1. Mapping circuit 2. Address FIF
O (first-in, first-out format register) 3゜Data FIFO 4
, control flag FIFO5, transmission circuit 6. Receiving circuit 7. Address PIFO8, data FIFO9, control flag FI
It includes a FOIO and processor timing control circuit 11.

Next, a more detailed configuration and operation of the inter-processor coupling device of this embodiment configured as described above will be explained.

Now, the processor 22 in FIG.
-2, when the processor 22 wants to access the memory resources of the processor 23 allocated to the processor 20-2, the processor 22 accesses a specific address space 20-1 in the address space 20-1 of its own processor.
3, and processor 2
The mapping circuit 2 in the interprocessor coupling device f20 connected to the processor f20 is set to perform mapping between the specific address space 20-3 and the address space 21-2. Conversely, processor 23 uses address space 2 of processor 22.
If you want to access the memory resources of the processor 22 allocated to the address space 20-2 of 0-1,
The processor 23 uses its own address space 21-1.
The mapping circuit 2 in the inter-processor coupling bag M21 connected to the processor 23 maps the specific address space 21-3 and the address space 20-2. set to do so. Note that the specific address space 20
-3 is assigned to an address space other than the one occupied by the resources owned by the processor 22, and similarly, the specific address space 21-3 is assigned to an address space other than the one occupied by the resources owned by the processor 23. assigned to a space.

Now, mutual access forms between the processors 22 and 23 in the multiprocessor system shown in FIG. , for each of them, ■ data writing ■ data reading can be considered, but (1) ■, ■ and (2) ■, ■
The operations are the same, so (1) (1) and (1) will be taken as examples, and their operations will be explained below.

(11.■; Access related to writing data to the resources of the processor 23 by the processor 22 When the processor 22 in FIG. 2 writes data to the resources of the processor 23, the processor 22 accesses the In order to access the corresponding address in the specific address space 20-3 shown in FIG. is output to the processor bus 24.

Inter-processor coupling bag F! 120 receives those signals from the processor bus 24 via terminals Tl-T4, and sends the address Sl and timing signal S4 to the window control circuit l.
to, data S2 to data FIF04, control flag S3
is sent to the control flag FIFO5.

When the window control circuit 1 receives the timing signal S4, the window control circuit 1 determines whether the address S1 is a value indicating an address included in the specific address space 20-3, and if the address value is not included therein, no further action is taken. Neither. On the other hand,
When the address value is included in the specific address space 20-3, the address Sl is sent to the mapping circuit 2, and the mapping circuit 2 converts this address S1 into the address space 21- of FIG. 3 according to a preset conversion rule. It is converted into an address Sl' indicating a predetermined area within 2 and sent to address FIFO3. Address 31' after this conversion and terminal T3. Data input from T4 32. Control flag S3 is set to address FIFO 3, data FIFO 4, and control flag FIF, respectively, by FIFO write signal a generated in window control circuit 1 based on the result of the area determination and timing signal S4 in window control circuit 1.
Retained at O5.

The transmitting circuit 6 starts operating in response to the FIFO write signal a, and transfers the data held in PIF03 to PIF5 to the control flags S3. The address Sl' and the data S2 are taken out in this order and transmitted from the terminal Tll to the inter-processor coupling device 21 via the transmitting/receiving transmission line 26 shown in FIG. Then, the transmitting circuit 6 sends a write operation end notification to the processor timing control circuit 11, and the processor timing control circuit 11 responds by sending a write operation end notification C to the terminal T.
6. Reports to processor 22 via processor bus 24.

The above information transmitted via the transmit/receive transmission line 26 is transmitted to the inter-processor coupling bag W! 21 via the terminal T12 of the receiving circuit 7, and the receiving circuit 7 sets the control flag S3.
is stored in the control flag FIFOIO, the address Sl' is stored in the address PIFO8, and the data S2 is stored in the data FIFO9, and a write notification signal d is sent to the processor timing control circuit 11.

The processor timing control circuit 11 includes FIF08 to FIF1
When it is recognized by the write notification signal d that data has been written to 0, the control flag S is transferred from the control flag FIFO 10.
3, and in this case we are writing data, so FI
By sending the FO read signal e to PIF08-1O, the address 81', data S2 . Control flag S3 is set to terminal T1 at a predetermined timing.
．． T3. T4 is output to the processor bus 25 in FIG. 2, and the address space 21-2 in FIG.
Data S2 is written to the resource at address Sl'. In addition, during this writing (the same applies to reading described later), the processor timing control circuit 11 arbitrates with the processor 23 through the terminal T5 for the right to use the accessed resource, and after acquiring the right to use, performs the above-mentioned write operation. This is what we do.

(11.■; Access for reading data from the resources of the processor 23 by the processor 22 When reading data from the resources of the processor 23, the processor 22 in FIG. In order to access the corresponding address in the specific address space 20-3 shown in FIG. Output to 24.

The inter-processor coupling bag U20 sends these signals to the terminal TI.
, T2. T4 is received from the processor bus 24, and the address St and timing signal S4 are sent to the window control circuit l, and the control flag S3 is sent to the control flag PIFO5.

When the window control circuit 1 receives the timing signal S4, the window control circuit 1 determines whether the address Sl is a value indicating an address included in the specific address space 20-3, and if the address value is not included therein, no further action is taken. Neither. On the other hand,
If the address value is included in the specific address space 20-3, the address S1 is sent to the mapping circuit 2, and the mapping circuit 2 converts the address S1 into the address space 21-3 in FIG. 3 according to preset conversion rules. 2 to an address Sl' indicating a predetermined area within 2, and the address F
Send to IFO3. The address 81' after this conversion and the control flag S3 input from the terminal T4 are respectively controlled by the FIFO write signal a generated in the window control circuit l based on the result of the area determination in the window control circuit l and the timing signal S4. It is held in address FIFO3 and control flag FTPO5.

The transmitting circuit 6 starts operating in response to the FIFO write signal a, and transfers the information held in the FIFOs 3 and 5 to the control flag S.
3. The inter-processor coupling bag is taken out in the order of address SL' and sent from terminal Tll via the transmitting/receiving transmission line 26 in FIG. Send to i21.

The above information transmitted via the transmitting/receiving transmission line 26 is received by the receiving circuit 7 via the terminal T12 of the inter-processor coupling bag ji21, and the receiving circuit 7 sets the control flag S3.
is stored in the control flag FIFOIO, address Sl'' is stored in the address PIFO8, and a write notification signal d is sent to the processor timing control circuit 11.

The processor timing control circuit 11 is a FIF08.1
When it is recognized by the write notification signal d that information has been written to 0, the control flag S3 is read from the control flag F I FO10, and in this case, data is read, so the F
By sending the IFO read signal e to PIFO8 and PIFO10, address PIFO8 and control flag FIFO1
, 0, and the control flag S3 are transferred to the terminals T1 . T4 is output to the processor bus 25 in FIG. 2, and data is read from the resource at address S1" in the address space 21-2 in FIG. The control circuit 11 arbitrates with the processor 23 through the terminal T5 for the right to use the resource to be accessed, and after acquiring the right to use, the above-described read operation is performed.

Next, by the read operation described above, the processor bus 2
The data S5 read on 5 is the inter-processor coupling bag f
The processor timing control circuit 11 sends the FIFO write signal f to the data FIFO 4 through the terminal T3 of f121, thereby
The data is stored in data FIFO4. At this time,
At the same time, the processor timing control circuit 11
A control flag S6 indicating that the data written into FO4 is the result of reading is stored in control flag PIFO5 using the FIFO write signal r.

The transmitting circuit 6 starts operating in response to the FIFO write signal f, and controls the control flag S6 held in the control flag PIFO5.
．． The result data S5 held in the data FIFO 4 is taken out in order and sent from the terminal Tll to the transmitting/receiving transmission line 2 in FIG.
Inter-processor coupling bag via 6! Send to 20.

The above information transmitted via the transmitting/receiving transmission line 26 is received by the receiving circuit 7 via the terminal T12 of the inter-processor coupling bag f12o, and the receiving circuit 7 sets the control flag S6.
is stored in the control flag FIFOIO, the result data S5 is stored in the data FIFO 9, and a write notification signal d is sent to the processor timing control circuit 11.

The processor timing control circuit 11 is a FIF09.1
When it is recognized by the write notification signal d that information has been written to 0, the control flag S6 is changed from the control flag PIFOIO.
In this case, the result data is returned, so FI
By sending the FO read signal e to the FIFO 9, the result data S5 held in the data FIFO 9 is output to the processor bus 24 in FIG. is sent to the processor 22. The processor 22 takes in the result data S5 from the processor bus 24 into its own processor at the timing when it recognizes the read operation completion notification g.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various other additions and changes are possible. For example, the mapping circuit 2 is connected to the address PIF
It may be moved to the input side or output side of O8 and convert the address sent from the other processor into a predetermined address of the own processor. Further, the mapping circuit 2 may be configured to be accessible from the own processor, so that the conversion rules can be set and changed freely from the own processor.

〔Effect of the invention〕

As explained above, according to the inter-processor coupling device of the present invention, the following effects can be obtained.

(Since the transmitting/receiving transmission line connecting the transmitting and receiving circuits can be sufficiently long, the processors can be separated and distributed with sufficient physical distance between them, compared to the conventional shared memory system.

(2) This inter-processor coupling device can be designed to suit any type of processor physically as long as the specifications for electrically transmitted and received signals are the same, making it easy to couple processors with different bus formats, etc. I can do it.

(3) Since it operates without a communication control program, high-speed operation is possible.

(4) Write and read operations can be performed on the resources of other processors as if they were the resources of the own processor. Therefore, distributed processing and parallel processing with shared data are possible without the need for special hardware such as shared memory, and not only memory but all resources can be shared, and only processors with limited Tl0 etc. can be used. By eliminating this restriction, it is possible to easily increase the efficiency of distributed processing and parallel processing by averaging tasks and processing loads.

6) There is basically no need to be aware of the operations on the own processor's resources and the operations on the resources of other processors.
Since they can apparently operate as resources of a second processor, they can be handled using the concept of a program.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a block diagram showing an example of a multiprocessor system in which two processors are connected using two inter-processor coupling devices shown in the figure. FIG. 4 and 5 are explanatory diagrams of conventional examples. In the figure, 1... Window control circuit 2... Mapping circuit 3. 8... Address FIFO 4, 9... Data FIFO 5, 10... Control flag FIFO 6... Transmission circuit 7... - Receiving circuit 11...processor timing control circuits T1 to T6.
Tl 1. Tl2...Terminal 20.21...Inter-processor coupling device 22.23...Processor 24.25...Processor bus 26...Transmission/reception transmission line

Claims (1)

[Claims] A first FIFO group that is connected between the processor bus and the transmission/reception transmission line and holds information by type; and a first FIFO group that is connected between the processor bus and the transmission/reception transmission line; a transmission circuit that sends out information to the transmission line; a reception circuit that receives information sent via the transmission/reception transmission line; a second FIFO group that holds information received by the reception circuit for each type; Information outputted to the processor bus by a first processor connected to the processor bus in order to access a specific address space is held in the first FIFO group, and then transmitted to the transmitting/receiving transmission line by the transmitting circuit. a first control means for accessing the resources of the first processor via the processor bus based on the information held in the second FIFO group when the information is information related to resource access; , during a read operation, the obtained result data is stored in the first FIFO group, and then sent out to the transmitting/receiving transmission line by the transmitting circuit;
a second control means for outputting the result data to the processor bus when the information held in the FO group is read result data; The address of the information output to the bus is converted into a predetermined address of the second processor connected via the transmission/reception transmission line and another inter-processor coupling device, or the information received by the reception circuit is An inter-processor coupling device comprising: a mapping circuit that converts an address related to the output of the second processor into a predetermined address of the first processor.