JPH0573509A - Inter-processor communication system - Google Patents

Abstract

PURPOSE:To obtain the inter-processor communication system which can send data to plural slave processors at the same time. CONSTITUTION:When a master processor 10 sends data to the slave processors 20, the data to be sent are written in the respective 2-PORT memories 23 of the slave processors 20 respectively and the master processor 10 interrupts the slave processors 20 at the same time; and the slave processors 20 receives the interruption from the master processor 10 and read the sent data out of the 2-PORT memory 23 to receive the data from the master processor at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interprocessor communication system in a multiprocessor system.

[0002]

2. Description of the Related Art FIG. 4 shows, for example, JP-A-60-23756.
It is a block diagram which shows the conventional inter-processor communication system shown by the 6th publication. In the figure, 10 is a processor A, 20
Is a processor B, 40 is a shared memory, and 300 and 301 are interrupt signals (or interrupt signal lines).

Next, the operation will be described. As shown in FIG. 4, the shared memory area 40 that can be accessed by either the processor A10 or the processor B20 is placed to exchange data. This shared memory area 40 is used for the processor A10 or the processor B2.
It can be used in the same way as from 0 to its own memory, and a predetermined area is divided into one for processor A10 or one for processor B20, an address is determined and allocated, and the instruction or state that the transmitting processor A10 wants to send to the other processor B20. Write the data of to the memory allocated to it. This is done just like a normal memory access. The transmitting processor writes the data and then sends an I / O command or the like to the receiving processor. The receiving processor sets the instruction of the transmitting processor as the cause of the interrupt of the receiving processor. Further, the receiving side processor immediately returns a response signal so that the transmitting side processor can immediately shift to the next processing, that is, in order to end the I / O command or the like. The receiving side processor may then read and process the data such as the instruction sent from the transmitting side at its own desired time. At this time, the transmitting side processor may be either the processor A10 or the processor B20 and can communicate in the same manner. Also, when data is transferred by the method described above, when the processing speed of both processors does not match (for example, one receiving processor has a lot of data to receive to the other receiving processor If you are busy with another process and do not have time to receive the data), you must confirm the data transfer. In this case, when the receiving processor completes the receiving side, the area is cleared (or a certain response pattern is written) to notify the transmitting processor that the data has not been processed yet. Therefore, if the communication area is not empty, the transmission side processor performs a process of waiting even if it has transmission data. By doing so, data loss due to the difference in processing speed between the transmitting processors can be avoided. FIG. 5 is a flow chart for explaining the above operation. In the figure, the transmission area and the reception area are the same address area on the common memory,
They are named the transmission area and the reception area depending on the direction of data flow. Further, even if the transmission side processor and the reception side processor are exchanged, if the transmission area (reception area of the other side) is divided for each processor, there is no data interference.

[0004]

Since the conventional interprocessor communication system is configured as described above, when transmitting data to a plurality of slave processors, the data must be transmitted sequentially for each processor. However, in the process of transmitting data at the same time, such as the process of synchronizing the times of a plurality of slave processors, the data is transmitted at a set time between the slave processors in order to sequentially transmit the data for each processor. There was a problem such as a time shift.

The present invention has been made in order to solve the above problems, and obtains an interprocessor communication system capable of simultaneously transmitting data from a master processor to a plurality of slave processors. The purpose is to

[0006]

An interprocessor communication system according to a first aspect of the present invention includes a memory accessible by a master processor and a slave processor, an interrupt generation unit for generating an interrupt on the slave processor on the master processor, A signal line for transmitting an interrupt to a plurality of slave processors and an interrupt controller for receiving an interrupt from a master processor are provided in each of the plurality of slave processors.

In the interprocessor communication system according to the second aspect of the invention, the master processor sets data in the memory, an interrupt notification step in which the master processor simultaneously generates interrupts to a plurality of slave processors, and each slave processor Each of them has an access step of detecting an interrupt and accessing the data in the memory.

[0008]

In the interprocessor communication system according to the first and second aspects of the invention, when data is transmitted from the master processor to a plurality of slave processors, the data for transmission is written in the memory and an interrupt from the master processor is generated. A plurality of slave processors simultaneously generate data, each slave processor receives an interrupt from the master processor, and reads the transmitted data from the memory, thereby simultaneously receiving the data from the master processor.

[0009]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 10 is a processor A which is a master processor, 12 is a CPU of this processor A10, 1
Reference numeral 4 is an interrupt generator of the processor A10, 15 is an interrupt controller of the processor A10, 20 is a processor B indicating one of a plurality of slave processors, 22 is a CPU of this processor B20, and 23 is readable / writable from the processor A10 or the processor B20. 2-PORT
A memory, 24 is an interrupt generator of the processor B20, and the output of the output is logically ORed and input to the interrupt controller 15. An interrupt controller 25 of the processor B20 receives the output of the interrupt generator 14. 301 is an interrupt signal line from the interrupt generator 14 to the interrupt controller 25, 302 is an interrupt signal line from the interrupt generator 24 to the interrupt controller 15, and 2-PORT in FIG.
An example of the configuration of the memory 23 is shown. 41 is a transmission flag of A, 4
Reference numeral 2 is an A transmission area (B reception area), 43 is a B transmission flag, and 44 is a B transmission area (A reception area).

Next, the operation will be described. FIG. 3 shows a flowchart when data is transmitted from the master processor to the plurality of slave processors. The process on the master processor side waits at step 101 for generation of data to be transmitted. In step 102, the transmission flag 41 of A of the 2-PORT memory 23 of the processor B20
If it is not checked that the empty pattern “0” is stored in, the step 101 is repeated. Step 103
2-PORT of the processor B20 to be transmitted
The data to be transmitted is written into the transmission area 42 of A of the memory 23. In step 104, the transmission flag 4 of A of the 2-PORT memory 23 of the processor B20 to be transmitted
The pattern "1" with data is written in 1, and the interrupt signal line 301 causes all processors B20 to generate an interrupt signal. In step 105, it is determined whether there is a response from the partner processor, which is the processor B2 to be transmitted.
It is checked that the empty pattern “0” is stored in the transmission flag 41 of A of the 2-PORT memory 23 of 0, and step 105 is repeated until all responses are received.
In the processing on the slave processor side, in step 111, the interrupt controller 25 senses the interrupt through the interrupt signal line 301, and the 2-P of the processor B20 is detected.
Whether or not there is a transmission is detected depending on whether or not the pattern "1" with data is written in the transmission flag 41 of A of the ORT memory 23. At step 112, the processor B20
The data in the transmission area 42 of A of the 2-PORT memory 23 is received. In step 113, processor B
Whether or not there is a transmission is detected depending on whether or not the pattern “1” with A in the 2-PORT memory 23 of 20 is written. By storing the empty pattern “0” in the transmission flag 41, the processor A10 is notified of the interrupt response.

As described above, in this embodiment, in the interprocessor communication system in the multiprocessor system including one master processor and a plurality of slave processors, means for causing the master processor to generate an interrupt to the plurality of slave processors, Means for receiving interrupts from a plurality of slave processors in a superimposed manner, each of the slave processors receiving a 2-PORT memory accessible from the master processor and the slave processor, and an interrupt from the master processor An inter-processor communication system has been described, which comprises means and means for generating an interrupt to the master processor, and in which data is simultaneously transmitted from the master processor to a plurality of slave processors.

Example 2. In the above embodiment, 2-PO
Although the example in which the RT memory 23 is installed for each of a plurality of slave processors is shown, one master memory and one shared memory accessible by the plurality of slave processors are provided, and a plurality of slave processors are provided on this one shared memory. An A transmission flag 41, an A transmission area 42, a B transmission flag 43, and a B transmission area 44 may be provided for each of them, and the same effect as that of the above-described embodiment is obtained.

Embodiment 3. Further, in the above embodiment, the case where the master processor and the slave processor are fixed is shown. However, since the master and the slave have the same configuration, the same processor can operate by arbitrarily changing the roles of the master and the slave. Is also possible.

[0014]

As described above, according to the first and second inventions, the master processor causes the plurality of slave processors to generate interrupts, and each of the plurality of slave processors receives the interrupt from the master processor. Since it is configured to do so, an inter-processor communication system capable of simultaneously transmitting data to a plurality of slave processors can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an interprocessor communication system according to an embodiment of the present invention.

2 of processor B according to one embodiment of the present invention; FIG.
FIG. 3 is a diagram showing a configuration example of a PORT memory.

FIG. 3 is a flowchart diagram when data is transmitted from a master processor to a plurality of slave processors according to an embodiment of the present invention.

FIG. 4 is a configuration diagram showing a conventional inter-processor communication system.

FIG. 5 is a flowchart of inter-processor communication according to a conventional example.

[Explanation of symbols]

 10 Processor A 12 A CPU 14 A interrupt generator 15 A interrupt controller 20 Processor B 22 B CPU 23 B 2-PORT memory 24 B interrupt generator 25 B interrupt controller 41 A transmission flag 42 A Transmission area 43 B transmission flag 44 B transmission area 301 A interrupt signal line 302 B interrupt signal line

Claims (2)

[Claims] 1. The following memory, a master processor,
Inter-processor communication method having a plurality of slave processors and signal lines (a) Memory accessed from master processor and slave processor, (b) Master processor having the following elements, (b1) Interruption to a plurality of slave processors An interrupt generation unit that generates a signal, (b2) a master CPU that sets data to be sent to a plurality of slave processors in a memory, (c) a slave processor having the following elements (c1) an interrupt that accepts an interrupt signal from the master processor A controller, (c2) a slave CPU that accesses data set in a memory based on acceptance of an interrupt signal from the interrupt controller, and (d) a signal line for transmitting the interrupt signal from the master processor to the interrupt controller of each slave processor. 2. An interprocessor communication method in which a master processor transmits data to a plurality of slave processors, including the following steps: (a) a setting step of setting data to be transmitted from a master processor to slave processors in a memory; b) an interrupt notification step in which the master processor simultaneously generates interrupts to a plurality of slave processors after the setting step, and (c) the slave processor senses the interrupt generated in the interrupt notification step and sets in the setting step. An access process for accessing data in memory.