JPH04164363A - Chip carrier - Google Patents
Chip carrierInfo
- Publication number
- JPH04164363A JPH04164363A JP29159190A JP29159190A JPH04164363A JP H04164363 A JPH04164363 A JP H04164363A JP 29159190 A JP29159190 A JP 29159190A JP 29159190 A JP29159190 A JP 29159190A JP H04164363 A JPH04164363 A JP H04164363A
- Authority
- JP
- Japan
- Prior art keywords
- glass epoxy
- semiconductor pellet
- epoxy substrate
- substrate
- epoxy resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000008188 pellet Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000004593 Epoxy Substances 0.000 claims abstract description 27
- 239000011521 glass Substances 0.000 claims abstract description 27
- 239000003822 epoxy resin Substances 0.000 claims abstract description 15
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 15
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はチップキャリアに関し、特にガラスエポキシ基
板上に半導体ペレットが搭載されて製造されるチップキ
ャリアに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a chip carrier, and particularly to a chip carrier manufactured by mounting semiconductor pellets on a glass epoxy substrate.
従来のチップキャリアは、第３図（ａ）、（ｂ）に示す
ように、４辺に外部との接続に使用される端面スルーホ
ールの電極１を有するガラスエポキシ基板２Ａ上に、半
導体ペレット３を接着剤でマウントし、Ａｕワイヤ４で
半導体ペレット３とガラスエポキシ基板２Ａ上の導体パ
ターンをワイヤボンディングして接続し、半導体ペレッ
ト３を保護する為にエポキシ樹脂５を塗布して形成され
ている。As shown in FIGS. 3(a) and 3(b), the conventional chip carrier has semiconductor pellets 3 mounted on a glass epoxy substrate 2A having electrodes 1 in end face through holes used for connection with the outside on four sides. is mounted with adhesive, the semiconductor pellet 3 and the conductor pattern on the glass epoxy substrate 2A are connected by wire bonding with Au wire 4, and epoxy resin 5 is applied to protect the semiconductor pellet 3. .
又は第４図（ａ）、（ｂ）に示すように、ガラスエポキ
シ基板２Ａ上に半導体ペレット３を搭載した後、半導体
ペレット３を囲むように樹脂枠６を取り付け、その後、
Ａｕワイヤ４で半導体ペレット３とガラスエポキシ基板
２Ａ上の導体パターンをワイヤボンディングし、半導体
ペレット３を保護する為のエポキシ樹脂５を樹脂枠６の
内に充てんをして形成されている。Alternatively, as shown in FIGS. 4(a) and 4(b), after mounting the semiconductor pellet 3 on the glass epoxy substrate 2A, attaching the resin frame 6 so as to surround the semiconductor pellet 3, and then,
The semiconductor pellet 3 and the conductor pattern on the glass epoxy substrate 2A are wire-bonded using Au wires 4, and the resin frame 6 is filled with epoxy resin 5 for protecting the semiconductor pellet 3.
上述した従来のチップキャリアでは、半導体ペレットを
２ケ搭載する場合は、チップキャリアの実装面積を２倍
以上にする必要があるため、小型化を図るのが困難であ
った。In the conventional chip carrier described above, when two semiconductor pellets are mounted, the mounting area of the chip carrier needs to be more than doubled, making it difficult to achieve miniaturization.
本発明のチップキャリアは、４辺に外部との接続に使用
される端面スルーホールの電極を有するガラスエポキシ
基板と、このガラスエポキシ基板の裏面に設けられた凹
部と、この凹部の内部に搭載された半導体ペレットとガ
ラスエポキシ基板の裏面を平坦化するために前記凹部に
充てんされたエポキシ樹脂と、前記ガラスエポキシ基板
の表面に搭載されエポキシ樹脂により封止された半導体
ペレットとを含んで構成される。The chip carrier of the present invention includes a glass epoxy substrate having end face through-hole electrodes on four sides used for connection with the outside, a recess provided on the back surface of this glass epoxy substrate, and a chip carrier mounted inside the recess. epoxy resin filled in the recess to flatten the back surface of the glass epoxy substrate, and a semiconductor pellet mounted on the surface of the glass epoxy substrate and sealed with the epoxy resin. .
次に本発明について図面を参照に説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の第１の実施例の平面図
及びＡ−Ａ線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along line A--A of a first embodiment of the present invention.
第１図（ａ）、（ｂ）のように、４辺に外部との接続に
使用される端面スルーホールの電極１を有し、且つ、裏
面が深さ約０．５ｍｍの凹部を有するガラスエポキシ基
板２のこの凹部に半導体ペレット３をマウントし、Ａｕ
ワイヤ４でワイヤボンディングを行う。その後、半導体
ペレット３を保護する為にエポキシ樹脂５を裏面が平ら
になるように充てんする。次にガラスエポキシ基板２の
表面に半導体ペレット３Ａをマウントし、Ａｕワイヤ４
でワイヤボンディングを行ったのち、半導体ペレット３
Ａを保護する為にエポキシ樹脂５を塗布する。As shown in FIGS. 1(a) and 1(b), the glass has electrodes 1 of end face through holes used for connection with the outside on its four sides, and has a recessed part with a depth of about 0.5 mm on the back surface. The semiconductor pellet 3 is mounted in this recess of the epoxy substrate 2, and the Au
Wire bonding is performed using wire 4. Thereafter, in order to protect the semiconductor pellet 3, an epoxy resin 5 is filled so that the back surface is flat. Next, the semiconductor pellet 3A is mounted on the surface of the glass epoxy substrate 2, and the Au wire 4 is mounted on the surface of the glass epoxy substrate 2.
After wire bonding, semiconductor pellet 3
Apply epoxy resin 5 to protect A.
このように構成された第１の実施例によれば、従来と表
面積の同じガラスエポキシ基板に２ケの半導体ペレット
３，３Ａを搭載することができる。According to the first embodiment configured in this way, two semiconductor pellets 3 and 3A can be mounted on a glass epoxy substrate having the same surface area as the conventional one.
第２図（ａ）、（ｂ）は本発明の第２の実施例の平面図
及びＢ−Ｂ線断面図である。FIGS. 2(a) and 2(b) are a plan view and a sectional view taken along the line B--B of a second embodiment of the present invention.
第１の実施例と同様にガラスエポキシ基板２の裏面の凹
部に半導体ペレット３を搭載し、エポキシ樹脂５で充て
んする。次にこのガラスエポキシ基板２上に半導体ペレ
ット３Ａを搭載し、その回りに樹脂枠６を取り付ける。Similarly to the first embodiment, semiconductor pellets 3 are mounted in the concave portion on the back surface of the glass epoxy substrate 2, and the concave portion is filled with epoxy resin 5. Next, a semiconductor pellet 3A is mounted on this glass epoxy substrate 2, and a resin frame 6 is attached around it.
その後、ワイヤホンディングを行い、エポキシ樹脂５を
樹脂枠６内に充てんし、表面を平らに形成する。Thereafter, wire bonding is performed to fill the resin frame 6 with epoxy resin 5 to form a flat surface.
このように構成された第２の実施例によれば、第１の実
施例と同一の効果の他に、表面を平らにすることにより
、自動実装が出来るという利点がある。According to the second embodiment configured in this way, in addition to the same effect as the first embodiment, there is an advantage that automatic mounting is possible by making the surface flat.
以上説明したように本発明は、４辺に外部との接続に使
用される端面スルーホールの電極を有するガラスエポキ
シ基板の裏面を凹状に形成して、裏面に半導体ベレット
搭載し、エポキシ樹脂を充てんして裏面を平らに形成す
ることにより、ガラスエポキシ基板の両面に半導体ペレ
ットを搭載−することが可能となり、従来半導体ペレッ
トを２ケ表面に搭載したチップキャリアと比較して、２
／３以下の実装面積で製造できるという効果がある。又
、１つのチップキャリアに２種類の半導体ペレットが搭
載できるので機能アップを図ることができるという効果
もある。As explained above, the present invention involves forming the back side of a glass epoxy substrate into a concave shape, which has electrodes for end face through holes used for connection with the outside on four sides, mounting a semiconductor pellet on the back side, and filling it with epoxy resin. By forming the back side flat, it is possible to mount semiconductor pellets on both sides of the glass epoxy substrate, which makes it possible to mount semiconductor pellets on both sides of the glass epoxy substrate.
It has the advantage that it can be manufactured with a mounting area of /3 or less. Furthermore, since two types of semiconductor pellets can be mounted on one chip carrier, there is also the effect that the functionality can be improved.
第１図（ａ）、（ｂ）及び第２図（ａ）、（ｂ）は本発
明の第１及び第１の実施例の平面図及び断面図、第３図
（ａ）、（ｂ）及び第４図（ａ）。
（ｂ）は従来のチップキャリアの平面図及び断面図であ
る。
１・・・電極、２，２Ａ・・・ガラスエポキシ基板、３
゜３Ａ・・・半導体ペレット、４・・・Ａｕワイヤ、５
・・・エポキシ樹脂、６・・・樹脂枠。1(a), (b) and 2(a), (b) are plan views and sectional views of the first and first embodiments of the present invention, and FIG. 3(a), (b) and FIG. 4(a). (b) is a plan view and a sectional view of a conventional chip carrier. 1... Electrode, 2, 2A... Glass epoxy substrate, 3
゜3A... Semiconductor pellet, 4... Au wire, 5
...Epoxy resin, 6...Resin frame.
Claims (1)
電極を有するガラスエポキシ基板と、このガラスエポキ
シ基板の裏面に設けられた凹部と、この凹部の内部に搭
載された半導体ペレットとガラスエポキシ基板の裏面を
平坦化するために前記凹部に充てんされたエポキシ樹脂
と、前記ガラスエポキシ基板の表面に搭載されエポキシ
樹脂により封止された半導体ペレットとを含むことを特
徴とするチップキャリア。A glass epoxy substrate with end face through-hole electrodes used for connection with the outside on four sides, a recess provided on the back side of this glass epoxy substrate, a semiconductor pellet mounted inside this recess, and a glass epoxy substrate. A chip carrier comprising: an epoxy resin filled in the recess to flatten the back surface of the substrate; and a semiconductor pellet mounted on the surface of the glass epoxy substrate and sealed with the epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2291591A JP2841831B2 (en) | 1990-10-29 | 1990-10-29 | Chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2291591A JP2841831B2 (en) | 1990-10-29 | 1990-10-29 | Chip carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04164363A true JPH04164363A (en) | 1992-06-10 |
| JP2841831B2 JP2841831B2 (en) | 1998-12-24 |
Family
ID=17770928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2291591A Expired - Lifetime JP2841831B2 (en) | 1990-10-29 | 1990-10-29 | Chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2841831B2 (en) |
-
1990
- 1990-10-29 JP JP2291591A patent/JP2841831B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2841831B2 (en) | 1998-12-24 |
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