JPH04162158A - Option memory and its arrangement system - Google Patents

Abstract

PURPOSE:To reduce the software load by performing the arrangement of an option memory by itself in a memory space at reception of an access. CONSTITUTION:A main body 7 monitors an RPLY signal 13 put on a bus through an address 0 with a memory reading or writing operation. If the signal 13 becomes active for the 3-unit time, i.e., the proper waiting time of a slot 4 after the bus received an access, the main body 7 increases the addresses in the least memory extension unit and then gives an access to the bus again to monitor the signal 13. When the arrangement is through all memories and an access is carried out over the upper limit of a memory space, no option board exists any more for return of the signal 13. Thus the software load is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an optional memory and its arrangement method.

[Conventional technology]

Conventional technology uses a system in which a dip switch on the optional memory specifies the memory address, or a system in which the dip switch is replaced with an IO boat, in order to locate the optional memory in the memory space of the main unit. In some cases, a method is used in which the start address of the memory is written to the I0 port by software.

[Problem to be solved by the invention]

The above-mentioned conventional technology has disadvantages in that it takes a lot of effort to operate the dip switch and requires software.

[Means to solve the problem]

The optional memory of the first invention is an optional memory for a computer having a bus for adding options.
A determination means for determining whether a response signal from another becomes active after a bus cycle is started until a waiting time specific to each option, and a response signal that is output on the bus according to instructions of the determination means. The device includes means for latching the address and determining its own address in the memory space, and means for returning a response signal when there is an access in the own memory space after the own memory address is determined.

The optional memory arrangement method of the second invention includes means for setting a memory address at address ○, means for reading or writing to the memory address, and waiting for 3 unit times after reading or writing to receive a response signal. a main body having means for incrementing the address in a minimum memory expansion unit when a non-active memory address setting routine is completed and a response signal becomes active within three unit times;
and means for issuing a response signal if there is no response signal from another device within a specific waiting time when a read or write is issued from the main body.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Slots 1 to 4 are for option boards, and memory 5 and 6 are currently installed in slots 1 and 3, and slot 2
, 4 are empty slots or have options other than memory installed.

When the main body 7 is started up, it performs read or write access to the memory space for each minimum memory expansion unit. If the access exceeds the memory implementation range of the main unit, a hash cycle is issued to the option bus. When the main body 7 activates the bus cycle start signal 11, the memory 5 installed in the slot 1 monitors the RPLY signal on the bus, and if there is no memory that returns the RPLY signal, the memory space is The option memory 5 latches the read address from the address line 12 and determines its own address within the memory space.

The main body 7 accesses the bus while incrementing the address for each minimum memory expansion unit, but when the upper limit of the memory space of the memory 5 is exceeded, the memory 5 no longer returns the RPLY signal. The memory 6 on the slot 3 also monitors the RPLY signal, and if the RPLY signal is inactive for 2 units of time after the bus cycle start signal 11 becomes active, the address currently being output on the address line is , determines that it is not allocated to either the memory space of slot 1 or the memory space of slot 2, latches the address from the address line 12, and determines its own address within the memory space.

The main body 7 further increments the address and stores the memory 6.
When the upper limit of the memory space is exceeded, slot 4 is empty and there is no memory to return RPLY. When the main body 7 confirms that there is no RPLY signal from the slot 4 after waiting for three unit times, it ends the bus cycle.

FIG. 2 is a block diagram showing details of the memories 5 and 6 shown in FIG. 1.

When the bus cycle start signal 11 becomes active,
The timer 9 operates and notifies the determination circuit 20 with a signal 14 of the time that has passed since the bus cycle start signal became active.

The determining means 20 observes that the signal 14 from the timer 9 is fixed to the slot number obtained from the slot number determining means 23, and that the RFLY signal 13 is inactive on the bus until the waiting time 15 is reached. If the RPLY signal 13 does not become active even after waiting the specific waiting time, the address is sent to the address latch means 21 by the signal 16.

instruct them to do so. The latched address is held as the start address of the optional memory, and at the same time, the capacity of this memory board is added to it, and the resultant address is passed to the end address holding means 24 as the end address.

The address comparison means 22 obtains the start address from the signal 17 and the end address from the signal 19, compares them with the address 12 on the bus, and activates the RPLY signal 13 if the address 12 is between the start address and the end address. Make it.

A flowchart of bus access on the main body side is shown in FIG.

Main unit 7 uses memory read or write from address O and monitors RPL, Y (g No. 13) on the bus. When the signal becomes active, the main body 7 increments the address by the minimum memory expansion unit, accesses the bus again, and monitors the RPLY signal 13.

When all memory allocation is completed and access exceeds the upper limit of the memory space, there will be no option board that returns the RPLY signal 13. If the RPLY signal 13 is inactive even after waiting for 3 units of time, which is the unique waiting time of the slot 4, the main body 7 lowers the bus access and ends the sequence of memory allocation.

Main body memory 8 is 1M byte, slot 1 memory is 1M
Byte, the memory of slot 3 is 1M byte, and the minimum memory expansion unit is 1M byte. The main body 7 first reads or writes data to memory atref address 0. In this case, the main body memory 8 returns the RPLY signal,
No bus cycles are issued on the option bus.

Next, the main body 7 increments the address by the minimum memory expansion unit IM byte and reads or writes data. Since the memory space of the main body memory 8 exceeds the upper limit of 1M bytes, a bus cycle occurs on the option bus, and when the memory 5 of slot 1 confirms that the RPLY signal 13 is inactive, it receives an address from the address line 12. It is latched and held as the start address, and at the same time, the address 2M-1, which is the sum of its own memory capacity of 111 Mbytes, is held as the end address, and the RPLY signal is returned on the option bus.

Further, the main body 7 increments the 1M address and accesses the memory address 2M. Since memory address 2M exceeds the upper limit address 2M-1 of the optional memory in slot 1, the (optional) memory 5 does not generate the RPLY signal 13.

The (optional) memory 6 of slot 3 confirms that the RPLY signal 13 is inactive for two time units, and the address on the option bus is set to slot 1. If it determines that the memory in slot 2 exceeds the upper limit, it latches the address, adds its own memory capacity IM, sets address 3M-1 as the end address, and returns the RPLY signal on the option bus. .

Next, when the main body 7 outputs a 3M memory address, the upper limit of all memories is exceeded, and there is no memory that returns the RPLY signal 13. When the main body 7 waits for three unit times and confirms that the RPLY signal 13 is not active, it ends the cycle.

The final memory layout diagram is shown in FIG.

〔Effect of the invention〕

As described above, the present invention arranges the optional memory itself in the memory space at the time the memory is accessed, so that the data switch can be eliminated and the software load can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing details of the memory shown in FIG. 1, FIG. 3 is a flowchart explaining the invention in detail, and FIG. 4 is a memory It is a layout diagram. 1 to 4...Slot, 5,6...Memory, 7...
Main unit, 8... Main unit memory.

Claims (1)

[Claims] 1. In the option memory of a computer having a bus for adding options, a response signal from another becomes active from the start of the bus cycle until the waiting time specific to each option. a means for determining whether or not the address is present in the memory space; a means for determining the own address in the memory space by latching the address appearing on the bus according to instructions from the determining means; and a means for determining the address in the memory space after the own memory address is determined and means for returning a response signal when there is an access within the space. 2. A means for setting a memory address to address 0, a means for reading or writing to the memory address, and a means for waiting 3 unit times after reading or writing and terminating the memory address setting routine if the response signal is inactive. , a main body that has means for incrementing the address in the minimum memory expansion unit if a response signal becomes active within 3 unit time, and a response from another until the unique waiting time when a read or write is issued from the main body. and means for issuing a response signal when there is no signal.