JPH05324538A - Bus controller - Google Patents

Abstract

PURPOSE:To enable plural devices to simultaneously and efficiently use a bus. CONSTITUTION:A bus controller 12 sets the byte access width, the word access width, or the long word access width as the use assignment width corresponding to the data access capability for access from registers REG1 and REG2 and memories MEM1 and MEM2 to a system bus BUS is set based on a signal BAC inputted from a CPU 11 and determines areas 1 to 4 of the system bus BUS, which registers REG1 and REG2 and memories SEM1 and MEM2 should use, based on this use assignment width and individually outputs access control signals to four buffers BUF1 to BUF4 through a control line 12a in accordance with this determination, thus controlling the transfer timings of data simultaneously transferred from registers REG1 and REG2 and memories MEM1 and MEM2 to areas 1 to 4 of the system bus BUS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus controller,
More specifically, the present invention relates to a bus control device that enables a plurality of devices to use a bus efficiently at the same time.

[0002]

2. Description of the Related Art A general-purpose bus is a bus (common bus) for connecting a processor board, a memory board, an input / output controller board and the like to construct a system. If a general-purpose bus is used, the system configuration can be changed on a board-by-board basis, and by dividing the functions into multiple boards, the system can be flexibly constructed and expanded according to the application. Recently, a 32-bit wide VME used in personal computers and workstations
(Versa Module Europea) buses, Multibus II, Nu buses, etc. have been proposed.

A general-purpose bus corresponding to such a 32-bit width microprocessor is not necessarily connected with only various boards and devices that are accessed with a 32-bit width, and has a data access capability of a 32-bit width or less. Boards and devices are often mixed and connected.

For example, as shown in FIG. 7, registers REG1 and REG2 and memories MEM1 and MEM2 connected to a BUS (bus) corresponding to a 32-bit wide CPU1.
Each device of 16 bits, 8 bits, 32 bits,
When the device has a 16-bit data access capability, each device is connected to the BUS by a data line suitable for the data access capability.

In FIG. 7, when the access state of each device is illustrated in FIG. 8, the access width actually used when each device accesses the bus BUS having a 32-bit width is, for example, in the register REG1, 16-bit width out of 32-bit width (D15 to D8 and D7 to D
0) is fixedly used and other devices (register REG
2 and memories MEM1 and MEM2) similarly have BUS 3
Data is exchanged with the CPU 1 by fixedly using the access width corresponding to the data access capability of the 2-bit width.

The access timing when each device uses the BUS is controlled by the CPU 1 or a bus controller connected to the CPU 1, and the access width actually used by each device is 32 bits or less as described above. However, each device is controlled as being accessed with a 32-bit width.

[0007]

However, in the bus controller for controlling the access timing of the device connected to such a conventional general-purpose bus, the above-mentioned FIG.
As shown in, B corresponding to the CPU 1 having a 32-bit width
Data access capability of each device connected to US is 32
Since the access width is less than or equal to 32 bits and the actually used access width of the 32-bit width is not fixed, the access width of the device is fixedly controlled so that the access width is 32 bits. If the number is smaller than the number, there is a problem that a large number of unused bits that are not used by the general-purpose bus occur.

Here, the state of occurrence of empty bits when the device accesses the bus will be described with reference to the system configuration example shown in FIG.

FIG. 9 shows a CPU 1, a CPU 2 and a memory ME.
A system configuration in which M1, MEM2, and an external storage device 3 are connected to a 32-bit wide system bus 4 is shown. The thick arrow lines in the figure respectively indicate the external device 4 to the memory MEM1.
Data transfer cycle to and from memory MEM2 to CPU
2 shows that a data transfer cycle to 2 is performed. The data transfer status on the system bus 4 in each transfer cycle is shown in FIG. 10A shows a WR signal output as a write command from the CPU1 to the memory MEM1 in the data transfer cycle from the external device 4 to the memory MEM1, and FIG. 10B shows the WR signal from the memory MEM2 to the CPU2. In the data transfer cycle to, the RD signal output as a read command from the CPU 2 from the memory MEM2 is shown. Assuming that the data width transferred by the WR signal and the RD signal output in each data transfer cycle is 16 bits as shown in FIG. 7C, and the upper side of the system bus 4 is used. As shown in FIG. 3D, unused bits are generated in the lower side of the system bus 4.

As described above, since the empty bit is generated for the access width actually used by the device connected to the bus, the utilization efficiency of the general-purpose bus is reduced and the data transfer efficiency is also reduced. was there.

An object of the present invention is to appropriately set an access width in accordance with the data access capability of a device connected to a bus to improve bus utilization efficiency and data transfer efficiency. ..

[0012]

The means of the present invention are as follows.

A byte access width, a word access width or a long word access width is set and set as a use allocation width when accessing the bus according to the data access capabilities of a plurality of devices connected to the bus having a predetermined data width. It is a bus control device or the like that controls the access timing from each device to the bus based on the utilization allocation width.

[0014]

The operation of the means of the present invention is as follows.

When a byte access width, a word access width or a long word access width is set as a use allocation width when accessing the bus according to the data access capabilities of a plurality of devices connected to the bus, it is set. The access timing from each device to the bus is controlled based on the usage allocation width.

Therefore, it is possible to simultaneously access the bus from two or more devices without fixing the access widths of a plurality of devices connected to the general-purpose bus, and the bus utilization efficiency and data transfer efficiency of the devices connected to the general-purpose bus. A bus control device that improves

[0017]

EXAMPLES Examples will be described below with reference to FIGS.

1 to 4 show a bus control unit (BCU) 1
2 is a diagram showing an example of No. 2 and is an example of being connected to the control device 10. FIG.

First, the structure will be described. FIG. 1 is a block diagram of the control device 10. In this figure, the control device 10 performs various arithmetic processes based on the programs in the ROM, and registers REG1 and R connected to the 32-bit system bus BUS for various arithmetic processes.
Data transfer processing is performed between the EG2 and the memories MEM1 and MEM2, and a bus access control signal (hereinafter referred to as a BAC signal) is used in the data transfer processing.
Connected to the CPU 11 for outputting the data to the bus control device 12 through the system bus BUS and the buffers BUF1 and BUF2, and registers REG1 and R for storing data necessary for various arithmetic processes in the data transfer process with the CPU11.
EG2, system bus BUS and buffers BUF3, B
Memories MEM1 and MEM2 that are connected through the UF4 and store data of various arithmetic processing results by data transfer processing with the CPU 11, and the system bus BUS and registers REG1 and REG by data transfer processing of the CPU11.
2 and the memories MEM1 and MEM2, buffers BUF1 to BUF4 for temporarily storing data transferred between them.
And the buffers BUF1 to BUF4 are controlled by the BAC signal output from the CPU 11 to control the system bus BUS, the registers REG1 and REG2, and the memories MEM1 and ME.
The bus control device 12 controls the data transfer timing with the M2.

The CPU 11 has a function of processing data up to 32 bits, performs various arithmetic processing based on a program in the ROM, and registers REG1 connected to the 32-bit system bus BUS at the time of various arithmetic processing. , REG2 and the memories MEM1 and MEM2, and registers REG1 and RE on the system bus BUS at the time of data transfer processing.
A bus access control signal (hereinafter, referred to as a BAC signal) that controls the bus access timing by monitoring how many bits of data are exchanged between which devices of the G2 and the memories MEM1 and MEM2 is sent to the bus control device 12. Output.

The registers REG1 and REG2 are connected to the system bus BUS through the buffers BUF1 and BUF2, respectively, store data necessary for various arithmetic processing executed by the CPU 11, and are controlled by the bus control device 12. Data stored in a later-described predetermined area of the system bus BUS is transferred according to the output timing of the BUF2.

The memories MEM1 and MEM2 are connected to the system bus B through buffers BUF3 and BUF4, respectively.
C connected to the US and transferred from a later-described predetermined area of the system bus BUS according to the input timing of the buffers BUF3 and BUF4 controlled by the bus control device C
It stores various calculation processing result data in the PU 11. The buffers BUF1 to BUF4, as shown in FIG.
A system bus BUS having a width of 32 bits is divided into 8 areas each having 4 areas 1 (D32 to D24) and 2 (D23 to D).
16), area 3 (D15 to D8), area 4 (D7 to
D0), the registers REG1 and REG2 and the data transfer lines of the memories MEM1 and MEM2 are connected to each of the areas 1 to 4. Buffer BUF connected to registers REG1 and REG2
1 and BUF2 have the same configuration, and in FIG.
The structure of the buffer BUF1 connected to G1 is shown,
The buffer BUF1 is each area 1 of the system bus BUS.
4 to 4 corresponding to output buffers OEN1 to OEN4. Output buffers OEN1 to OEN4 are controlled by access control signals input from the bus control device 12 through a control line 12a in FIG. The data stored in the register REG1 at the timing is transferred to the areas 1 to 4 of the system bus BUS.
Transfer every time. The buffers BUF3 and BUF4 connected to the memories MEM1 and MEM2 have the same configuration. The figure shows the configuration of the buffer BUF3 connected to the memory MEM1. The buffer BUF3 corresponds to the areas 1 to 4 of the system bus BUS. Input buffers IEN1 to IE
N4, input buffers IEN1 to IEN4
Are controlled by access control signals input from the bus control device 12 through the control line 12a, respectively, and the system bus BUS is controlled at the timing of the access control signals.
Data transferred for each of the areas 1 to 4 of the memory MEM1
Transfer to and store.

The bus control device 12 is denoted by B in FIG.
The buffers BUF1 to BU are connected to the CPU 11 by an AC line and are connected by a control line 12a in the drawing.
Connect to F4. The bus controller 12 registers the registers REG1 and REG2 and the memory MEM based on the BAC signal input from the CPU 11 through the BAC line 11a.
1. Byte access width, word access width or long word access width is set as the use allocation width according to the data access capability when MEM2 accesses the system bus BUS, and register REG1, REG2 and memory MEM1,
Areas 1 to 4 of the system bus BUS used by MEM2
And the buffers BUF1 to BUF according to this determination.
4 output buffers OEN1 to OEN4 and input buffers IEN1 to IEN4 individually to output access control signals through the control line 12a, and register REG1 and REG.
2 and memories MEM1 and MEM2 to system bus BU
It controls the transfer timing of the data to be transferred simultaneously onto the S areas 1 to 4.

Next, the operation of this embodiment will be described.

BAC from the CPU 11 to the bus controller 12
When the signal is output, in the bus controller 12, the byte access width, the word access width, or the long word access width is set as the usage allocation width of the system bus BUS according to the data access capabilities of the registers REG1 and REG2 and the memories MEM1 and MEM2. The system bus B that is set and is used by the registers REG1 and REG2 and the memories MEM1 and MEM2 based on the usage allocation widths
Areas 1 to 4 of the US are determined. Then, in the bus controller 12, the buffers BUF1 to BUF are sent according to this determination.
The access control signal is output to each of the output buffers OEN1 to OEN4 and the input buffers IEN1 to IEN4 in the F4, and the registers REG1 and REG2 and the memory MEM are output.
1, the transfer timing of data simultaneously transferred from the MEM 2 to the areas 1 to 4 of the system bus BUS is controlled.

The transfer timing process associated with the use allocation width setting of the system bus BUS in the bus control device 12 will be described with reference to the data transfer timing charts shown in FIGS.

FIG. 3A shows registers REG1 and REG2 set by the bus control device 12 and a memory MEM.
The data access widths of 1 and MEM2 are all word access widths (16-bit width), and access timings are set. In this figure,
The portions indicated by black bands in the access timing with and indicate access to the registers REG1 and REG2,
The hatched area indicates the memory MEM.
1 and MEM2 access, and FIG.
The same applies to (b) and FIG. 3 (c).

In the bus control unit 12, since the data access width set in the figure is the word access width and the 16-bit width, at the access timing in the figure, for example, area 1 of areas 1 to 4 of the system bus BUS is used. 2 (D31 to D24, D23 to D16) are assigned to the register REG1, and at the same time, areas 3 and 4 (D
15 to D8, D7 to D0) are allocated to the memory MEM1 and the output buffers OEN1 and OEN2 in the buffer BUF1 and the input buffers IEN3 and IEN4 in the buffer BUF3 are allocated to the allocated areas 1 to 4.
Are controlled by access control signals, and at the same time, the system bus BUS is accessed from two devices to transfer word data.

Further, at the access timing shown in the figure, the bus control unit 12 controls the system bus B, for example.
Areas 1 and 2 (D31 to D2) of US areas 1 to 4
4, D23 to D16) are assigned to the memory MEM2, and at the same time, areas 3 and 4 (D15 to D8, D7 to D).
0) is assigned to the register REG2, and the input buffers IEN1 and IEN2 in the buffer BUF4 and the output buffers OEN3 and OEN4 in the buffer BUF4 are controlled by the access control signal in accordance with the assigned areas 1 to 4, and two locations at the same time. The word bus is transferred by accessing the system bus BUS from this device.

In FIG. 3B, the data access width of the registers REG1 and REG2 set by the bus controller 12 is the word access width (16-bit width), and the memory ME
The data access width of M1 and MEM2 is the byte access width (8-bit width), and the access timing is set.

In the bus control unit 12, the data access width set in the figure is a word access width, a 16-bit width, a byte access width, and an 8-bit width. Therefore, at the access timing in the figure, for example, the system bus BU is used.
Areas 1 and 2 of S areas 1 to 4 (D31 to D2
4, D23 to D16) are assigned to the register REG1, and at the same time area 4 (D7 to D0) is stored in the memory MEM.
1 is assigned to the assigned area 1, 2,
Output buffer OEN in buffer BUF1 according to 4
1, OEN2 and input buffer I in buffer BUF3
EN4 is controlled by an access control signal, and at the same time, the system bus BUS is accessed from two devices to transfer word data and byte data.

At the access timing shown in FIG. 3, the bus controller 12 controls the system bus B, for example.
Areas 1 and 2 (D31 to D2) of US areas 1 to 4
4, D23 to D16) are assigned to the register REG2, and at the same time area 3 (D15 to D8) is stored in the memory ME.
Areas 1 to 3 assigned to M2
According to the output buffer OEN in the buffer BUF2
1, OEN2 and input buffer I in buffer BUF4
EN3 is controlled by an access control signal, and at the same time, two devices access the system bus BUS to transfer word data and byte data.

FIG. 3C shows the registers REG1 and REG2 set by the bus controller 12 and the memory MEM.
The data access widths of 1 and MEM2 are all byte access widths (8-bit width), and access timings are set.

In the bus control unit 12, since the data access width set in the figure is the byte access width and the 8-bit width, at the access timing in the figure, for example,
Area 1 (D among areas 1 to 4 of the system bus BUS
31-D24) are assigned to the register REG1 and at the same time area 2 (D23-D16) is stored in the memory MEM1.
The output buffer OEN1 in the buffer BUF1 and the input buffer IEN2 in the buffer BUF3 are controlled by the access control signal in accordance with the allocated areas 1 and 2, and the system bus BUS is simultaneously accessed from two devices. Byte data is transferred.

Further, at the access timing shown in the figure, the bus controller 12 controls the system bus B, for example.
Area 1 of US areas 1 to 4 (D31 to D24)
Is simultaneously allocated to the register REG2, and at the same time, the area 4 (D7 to D0) is allocated to the memory MEM2, and the buffer BU according to the allocated areas 1 and 4.
The output buffer OEN1 in the F2 and the input buffer IEN4 in the buffer BUF4 are controlled by the access control signal, and at the same time, the system bus BUS can be sent from two devices.
Is accessed and byte data is transferred.

The registers REG1 and REG2 and the memories MEM1 and MEM shown in FIGS.
Of course, the access areas of the areas 1 to 4 of the system bus BUS assigned according to the respective data access capacities 2 are not fixed and can be arbitrarily changed in the bus control device 12.

FIG. 4 outputs to the system bus BUS according to the usage allocation width of the system bus BUS set in the register REG1 and the usage allocation width of the system bus BUS set in other devices (register REG2 and memories MEM1 and MEM2). It shows an example of a combination of data.

In FIG. 4, when the use allocation width of the register REG1 is the long word access width (32-bit width), the data A to D are transferred in 8-bit parallel using all the areas 1 to 4 of the system bus BUS. Then, the use allocation width of the register REG1 becomes the word access width (1
6-bit width), when the allocation width used by other devices is also the word access width (16-bit width), the system bus B
8 using US Areas 1 and 2 and Areas 3 and 4 at the same time
Data A and B and data E and F are transferred in bit parallel. Therefore, as shown in another example of the combination of data output in the figure, if the use allocation width of the register REG1 is equal to or smaller than the word access width (16-bit width), the system bus BU corresponding to the use allocation width of another device.
S can be used simultaneously to change and transfer the combination of data to be output in 8-bit parallel, and the system bus B can be changed according to the data access capability of each device.
Areas 1 to 4 using the US can be arbitrarily changed without being fixed.

FIG. 5 is a view showing another embodiment of the bus control device, in which the bus control device 12 is replaced with the conventional one shown in FIG.
CPU1, CPU2, and memory ME similar to those shown in FIG.
In this example, M1, MEM2 and external storage device 3 are connected to a system configuration in which a 32-bit wide system bus 4 is connected.

In FIG. 5, the bus controller 12 is a CP
An access control signal for controlling the data transfer timing between the CPU1, CPU2, the external storage device 3 and the memories MEM1, MEM2 based on the BAC1 signal and the BAC2 signal as the bus access control signals input from the U1 and the CPU2, respectively. Is output to the CPU1 and the CPU2 through the control lines indicated by 12a and 12b in the figure.

For example, in FIG. 5, the thick arrow line in the figure
The figure shows that a data transfer cycle from the external device 4 to the memory MEM1 and a data transfer cycle from the memory MEM2 to the CPU2 are performed, and the BAC1 signal is input from the CPU1 to the bus controller 12 to execute these transfer cycles. If the BAC2 signal is input from the CPU 2 to the bus control device 12, the external storage device 3
Also, the use allocation width of the system bus 4 in each transfer cycle is determined based on the data access capability of the memories MEM1 and MEM2, and the access control signal is output to the CPU1 and CPU2. FIG. 6 shows a data transfer situation on the system bus 4 in each transfer cycle controlled by the access control signal.

In FIG. 6, (a) shows the CP in the data transfer cycle from the external device 4 to the memory MEM1.
The WR signal output as a write command from U1 to the memory MEM1 is shown. FIG. 7B shows the CPU2 in the data transfer cycle from the memory MEM2 to the CPU2.
Shows the RD signal output as a read command from the memory MEM2 from the memory MEM2, and the data width transferred by the WR signal and the RD signal output in each data transfer cycle is as shown in FIGS. , And 16 bits.

In FIG. 6, data is transferred from the external storage device 3 to the memory MEM1 by utilizing the upper side of the system bus 4 in FIG. In (d), the lower side of the system bus 4 is used in the same transfer cycle and the memory M
This shows that data transfer from the EM2 to the CPU2 is being performed.

Therefore, conventionally, the data transfer is executed between two or more devices at the same time by utilizing the vacant bit on the system bus 4 which occurs when the data transfer is performed in the different transfer cycles. Therefore, the bus utilization efficiency and the data transfer efficiency can be improved.

As described above, the bus controller 12
Is a register REG1, REG2 and memories MEM1, MEM2 based on the BAC signal input from the CPU 11.
Sets a byte access width, a word access width or a longword access width as a usage allocation width according to the data access capability when accessing the system bus BUS, and registers REG1, REG2 and memory MEM1 based on these usage allocation widths. , Areas 1 to 4 of the system bus BUS used by the MEM2 are determined, and the output buffers OEN1 to OEN4 and the input buffers IEN1 to 1 in the buffers BUF1 to BUF4 are determined according to the determination.
IEN4 individually outputs an access control signal through the control line 12a, and registers REG1 and REG2 and memories MEM1 and MEM2 to area 1 of the system bus BUS.
4 controls the transfer timing of data to be transferred simultaneously, it is possible to access the system bus BUS from a plurality of devices at the same time in the same transfer cycle to execute data transfer, thereby improving bus utilization efficiency and data transfer. The efficiency can be improved.

[0046]

According to the present invention, the byte access width is used as the utilization allocation width when the bus is accessed according to the data access capabilities of a plurality of devices connected to the bus.
Since the word access width or long word access width is set and the access timing from each device to the bus is controlled based on the set usage allocation width, each access width of multiple devices connected to the general-purpose bus is not fixed. Thus, the bus can be accessed from two or more devices at the same time, and a bus control device that improves the bus utilization efficiency and the data transfer efficiency of the device connected to the general-purpose bus can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a control device.

FIG. 2 is a circuit diagram of a buffer in the control device.

FIG. 3 is a timing chart for explaining a data transfer operation of a register and a memory controlled by a bus control device in the control device.

FIG. 4 is a timing chart for explaining a data transfer operation by a combination of a register controlled by a bus control device in the control device and another device.

FIG. 5 is a block diagram of the system.

FIG. 6 is a timing chart for explaining a data transfer operation by an external storage device and a memory controlled by a bus control device in the system, and a CPU and a memory.

FIG. 7 is a block diagram of a conventional system.

FIG. 8 is a timing chart for explaining a data transfer operation between a bus and a device in a conventional system.

FIG. 9 is a block diagram of a conventional system.

FIG. 10 is a timing chart for explaining a data transfer operation of a plurality of devices connected to a system bus in a conventional system.

[Explanation of symbols]

 10 control device 11 CPU 11a BAC line 12 bus control device 12a control line BUS system bus BUF1 to BUF4 buffer IEN1 to IEN4 input buffer OEN1 to OEN4 output buffer MEM1, MEM2 memory REG1, REG2 register

Claims (2)

[Claims] 1. A bus control device for controlling access timing when a plurality of devices connected to a bus having a predetermined data width respectively access the bus to transfer data, in accordance with a data access capability of each device. A bus control device, wherein a utilization allocation width for accessing the bus is set, and access timing from each device to the bus is controlled based on the set utilization allocation width. 2. A byte access width, a word access width, or a longword access width is set as a utilization allocation width when accessing the bus according to the data access capabilities of a plurality of devices connected to the bus having a predetermined data width, A bus control device for controlling access timing from each device to a bus based on a set use allocation width.